EE247 Lecture 22 Pipelined ADCs Combining the bits Stage implementation Circuits Noise budgeting Figures of merit (FOM) and trends for ADCs How to use/not use FOM Oversampled ADCs EECS 247 Lecture 22: Data Converters 2004 H. K. Page 1 Summary Pipelined A/D Converters V in B 1 bits 2 B1 B 2 B2 B 3 bits 2 B3 2 bits ADC ADC DAC - + Cascade of low resolution stages Stages operate concurrently- trades latency for conversion speed Throughput limited by speed of one stage fi Fast Errors and correction Built-in redundancy compensate for sub-adc inaccuracies Digital calibration compensates: Inter-stage gain inaccuracy Sub-DAC error Inter-stage gain nonlinearities EECS 247 Lecture 22: Data Converters 2004 H. K. Page 2
Combining the Bits Example: Three 2-bit stages, no redundancy B 1 B 1eff B 2 B 2eff B 3 V in Stage 1 Stage 2 Stage 3 6 2 D 1 2 D 2 2 D 3 D out + + 1/2 2 1/2 2 1 D out = D1 + D2 + 4 1 16 D 3 EECS 247 Lecture 22: Data Converters 2004 H. K. Page 3 Combining the Bits D 1 XX D 2 XX D 3 XX ------------ D out DDDDDD Only bit shifts No arithmetic circuits needed B 1 B 1eff B 2 B 2eff B 3 V in Stage 1 Stage 2 Stage 3 MSB LSB D out[5:0] EECS 247 Lecture 22: Data Converters 2004 H. K. Page 4
Combining the Bits Example: Three 2-bit stages, one bit redundancy in stages 1 and 2 B 1 =3 B 1eff B 2 =3 B 2eff B 3 V in Stage 1 Stage 2 Stage 3 8 Wires??? 6 Wires D out[5:0] EECS 247 Lecture 22: Data Converters 2004 H. K. Page 5 Combining the Bits 1 D out = D1 + D2 + 4 1 16 D 3 B 1 =3 B 1eff D 1 XXX D 2 XXX D 3 XX ------------ D out DDDDDD B 2 =3 B 2eff Bits overlap Need adders B 3 V in Stage 1 Stage 2 Stage 3 HADD HADD FADD HADD HADD D out[5:0] EECS 247 Lecture 22: Data Converters 2004 H. K. Page 6
Stage Implementation CLK φ 1 φ 2 φ 1... φ 1 φ 2 acquire convert convert acquire...... V in Stage 1 Stage 2 Stage n V in T/H +- G V res ADC DAC Each stage needs T/H hold function Track phase: Acquire input/residue from previous stage Hold phase: sub-adc decision, compute residue EECS 247 Lecture 22: Data Converters 2004 H. K. Page 7 Stage Implementation V in T/H T/H +- G V res T/H ADC DAC Usually no dedicated T/H amplifier in each stage (Except first stage why?) T/H implicitely contained as passive samplers in stage building blocks EECS 247 Lecture 22: Data Converters 2004 H. K. Page 8
Stage Implementation V in T/H + - G V res T/H ADC DAC MDAC Multiply-DAC-subtract function can be lumped into a single switched capacitor circuit "MDAC" EECS 247 Lecture 22: Data Converters 2004 H. K. Page 9 1.5 Bit Stage Implementation Ref: A. Abo, "Design for Reliability of Low- voltage, Switched-capacitor Circuits," UCB PhD Thesis, 1999 EECS 247 Lecture 22: Data Converters 2004 H. K. Page 10
1.5 Bit Stage Implementation Ref: A. Abo, "Design for Reliability of Low- voltage, Switched-capacitor Circuits," UCB PhD Thesis, 1999 EECS 247 Lecture 22: Data Converters 2004 H. K. Page 11 Stage Scaling Example: Pipeline using 1-bit eff stages V in Stage 1 Stage 2 Stage 3 C 1 /2 C 2 /2 C 3 /2 V in C 1 Gm C 2 Gm C 3 Gm Total input referred noise power: N tot 1 1 1 kt + + +... C1 4C2 16C3 EECS 247 Lecture 22: Data Converters 2004 H. K. Page 12
Stage Scaling C 1 /2 C 2 /2 C 3 /2 V in C 1 Gm C 2 Gm C 3 Gm N tot 1 1 1 kt + + +... C1 4C2 16C3 If we make all caps the same size, backend stages contribute very little noise Wasteful, because Power ~ Gm ~ C EECS 247 Lecture 22: Data Converters 2004 H. K. Page 13 Stage Scaling C 1 /2 C 2 /2 C 3 /2 V in C 1 Gm C 2 Gm C 3 Gm N tot 1 1 1 kt + + +... C1 4C2 16C3 How about scaling caps down by 2 2 =4x per stage? Same amount of noise from every stage All stages contribute significant noise Noise from first few stages must be reduced Power ~ Gm ~ C goes up! EECS 247 Lecture 22: Data Converters 2004 H. K. Page 14
Stage Scaling Optimum capacitior scaling lies approximately midway between these two extremes Ref: D. W. Cline, P.R Gray "A power optimized 13-b 5 MSamples/s pipelined analog-to-digital converter in 1.2um CMOS," JSSC 3/1996 EECS 247 Lecture 22: Data Converters 2004 H. K. Page 15 Stage Scaling Power minimum is "shallow" Near optimum solution in practice: Scale capacitors by stage gain E.g. for effective stage resolution of 1bit (Gain): C/2 C/4 C/8 V in C Gm C/2 Gm C/4 Gm EECS 247 Lecture 22: Data Converters 2004 H. K. Page 16
Stage Scaling Ref: D. W. Cline, P.R Gray "A power optimized 13-b 5 MSamples/s pipelined analog-to-digital converter in 1.2um CMOS," JSSC 3/1996 EECS 247 Lecture 22: Data Converters 2004 H. K. Page 17 How Many Bits Per Stage? Many possible architectures E.g. B 1eff, B 2eff =1,... Vs. B 1eff =1, B 2eff =1, B 3eff =1,... Complex optimization problem, fortunately optimum tends to be shallow... Qualitative answer: Maximum speed for given technology Use small stage resolution (large feedback factor) Maximum power efficiency for fixed, "low" speed Try higher resolution stages Can help alleviate matching requirements in front-end Ref: Singer VLSI 96, Yang, JSSC 12/01 EECS 247 Lecture 22: Data Converters 2004 H. K. Page 18
Two State-of-the-Art Implementations Reference Bits Architecture SNR Speed Power Yang (JSSC 12/2001) 12 3-1-1-1-1-1-1-3 ~70dB 75MS/s 340mW Loloee (ESSIRC 2002) 12 1-1-1-1-1-1-1-1-1-1-2 ~66dB 80MS/s 260mW EECS 247 Lecture 22: Data Converters 2004 H. K. Page 19 ADC Figures of Merit Objective: Want to compare performance of different ADCs Can use FOM to combine several performance metrics to get one single number What are reasonable FOM for ADCs? How can we use and interpret them? Trends? EECS 247 Lecture 22: Data Converters 2004 H. K. Page 20
ADC Figures of Merit FOM 2 1 = f s ENOB This FOM suggests that adding a bit to an ADC is just as hard as doubling its bandwidth Is this a good assumption? Ref: R.H. Walden, "Analog-to-digital converter survey and analysis," IEEE J. Selected Areas Comm., April 1999 EECS 247 Lecture 22: Data Converters 2004 H. K. Page 21 Survey Data 1bit/Octave Ref: R.H. Walden, "Analog-to-digital converter survey and analysis," IEEE J. Selected Areas Comm., April 1999 EECS 247 Lecture 22: Data Converters 2004 H. K. Page 22
ADC Figures of Merit FOM 2 = fs 2 Power ENOB Sometimes inverse of this metric is used In typical circuits power ~ speed, FOM 2 captures this tradeoff correctly How about power vs. ENOB? One more bit 2x in power? Ref: R.H. Walden, "Analog-to-digital converter survey and analysis," IEEE J. Selected Areas Comm., April 1999 EECS 247 Lecture 22: Data Converters 2004 H. K. Page 23 ADC Figures of Merit One more bits means... 6dB SNR, 4x less noise power, 4x bigger C Power ~ Gm ~ C increases 4x Even worse: Flash ADC Extra bit means 2x number of comparators Each of them needs double precision Transistor area 4x, Current 4x to keep same current density Net result: Power increases 8x EECS 247 Lecture 22: Data Converters 2004 H. K. Page 24
ADC Figures of Merit FOM 2 seems inappropriate, but somehow still standard in literature, papers "Tends to work" because: Not all power in an ADC is "noise limited E.g. Digital power, biasing circuits, etc. Avoid comparing different resolution ADCs using FOM 2! EECS 247 Lecture 22: Data Converters 2004 H. K. Page 25 ADC Figures of Merit FOM = 3 Power Speed Compare only power of ADCs with approximately same ENOB Useful numbers: (state-of-the-art): 10b (~9 ENOB) ADCs: 1 mw/msample/sec 12b (~11 ENOB) ADCs: 4 mw/msample/sec EECS 247 Lecture 22: Data Converters 2004 H. K. Page 26
10-Bit ADC Power EECS 247 Lecture 22: Data Converters 2004 H. K. Page 27 12-Bit ADC Power EECS 247 Lecture 22: Data Converters 2004 H. K. Page 28
1.0E+12 Performance Trend Bandwidth x Resolution [Hz-LSB] 1.0E+11 1.0E+10 2x/5 years 1.0E+09 1985 1990 1995 2000 2005 EECS 247 Lecture 22: Data Converters 2004 H. K. Page 29 The Dream Transceiver "Software Radio" e.g.: SNR 100dB BW 30MHz Ref: Schreier, "ADCs and DACs: Marching Towards the Antenna," GIRAFE workshop, ISSCC 2003 EECS 247 Lecture 22: Data Converters 2004 H. K. Page 30
ADC for Software Radio Bandwidth x Resolution [Hz-LSB] 1.0E+13 1.0E+12 1.0E+11 1.0E+10 Software Radio Poulton, ISSCC 2003, Power=10W! 1.0E+09 1985 1990 1995 2000 2005 EECS 247 Lecture 22: Data Converters 2004 H. K. Page 31 Today's Transceiver... Ref: Schreier, "ADCs and DACs: Marching Towards the Antenna," GIRAFE workshop, ISSCC 2003 EECS 247 Lecture 22: Data Converters 2004 H. K. Page 32
Oversampled ADCs Why oversampling? Pulse-count modulation Sigma-delta modulation 1-Bit quantization Quantization error spectrum SQNR analysis EECS 247 Lecture 22: Data Converters 2004 H. K. Page 33 The Case for Oversampling Nyquist sampling: Signal f s B Freq narrow transition AA-Filter f s >2B +δ Sampler Nyquist ADC DSP Oversampling: Signal f s >> f N?? B Freq wide transition AA-Filter f s = Mf N Sampler Oversampled ADC DSP Nyquist rate f N = 2B Oversampling rate M = f s /f N >> 1 EECS 247 Lecture 22: Data Converters 2004 H. K. Page 34
Oversampled Converters Antialiasing EECS 247 Lecture 22: Data Converters 2004 H. K. Page 35 Oversampling Benefits Trades speed for resolution Relaxed transition band requirements for analog anti-aliasing filters Reduced baseband quantization noise power Utilizes low cost, low power digital filtering EECS 247 Lecture 22: Data Converters 2004 H. K. Page 36
Oversampled Converters Baseband Noise For a quantizer with step size and sampling rate f s : Quantization noise power distributed uniformly across Nyquist bandwidth (f s /2) Power spectral density: 2 2 e 1 N(f) e = = fs 12 fs Noise is aliased into the Nyquist band f s /2 to f s /2 EECS 247 Lecture 22: Data Converters 2004 H. K. Page 37 Oversampled Converters Baseband Noise fb fb 2 1 SB = N(f)df e = df fb f 12 f B s 2 2fB = 12 f s where for fb = f s /2 2 SB0 = 12 2fB SB0 SB = SB0 = f s M fs wherem = = oversampling ratio 2f B EECS 247 Lecture 22: Data Converters 2004 H. K. Page 38
Oversampled Converters Baseband Noise 2fB SB0 SB = SB0 = f s M fs wherem = = oversampling ratio 2f B 2X increase in M 3dB reduction in SB ½ bit increase in resolution/octave oversampling Greater improvement in resolution: Embed quantizer in a feedback loop Predictive (delta modulation) Noise shaping (sigma delta modulation) EECS 247 Lecture 22: Data Converters 2004 H. K. Page 39 Pulse-Count Modulation V in (kt) Nyquist ADC 0 1 2 t/t V in (kt) Oversampled ADC, M = 8 0 1 2 t/t Mean of pulse-count signal approximates analog input! EECS 247 Lecture 22: Data Converters 2004 H. K. Page 40
Pulse-Count Spectrum Magnitude Frequency, f / f s Signal: low frequencies, f < B << f s Quantization error: high frequency, B f s / 2 Separate with low-pass filter! EECS 247 Lecture 22: Data Converters 2004 H. K. Page 41 Oversampled ADC Predictive Coding v IN + _ ADC d OUT Predictor Quantize the difference signal rather than the signal itself Smaller input to ADC Buy dynamic range Only works if combined with oversampling 1-Bit digital output Digital filter computes average N-Bit output EECS 247 Lecture 22: Data Converters 2004 H. K. Page 42
Oversampled ADC Signal B Freq wide transition Analog AA-Filter f s = Mf N Sampler E.g. Pulse-Count Modulator Modulator 1-Bit Digital f s = M f N Decimator narrow transition Digital AA-Filter N-Bit Digital f s = f N+ δ DSP Decimator: Digital (low-pass) filter Removes quantization error for f > B Provides most anti-alias filtering Narrow transition band, high-order 1-Bit input, N-Bit output (essentially computes average ) EECS 247 Lecture 22: Data Converters 2004 H. K. Page 43 Modulator Objectives: Convert analog input to 1-Bit pulse density stream Move quantization error to high frequencies f >>B Operates at high frequency f s >> f N M = 4 256 (typical) Better be simple Σ = Σ Modulator EECS 247 Lecture 22: Data Converters 2004 H. K. Page 44
Sigma- Delta Modulators Analog 1-Bit Σ modulators convert a continuous time analog input v IN into a 1-Bit sequence d OUT f s v IN + _ H(z) d OUT DAC Loop filter 1b Quantizer (a comparator) EECS 247 Lecture 22: Data Converters 2004 H. K. Page 45 Sigma-Delta Modulators The loop filter H can be either a SC or continuous time SC s are easier to implement and scale with the clock rate Continuous time filters provide anti-aliasing protection Can be realized with passive LC s at very high frequencies f s v IN + _ H(z) d OUT DAC EECS 247 Lecture 22: Data Converters 2004 H. K. Page 46
1 st Order Σ Modulator In a 1 st order modulator, simplest loop filter an integrator H(z) = z -1 1 z -1 v IN + _ d OUT DAC EECS 247 Lecture 22: Data Converters 2004 H. K. Page 47 1 st Order Σ Modulator Switched-capacitor implementation f 1 f 2 - f 2 d OUT 1,0 V i + V R -V R EECS 247 Lecture 22: Data Converters 2004 H. K. Page 48
1 st Order Σ Modulator v IN + -D/2 v IN +D/2 _ dout -D/2 or +D/2 DAC Properties of the first-order modulator: Analog input range is equal to the DAC reference The average value of d OUT must equal the average value of v IN +1 s (or 1 s) density in d OUT is an inherently monotonic function of v IN linearity is not dependent on component matching Alternative multi-bit DAC (and ADCs) solutions reduce the quantization error but loose this inherent monotonicity EECS 247 Lecture 22: Data Converters 2004 H. K. Page 49 1 st Order Σ Modulator Analog input - /2 V in + /2 Tally of quantization error 1 X 2 Q 1-Bit quantizer 3 Y z -1 Sine Wave 1-z -1 Integrator Comparator 1-Bit digital output stream, -1, +1 Instantaneous quantization error Implicit 1-Bit DAC + /2, - /2 ( = 2) EECS 247 Lecture 22: Data Converters 2004 H. K. Page 50
1 st Order Modulator Signals 1.5 1 1st Order Sigma-Delta X Q Y X analog input Q tally of q-error Y digital/dac output Amplitude 0.5 0-0.5 Mean of Y approximates X -1 T = 1/f s = 1/ (M f N ) -1.5 0 10 20 30 40 50 60 Time [ t/t ] EECS 247 Lecture 22: Data Converters 2004 H. K. Page 51 Σ Modulator Characteristics Quantization noise and thermal noise (KT/C) distributed over fs/2 to +fs/2 Total noise reduced by 1/M Very high SQNR achievable (> 20 Bits!) Inherently linear for 1-Bit DAC Quantization error independent of component matching Limited to moderate to low speed EECS 247 Lecture 22: Data Converters 2004 H. K. Page 52