Desgn and Implementaton of DDFS Based on Quas-lnear Interpolaton Algorthm We Wang a, Yuanyuan Xu b and Hao Yang c College of Electroncs Engneerng, Chongqng Unversty of Posts and Telecommuncatons, Chongqng 400065, Chna. Abstract a 935549301@qq.com, b 68400639@qq.com, c 369349077@qq.com In ths paper, a quas-lnear nterpolaton algorthm whch can be appled on DDFS s proposed. And the hardware desgn s acheved on FPGA. The core block of DDFS s the phase-to-sne mapper (PSM). The advantages and dsadvantages of the dfferent PSM algorthms s dscussed. The pece-wse fttng algorthm for sne wave curve utlzng lnear functons and parabolc functons, whch mprovng algorthm precson and decreasng the algorthm complexty effetely. The algorthm s useful to mprove the speed of the hardware. The fttng result s analyzed wth MATLAB. Accordng to the crcut performance requrements, the polynomal coeffcents are got. The Altera's Cyclone II devce s used for mplementaton. The expermental results show that: the frequency resoluton of DDFS s as hgh as 7.45e-7Hz, and the spectral purty s hgh, ts SFDR value s -94dBc. Keywords Drect Dgtal Frequency Syntheszer(DDFS); Quas-lnear nterpolaton algorthm; FPGA. 1. Introducton Dgtal Drect Frequency Synthess (DDFS) technology was proposed by J. Trency [1] n 1971 and s a new dgtal frequency synthess method [] based on phase concept. Drect smulaton frequency synthess and phase-lock lnk frequency synthess (PLL [3]), are also the key technologes to realze all-dgtal equpment []. Compared wth tradtonal frequency synthess technques, DDFS has the advantages of short swtchng frequency, hgh frequency resoluton, and contnuous phase varaton [4], makng DDFS wdely used n radar, software defned rado (SDR), communcatons, bology Medcal testng equpment and other felds [4]. Snce DDFS technology was put forward, domestc and foregn scholars have been perfectng DDFS theory contnuously, and ntroduced varous algorthms, whch are manly dvded nto four types: angle decomposton algorthm [6], sne ampltude compresson algorthm [6][7], angle rotaton algorthm [8], polynomal approxmaton algorthm [1]. Angle decomposton algorthm [6] s based on trgonometrc approxmaton formula trgonometrc functon expanson, and then dfferent sectons of the ROM correspondng to dfferent look-up table [1]. Ths method s ntutve but s lmted by the trgonometrc denttes and approxmaton formulas and s dffcult to angle decompose. Sne Ampltude Compresson Algorthm [1] [6] [7] reduces ROM memory by storng an error functon n the ROM look-up table. The method s smple n structure but requres the ntroducton of a ROM look-up table for storng error correcton functons. The above two methods are all based on the DDFS of the ROM look-up table. However, as the word length of the DDFS phase accumulator ncreases, the sze of the ROM look-up table can be very large. The crcut desgn has the dsadvantages of hgh power consumpton, slow speed and dffculty n mplementaton. Therefore, n recent years, the desgn of DDFS has focused on reducng the ROM look-up table sze and even replacng the ROM look-up table. So there are angle rotaton algorthm and polynomal approxmaton algorthm. 10
Angle rotaton algorthm [8] s manly based on CORDIC algorthm [1], ths method can fundamentally reduce the ROM look-up table capacty or even replace the ROM look-up table, but the delay, the system operatng frequency s low, the output waveform Small bandwdth [9]. In order to overcome the shortcomngs of the above three methods, the polynomal approxmaton algorthm s proposed [4], that s, from the phase pont of vew, through the pece-wse polynomal calculaton, the synthess of the requred frequency sne wave. The method acheves hgh purty of DDFS spectrum, low power consumpton and hgh samplng precson. It can be dvded nto three categores: frst-order polynomal approxmaton algorthm [4] [5], second-order polynomal approxmaton algorthm [] and hgher-order polynomal approxmaton algorthm. Ths paper ntends to use a new class of lnear polynomal algorthm to reduce the complexty of the algorthm, whle ensurng hgh accuracy. And the algorthm on the FPGA hardware desgn. The frst secton of ths artcle analyzes the workng prncple of DDFS and the lmtatons of tradtonal algorthms. The second secton analyzes the lnear nterpolaton algorthm. The thrd secton dscusses the FPGA desgn of the algorthm. Concluded the concluson.. DDFS structure and workng prncple A complete DDFS system conssts of phase-accumulator (PAC), phase-to-sne mapper (PSM), dgtal to analog converter (DAC) and low The pass flter (LPF) four parts consttute [1] [] [4] [5], the output s a sne wave. The block dagram shown n Fg. 1, the nput and output sgnals are defned n Table 1 below. The proposed DDFS part clk reset scan_enable L Phase accumulator (PAC) W W- Phase-tosne mapper (PSM) D dataout vald_out DAC LPF Fg. 1 DDFS block dagram Table 1 Defnton of nput, output sgnal Sgnal Defnton Frequency control word, whch s the cumulatve PAC step clk System clock reset System reset sgnal scan_enable Enable sgnal, the system to work properly when set 1 dataout Output dgtal sne wave sequence vald_out Output vald flag Under the control of the L-bt frequency control word () and the reference clock (clk), the PAC generates a L-bt dgtal lnear phase sequence and then undergoes sne-wave phase-ampltude converson through the PSM to generate a dscrete sequence of snusodal wave forms. It s then converted to an analog waveform by a dgtal-to-analog converter (DAC) and fnally smoothed by a low-pass flter (LPF). Ths s the basc workng prncple of DDFS. 3. Quas-lnear nterpolaton algorthm Because the sne wave symmetry for the deal sne curve, n the range [ 0, ], the closer to 0 closer to a straght lne. Curves throughout the range can be ftted pece-wse by lnear functons and polynomals. Through the analyss, t s found that n the range [ 0, ], the boundary between the lnear and parabolc polynomal segments s 3 4 [], that s, n the range [ 0, 8] of lnear segment, the 11
segment s ftted by the lnear equaton y a x c whle the range [ 8, ] s ftted by the parabola equaton y a x b x c, as shown n Fg.. The advantage of ths method s that the computatonal complexty s lower than that of pure parabolc nterpolaton, and the accuracy of the approxmate precson s hgher than the lnear nterpolaton [4]. The core of the pece-wse lnear nterpolaton s the determnaton of the polynomal nterpolaton method, whch determnes the error of fttng the sne wave wth respect to the standard sne wave and thus affects the spectral purty of the output [5]. Algorthm research should take nto account the complexty of the calculaton and spectral purty. The basc nterpolaton method ncludes lnear nterpolaton method, parabola nterpolaton method and lnear nterpolaton method []. There are two knds of segmentaton methods: unform and non-unform [4] [5]. Lnear nterpolaton method Parabolc nterpolaton method Fg. Quas-lnear nterpolaton Fg.3 Lnear nterpolaton error curve of 16 average segments Accordng to the lterature [4], we can see that the snusodal wave wth good spectral purty can be obtaned when the 16 segments are evenly dvded by pece-wse lnear nterpolaton, whch s about 90dBc. As a reference, wth MATLAB fttng, we can fnalze the DDFS desgn of ths cuttng method. We know that under dfferent splttng condtons, the error between the ftted sne wave and the deal sne wave s dfferent, and the sze of the error value determnes the spectral purty of the output sne wave. It can be seen from Fgure 3, there s a certan error between the ftted sne wave and the standard sne wave. In order to determne our segmentaton method, we frst ft the sne wave by dvdng the 16 segments n the lterature [4], and get the curve of the error under ths segmentaton method, as shown n Fg.3. As can be seen from Fg. 3, when usng the lnear nterpolaton method to dvde the sne wave nto a 16-hour average, the maxmum error between the ftted waveform and the deal sne wave s 4 approxmately 8 10. Takng ths value as a reference, the lnear nterpolaton method s used to ft the sne wave. After MATLAB fttng, the fnal determnaton of ths DDFS desgn cuttng method. That s dvded nto 4 sectons n the secton [ 0, 8], usng lnear nterpolaton method, the nterval s 3 ; [ 8, ] secton s dvded nto 4 sectons, usng parabolc nterpolaton method, the nterval s 3 3. As shown n Fg. 4: Lnear nterpolaton method(m1=4) Parabolc nterpolaton method(m=4) Fg. 4 Ths proposed quas-lnear nterpolaton Fg. 5 The proposed nterpolaton error curve 1
Regster 1's Complementer 's Complementer In other words, usng quas-lnear nterpolaton method, we can cut the 8 segments can be compared to the lnear nterpolaton method to cut 16 segments s also close to the deal sne wave waveform. And based on the above nterpolaton sne wave and deal sne wave error curve shown n Fg. 5. It can be seen from Fg. 5 that the maxmum error s, and that the error between the ftted sne wave and the deal sne wave usng the above lnear nterpolaton method s much smaller. Table shows the approxmate polynomal coeffcents of each segment. Table Approxmatons of polynomal coeffcents n each sub-secton Coeffcents a b c 1 0.9985-0.0000 0.9889-0.0010 3 0.9698-0.0049 4 0.9413-0.0133 5-0.566 1.1330-0.08 6-0.3699 1.874-0.0758 7-0.4513 1.4456-0.159 8-0.4938 1.553-0.199 8 4. Desgn of DDFS Crcut Based on Lnear Interpolaton Method In a DDFS system, DACs and LPFs are mplemented by exstng devces, and the PAC and PSM sectons are desgned n ths paper. PAC s the most basc part of DDFS and conssts of an L-bt adder and an L-bt regster cascaded. Under the acton of the clock clk, the s added n steps, generatng a full-scale overflow [4]. PSM s the core part of DDFS. The tradtonal PSM module uses ROM look-up table to realze the sne ampltude correspondng to the phase of snusodal waveform stored n ROM. Under clock control, the phase sequence of PAC output s addressed to obtan the correspondng ampltude Value Sequence [9]. However, the capacty of ROM ncreases exponentally wth the ncrease of PAC bt wdth [7]. Integratng such a large capacty ROM on a DDFS chp can ncrease the power consumpton of the chp, ncrease the chp area, and slow down the operaton speed [ 9]. Ths paper does not use ROM DDFS structure lnear nterpolaton algorthm [5], nstead of ROM memory-based look-up table, the phase of the sne wave ampltude converson, n order to acheve the need to reduce hardware costs [5]. Accordng to the symmetry of the sne wave, the frst quadrant waveform can be nverted symmetrcally to obtan a complete sne wave. Therefore, two complementers are used n the crcut to acheve waveform symmetry nverson. In ths desgn, wth the most sgnfcant bt (MSB1) and second most sgnfcant bt (MSB) as the symmetrcal flp control bt. Therefore, ths part of the desgn of the DDFS block dagram shown n Fg. 6. Phase-to-sne ampltude converter for sne phase-ampltude converson module. Phase accumulator(pac) Phase-to-sne mapper(psm) L W W- Phase-tosne ampltude converter MSB MSB1 Fg. 6 The proposed DDFS block dagram 13
In the desgn of DDFS, the phase truncaton technque s usually used. That s, the hgh W bt of the PAC output s taken as the nput of the PSM, whch can greatly reduce the computatonal complexty of the PSM part and have lttle effect on the spectral purty of the output sne wave, That s, n Fg. 6, L> W. In the crcut structure part of the phase-to-sne ampltude converter, accordng to the dscusson of the algorthm above, there s a multplcaton and square operaton n the desgn, and the multplcaton of the multpler can slow the speed of the crcut, So we consder usng shfters and adders nstead of very large multplers. When the equaton y a x b x c of the crcut s mplemented, takng nto account the form rewrtten nto y a ( x b c can reduce the multplcaton, we wll make the above coeffcents changed accordngly. At the same tme, the frst 3 ~ 5 hgh MSB3, MSB4, MSB5 used to control the tmng of the operaton. Therefore, the desgn PSM part of the crcut structure shown n Fg. 7: Phase-to-sne mapper (PSM) MSB3, MSB4, MSB5 MSB1 ) MSB b1 b b8 <<a1-1 <<a-1 <<a7-1 MUX <<a8-1 W- 1's Complementer MUX1 Regster <<a1-4 <<a-4 <<a7-4 <<a8-4 <<a1-5 <<a-5 <<a7-5 <<a8-5 MUX5 MUX6 's Complementer dataout D Squarer <<a1-8 <<a-8 <<a7-8 MUX9 <<a8-8 c1 5. FPGA mplementaton MSB3, MSB4, MSB5 c c7 c8 Fg. 7 PSM crcut structure FPGA s a good choce for hgh-speed, hgh-performance dgtal devces. Ths artcle uses FPGA to desgn DDFS. In ths desgn, the nput s L = 3 bts, the output bt D = 18 bts. Therefore, the PAC bt wdth s 3 bts, whch uses a 3-bt regster, 3-bt adder. DAC s a ready-made resource on the FPGA development board. 5.1 DDFS FPGA mplementaton Wrte the correspondng Verlog code accordng to the desgned crcut structure and then download t to the FPGA board to run. The PFGA development board model used s Altera Corporaton Cyclone II EPC35F67C6. After power-on reset, connect the output termnal to the osclloscope to observe the expermental envronment and The result s shown n Fg. 8. From the osclloscope, we can see the full sne wave output. Fg. 8 DDFS FPGA mplementaton MUX10 0-0 -40-60 -94dBc -80-100 -10-140 -160-180 -00 0 5 10 15 0 5 Mag (db) SFDR Fg. 9 SFDR frequency (MHz) 14
5. DDFS performance parameters 5..1 Frequency resoluton Δf0 f0 (1) In (1), f c s the system clock sgnal frequency, FPGA board crystal 50M, so f c = 50M, N s the phase accumulator word length, the desgn of N = 3, the above formula avalable, the desgn of the DDFS frequency The resoluton Δf o s 7.45e-7Hz. 5.. Output sne wave frequency f0 f0 f N c () It can be seen from the above formula, the output frequency and frequency control word s proportonal. The maxmum output frequency s lmted by the Nyqust samplng rate, so f0(max) 1/ f c. 5..3 Spurous-free dynamc range (SFDR) The SFDR after the truncaton of the DDFS phase s gven by the followng equaton[10]: ( 1) sn N SFDR 0log ( ) dbc (3) 10 sn( ) N In equaton (3), W s the phase accumulator output phase truncated word length, the desgn, W = 0, whch can be calculated, SFDR = 10dBc However, due to the nonlnear DAC and other factors, makng SFDR value s generally less than the theoretcal value, the sne wave spectrum analyss by FFT transform, SFDR and frequency curve can be obtaned, shown n Fg. 9, the analyss shows that ths desgn SFDR value up to -94dBc. 6. Concluson In ths paper, the polynomal nterpolaton of the phase-to-ampltude converson module (PAC) n DDFS s analyzed, and the lnear nterpolaton algorthm and the method of segment-specfc segmentaton are proposed. The FGGA s mplemented on Altera's Cyclone II devce. Based on ths algorthm, DDFS acheves better performance n terms of frequency resoluton, SFDR, workng frequency and so on. In partcular, the frequency resoluton Δfo reaches 7.45e-7Hz and the SFDR value reaches -94dBc, thus achevng hgh precson, Hgh spectral purty sne wave output. In addton, f an LPF s connected to the DAC and the sne waveform s smoothed out, the spectral purty can be further mproved. References [1] J M P Langlos, D Al-Khall. Phase to snusod ampltude converson technques for drect dgtal frequency synthess, IEE Proceedngs - Crcuts, Devces and Systems, vol. 151 (005) No. 6, p.519-58. [] A Ashraf, R Adham, A Mlenkovc. A drect dgtal frequency syntheszer based on the quas-lnear nterpolaton method, IEEE Transactons on Crcuts and Systems I Regular Papers, vol. 57 (005) No. 4, p.863-87. [3] J Goncalves, J. R. Fernendes, M. M. Slva: A reconfgurable quadrature oscllator based on a drect dgtal synthess system, Desgn of Crcuts and Integrated Systems (Barcelona, Span, 006), p. 1-4. f c N W 15
[4] D D Caro, N Petra, A G M Strollo. Drect dgtal frequency syntheszer usng nonunform pecewse-lnear approxmaton, IEEE Transactons on Crcuts and Systems I Regular Papers, vol. 58 (011) No. 10, p.409-419. [5] Huang J M, Lee C C, Wang C C: A ROM-less drect dgtal frequency syntheszer based on 16-segment parabolc polynomal nterpolaton, IEEE Internatonal Conference on Electroncs, Crcuts and Systems (St. Julen's, Malta, 008), p.1018-101. [6] M Genovese, E Napol, D D Caro, et al. Analyss and comparson of Drect Dgtal Frequency Syntheszers mplemented on FPGA, Integraton the Vls Journal, vol. 47 (013) No., p. 61-71. [7] S S Jeng, H C Ln, C H Ln. A novel ROM compresson archtecture for DDFS utlzng the parabolc approxmaton of equ-secton dvson, IEEE Transactons on Ultrasoncs Ferroelectrcs & Frequency Control, vol. 59 (01) No. 1, p.603-61. [8] K S Asok, K P Sahoo: Dgtal hardware optmzaton for 1.5-GHz hgh-speed DDFS, IEEE Internatonal Conference on Electroncs, Crcuts and Systems (Marselle, France, 014), p.746-749. [9] I Hata, I Chakrabart: Advanced Computng (Sprnger, Germany, 011), p.108-119. [10] Curtcapean, Nttylaht. Exact analyss of spurous sgnals n drect dgtal frequency syntheszers due to phase truncaton, Electroncs Letters, vol. 39 (003) No. 6, p.499-501. 16