SENSOR LESS VOLTAGE CONTROL OF CHB MULTILEVEL INVERTER FED THREE PHASE INDUCTION MOTOR WITH ONE DC SOURCE PER EACH PHASE

Similar documents
Crossover Switches Cell (CSC): A New Multilevel Inverter Topology with Maximum Voltage Levels and Minimum DC Sources

Modeling and Analysis of Novel Multilevel Inverter Topology with Minimum Number of Switching Components

A New Multilevel Inverter Topology of Reduced Components

COMPARISON STUDY OF THREE PHASE CASCADED H-BRIDGE MULTI LEVEL INVERTER BY USING DTC INDUCTION MOTOR DRIVES

A Novel Cascaded Multilevel Inverter Using A Single DC Source

Hybrid Five-Level Inverter using Switched Capacitor Unit

Voltage Unbalance Elimination in Multilevel Inverter using Coupled Inductor and Feedback Control

Harmonic Reduction in Induction Motor: Multilevel Inverter

International Journal Of Engineering And Computer Science ISSN: Volume 2 Issue 12 December, 2013 Page No Abstract

SEVEN LEVEL HYBRID ACTIVE NEUTRAL POINT CLAMPED FLYING CAPACITOR INVERTER

A New Transistor Clamped 5-Level H-Bridge Multilevel Inverter with voltage Boosting Capacity

Seven-level cascaded ANPC-based multilevel converter

Literature Survey: Multilevel Voltage Source Inverter With Optimized Convention Of Bidirectional Switches

Three Phase 15 Level Cascaded H-Bridges Multilevel Inverter for Motor Drives

Simulation and Experimental Results of 7-Level Inverter System

Generating 17 Voltage Levels Using a Three Level Flying Capacitor Inverter and Cascaded Hbridge

Harmonic elimination control of a five-level DC- AC cascaded H-bridge hybrid inverter

SIMULATION, DESIGN AND CONTROL OF A MODIFIED H-BRIDGE SINGLE PHASE SEVEN LEVEL INVERTER 1 Atulkumar Verma, 2 Prof. Mrs.

II. WORKING PRINCIPLE The block diagram depicting the working principle of the proposed topology is as given below in Fig.2.

Single Phase Multi- Level Inverter using Single DC Source and Reduced Switches

ISSN Vol.07,Issue.11, August-2015, Pages:

Performance Evaluation of Multi Carrier Based PWM Techniques for Single Phase Five Level H-Bridge Type FCMLI

Design and Evaluation of PUC (Packed U Cell) Topology at Different Levels & Loads in Terms of THD

A Fifteen Level Cascade H-Bridge Multilevel Inverter Fed Induction Motor Drive with Open End Stator Winding

A New Single-Phase Multilevel Inverter with Reduced Number of Switches for Solar Applications

CAPACITOR VOLTAGE BALANCING IN SINGLE PHASE SEVEN-LEVEL PWM INVERTER

Timing Diagram to Generate Triggering Pulses for Cascade Multilevel Inverters

CASCADED H-BRIDGE MULTILEVEL INVERTER FOR INDUCTION MOTOR DRIVES

COMPARATIVE STUDY OF DIFFERENT TOPOLOGIES OF FIVE LEVEL INVERTER FOR HARMONICS REDUCTION

Reduction of Power Electronic Devices with a New Basic Unit for a Cascaded Multilevel Inverter fed Induction Motor

A Novel Multilevel Inverter Employing Additive and Subtractive Topology

Performance Evaluation of a Cascaded Multilevel Inverter with a Single DC Source using ISCPWM

Analysis of IM Fed by Multi-Carrier SPWM and Low Switching Frequency Mixed CMLI

Performance Analysis of Switched Capacitor Three Phase Symmetrical Inverter Topology with Induction Drive

Hybrid 5-level inverter fed induction motor drive

ANALYSIS AND DESIGN OF HYBRID ACTIVE MULTI-LEVEL INVERTER TOPOLOGY FED INDUCTION MOTOR DRIVE

11 LEVEL SWITCHED-CAPACITOR INVERTER TOPOLOGY USING SERIES/PARALLEL CONVERSION

Vinay Potdar 1, Shankar Vanamane 2. P. G. Student, Walchand College of Engineering, Sangli, Maharashtra, India

COMPARATIVE STUDY ON MCPWM STRATEGIES FOR 15 LEVEL ASYMMETRIC INVERTER

Abstract In this paper, a new three-phase, five-level inverter topology with a single-dc source is presented. The proposed topology is obtained by

Low Order Harmonic Reduction of Three Phase Multilevel Inverter

Keywords Cascaded Multilevel Inverter, Insulated Gate Bipolar Transistor, Pulse Width Modulation, Total Harmonic Distortion.

Analysis and Simulation of Multilevel DC-link Inverter Topology using Series-Parallel Switches

ADVANCES in NATURAL and APPLIED SCIENCES

SPECIFIC HARMONIC ELIMINATION SCHEME FOR NINELEVEL CASCADED H- BRIDGE INVERTER FED THREE PHASE INDUCTION MOTOR DRIVE

IJSRD - International Journal for Scientific Research & Development Vol. 4, Issue 04, 2016 ISSN (online):

MODELING AND ANALYSIS OF THREE PHASE MULTIPLE OUTPUT INVERTER

ADVANCED PWM SCHEMES FOR 3-PHASE CASCADED H-BRIDGE 5- LEVEL INVERTERS

THE demand for high-voltage high-power inverters is

CASCADED SWITCHED-DIODE TOPOLOGY USING TWENTY FIVE LEVEL SINGLE PHASE INVERTER WITH MINIMUM NUMBER OF POWER ELECTRONIC COMPONENTS

Switching of Three Phase Cascade Multilevel Inverter Fed Induction Motor Drive

A New Multilevel Inverter Topology with Reduced Number of Power Switches

CARRIER BASED PWM TECHNIQUE FOR HARMONIC REDUCTION IN CASCADED MULTILEVEL INVERTERS

A Modified Apod Pulse Width Modulation Technique of Multilevel Cascaded Inverter Design

CHAPTER 3 SINGLE SOURCE MULTILEVEL INVERTER

DC Link Capacitor Voltage Balance and Neutral Point Stabilization in Diode Clamped Multi Level Inverter

A Comparative Study of SPWM on A 5-Level H-NPC Inverter

IMPLEMENTATION OF MULTILEVEL INVERTER WITH MINIMUM NUMBER OF SWITCHES FOR DIFFERENT PWM TECHNIQUES

Multilevel Cascade H-bridge Inverter DC Voltage Estimation Through Output Voltage Sensing

Analysis And Comparison Of Flying Capacitor And Modular Multilevel Converters Using SPWM

A Five-Level Single-Phase Grid-Connected Converter for Renewable Distributed Systems

An Efficient Cascade H-Bridge Multilevel Inverter for Power Applications

Analysis of Asymmetrical Cascaded 7 Level and 9 Level Multilevel Inverter Design for Asynchronous Motor

Modified Multilevel Inverter Topology for Driving a Single Phase Induction Motor

Speed Control of Induction Motor using Multilevel Inverter

Performance Evaluation of Single Phase H-Bridge Type Diode Clamped Five Level Inverter

29 Level H- Bridge VSC for HVDC Application

ADVANCES in NATURAL and APPLIED SCIENCES

Single-phase multilevel inverter topologies with self-voltage balancing capabilities

A New Self-Balancing Cascaded Multilevel Inverter for Level Doubling Application

ANALYSIS AND IMPLEMENTATION OF FPGA CONTROL OF ASYMMETRIC MULTILEVEL INVERTER FOR FUEL CELL APPLICATIONS

ANALYSIS AND SIMULATION OF CASCADED FIVE AND SEVEN LEVEL INVERTER FED INDUCTION MOTOR

SIMULATION AND COMPARISION OF SYMMETRICAL AND ASYMMETRICAL 3- PHASE H-BRIDGE MULTI LEVEL INVERTER FOR DTC INDUCTION MOTOR DRIVES

ISSN Vol.05,Issue.05, May-2017, Pages:

A Single-Phase Carrier Phase-shifted PWM Multilevel Inverter for 9-level with Reduced Switching Devices

Three Phase 11-Level Single Switch Cascaded Multilevel Inverter

A NOVEL SWITCHING PATTERN OF CASCADED MULTILEVEL INVERTERS FED BLDC DRIVE USING DIFFERENT MODULATION SCHEMES

Enhanced Performance of Multilevel Inverter Fed Induction Motor Drive

An n-level flying capacitor based active neutralpoint-clamped

Multilevel Inverter with Coupled Inductors with Sine PWM Techniques

Multilevel Inverter for Single Phase System with Reduced Number of Switches

COMPENSATION OF VOLTAGE SAG USING LEVEL SHIFTED CARRIER PULSE WIDTH MODULATED ASYMMETRIC CASCADED MLI BASED DVR SYSTEM G.Boobalan 1 and N.

International Journal of Advance Engineering and Research Development

A comparative study of Total Harmonic Distortion in Multi level inverter topologies

THREE PHASE SEVENTEEN LEVEL SINGLE SWITCH CASCADED MULTILEVEL INVERTER FED INDUCTION MOTOR

Elimination of Harmonics using Modified Space Vector Pulse Width Modulation Algorithm in an Eleven-level Cascaded H- bridge Inverter

A New Three Phase Multilevel Inverter With Reduced Number Of Switching Power Devices With Common Mode Voltage Elimination

NEW VARIABLE AMPLITUDE CARRIER OVERLAPPING PWM METHODS FOR THREE PHASE FIVE LEVEL CASCADED INVERTER

Common Mode Voltage Reduction in a Three Level Neutral Point Clamped Inverter Using Modified SVPWM

Simulation of Single Phase Multilevel Inverters with Simple Control Strategy Using MATLAB

Modeling and Simulation of Five Phase Induction Motor Fed with Five Phase Inverter Topologies

A COMPARITIVE STUDY OF THREE LEVEL INVERTER USING VARIOUS TOPOLOGIES

Performance Metric of Z Source CHB Multilevel Inverter FED IM for Selective Harmonic Elimination and THD Reduction

PERFORMANCE ANALYSIS OF SEVEN LEVEL INVERTER WITH SOFT SWITCHING CONVERTER FOR PHOTOVOLTAIC SYSTEM

SINGLE PHASE THIRTY ONE LEVEL INVERTER USING EIGHT SWITCHES TOWARDS THD REDUCTION

Power Quality Enhancement of Diode Clamped Multilevel Inverter Using Different Modulation Schemes

Phase Shift Modulation of a Single Dc Source Cascaded H-Bridge Multilevel Inverter for Capacitor Voltage Regulation with Equal Power Distribution

Three Phase Parallel Multilevel Inverter Fed Induction Motor Using POD Modulation Scheme

A Comparative Analysis of Modified Cascaded Multilevel Inverter Having Reduced Number of Switches and DC Sources

Design and Analysis of a Novel Multilevel Inverter Topology Suitable for Renewable Energy Sources Interfacing to AC Grid for High Power Applications

Transcription:

Volume 120 No. 6 2018, 4079-4097 ISSN: 1314-3395 (on-line version) url: http://www.acadpubl.eu/hub/ http://www.acadpubl.eu/hub/ SENSOR LESS VOLTAGE CONTROL OF CHB MULTILEVEL INVERTER FED THREE PHASE INDUCTION MOTOR WITH ONE DC SOURCE PER EACH PHASE G. V. V. Nagaraju 1, G. Sambasiva Rao 2, CH Rami Reddy 3 1 Department of Electrical & Electronics Engineering, Acharya Nagarjuna University, Guntur, India 2 Department of Electrical & Electronics Engineering, RVR & JC college of Engineering, Guntur, India 3 Department of Electrical & Electronics Engineering, Nalanda Institute of Engineering & Technology, Guntur, India 1 nagaraju006@gmail.com, 2 sambasiva.gudapati@gmail.com, 3 crreddy229@gmail.com. June 20, 2018 Abstract In this paper a single DC source per phase cascaded h bridge (CHB) three phase five level inverter fed induction motor with minimum number of switches and a single capacitor is proposed. Maximum all available switching 1 4079

states are evaluated and a sensor less voltage regulating technique is suggested which controls the second bus voltage as half of the applied single DC voltage source. Voltage levels at the output are zero, the voltage across the capacitor and voltage of DC voltage source. The switching method is mixed with a simple voltage balancing technique which can be possible to implement even with small, simple microcontrollers and Simulation results exhibit the dynamic performance of this method in controlling the second bus capacitor voltage. The low harmonic desired value of five level voltage is regulated by the voltage across the capacitor. Keywords:Three phase CHB inverter; Single DC voltage source; Sensor less voltage regulating technique; Regulating capacitor; Induction motor load. 1 INTRODUCTION The world power demand in the energy market leads to redesign of power converters. The complications with the two level inverter topology are low efficiency and high power losses, which leads to the development of Multi level inverters (MLI). Now a days the use of multilevel inverters is increasing due their advantages and attraction by industries. MLI produces a number of voltage levels at output with the use of many switches with different configurations and DC links, so that the output quasi sine wave has low harmonic distortion [1-3]. The researchers introduce so many types of MLI, among CHB and Neutral point clamped (NPC) inverters are the best ones [4-7]. NPC inverters are finest ones which are attracted by many industries, and provides common DC bus for the application of three phase loads [8]. The CHB inverters have interesting structures and it provides more levels for high power applications, but suffers with many separated DC supplies [9]. Many of the MLI are facing the above mentioned problem [10-20]. Freshly, an attractive structure is designed with the modification of the flying capacitor (FC) inverter, but, suffering with separate voltage ratings and switching frequency [15-17, 21-27]. With the advantages of h bridge inverters a single DC source three phases MLI is designed in Fig.1 2 4080

[28], which has two cells, one cell is connected to DC source and next cell is connected to a charging capacitor. So many studies are implemented for balancing the capacitor voltage for different loads [29-34]. To track the voltage of the source and capacitor it needs a voltage sensor In this paper a new CHB sensor three less inverter fed by induction motor is proposed for generating three phase five level output with single DC source per phase and a single capacitor phase. In each phase when the capacitor is in series to the source and load, it will charge upto half of the source voltage. When it is in series with load the energy is discharged through the load. It has the drawback of reducing voltage levels from seven levels to five levels, but has an advantage of removing sensors at DC source and capacitor. 2 FIVE LEVEL THREE PHASE CHB INVERTER The block diagram of the three phase CHB inverter is presented in Fig.1. It has three single phase CHB inverters, each one is fed by one DC source and one capacitor. Each inverter will act as a single phase CHB inverter, but when connected to induction motor they has a phase difference of 120 degrees. Each one has eight switches and two H- bridge cells in which one cell is connected to supply DC voltage source and other is connected to storage capacitor shown in Fig.2. The voltage across capacitor should be managed as half of the applied voltage source. If the source voltage Vdc is 2E, then the capacitor voltage Vc was E. In the fast published works, the CHB inverter is employed as a seven level inverter with distinct modulation technique, but it is facing voltage balancing problem [32]. But in this paper, we are presenting a sensor less voltage regulating technique which can produce five level output. The switching states of five level voltage waveforms are indexed in the Table. I. Due to no effect on charging and discharging of capacitor voltage some switching positions which produce zero at voltage output are not considered. These switching states are used for reducing the frequency of the inverter. From the switching states listed in Table. I, with paths 3 4081

2, 3, 5 & 6 we can analyze whether the capacitor is charging or discharging. With paths 2 & 6, the capacitor is in series with the DC voltage source and load, hence the capacitor would charge up to E and delivers power to a load. In the sequence 3 & 5 the capacitor is only connected to load so it will discharges power to the load. By introducing the voltage balancing technique into switching techniques, the controller structure gets simple which can be easy to implement by using cheap microcontrollers. The charging and discharging effects of a capacitor after introducing voltage balancing techniques into switching techniques are listed in Table. I Figure 1: Block diagram of the three phase CHB five level inverter fed Induction motor 3 SENSOR-LESS VOLTAGE REGULATING TECHNIQUE From Table. I, it is well known that the capacitor may be charged or discharged in any one half cycle, But to maintain the capacitor voltage fixed, the switching technique of the capacitor is designed in such a way that it should be charged during the positive half cycle and discharged in the negative half cycle. Due to switching technique of capacitor and output waveform frequency the 4 4082

Figure 2: Single DC source multilevel inverter R Phase 5 4083

capacitor charge is increases to half of Vdc supply. The capacitor charge increases when it is connected in series with the load and Vdc source, the charging states of capacitor are 2 and 6, and the load voltage is E. These charging and discharging states are mathematically represented in the equation (1) If the primary source voltage Vdc is 2E, to produce the desired load voltage the charging capacitor voltage Vc must be E. The charging time and discharging time of the capacitor will matain the capacitor voltagevc to E. Hence, to have equivalent charging time and discharging times, in the charging state 2 the capacitor is connected in series with the voltage source in the positive half cycle and from switching state 5 the capacitor is discharged in the negative half cycle by connecting in series with the load. It should be known that the capacitor charging and discharging depends on the type of load only, but not on the output frequency or switching frequency. The type of load connected will directly affect the size of the capacitor. The self regulating voltage procedure is mathematically proved with energy storage relations of the capacitor. The output voltage and current waveforms of a five level CHB inverter is shown in Fig.2. Mathematically the output voltage and current waveforms can be written as an equation (2) and (3) Where Vm, Im and are the maximum value of voltage, current and phase angle between voltage and current. The load current flowing through capacitor can be written as Where I, V, q and U are the current flowing through the capacitor, the voltage across the capacitor, the charge on capacitor plates and energy stored in the capacitor respectively. From equations (3) and (4) the charging energy of the capacitor can be written as 6 4084

7 4085

8 4086

In the same way the discharging energy of the capacitor can be written as From equation (5) and (6), we can observe that the output voltage is symmetric about positive and negative half. Hence we can assume an equation (7) as The energy stored in positive half cycle and negative half cycles are same but has opposite in polarity From equation (8) the energy stored or discharged by the capacitor is balanced and constant and also it keeps the capacitor output voltage constant irrespective of all conditions. For preparing the hardware setup the sensor less voltage regulating technique is integrated with modulation technique. The Multi carrier switching technique is used as modulation technique [17]. For a five level inverter PWM scheme is implemented with four carrier waveforms (Cr1, Cr2, Cr3, and Cr4) and reference sine wave are shown in Fig. 3. 9 4087

Figure 3: Five-level PWM scheme using four level shifted carrier waves Figure 4: Proposed sensor-less voltage regulating approach integrated into switching technique 10 4088

The four carrier waves are chipped vertically for modulating the reference sine wave. The firing pulses related to Table.I are produced after comparing the carrier waves with the reference waveform. The algorithms for producing the firing pulses are presented in Fig.4. This algorithm produces the five level output after seting the capacitor voltage at a currect value without any feedback sensor. This technique does not depend on the type of the system model (e.g. average modelling), modulation index, feedback sensors, grid frequency and switching frequency. It can operate the system voltage to any arbitrary value and also at varying DC source conditions. 4 SIMULATION RESULTS AND DISCUSSION The CHB inverter depicted in Fig.1 is simulated with Matlab/ Simulink, the results shows its performance in standalone mode with induction motor as a load. We can use the standalone inverters as power supply units for motor drives. The simulation parameters of the test system are listed in Table. II. To evaluate the behavior of the proposed method induction motor load is connected to the inverter. When the capacitor is connected with the source and induction motor capacitor voltage starts rising and it reaches the desired value which is half of the Vdc value within 20 cycles. From Fig.5, when the source voltage Vdc is 200 V, the capacitor voltagevc starts increasing and tracks the desired value which is half of the source voltage is 100 V. To observe the changes in the voltage and currents, in Fig.5, the corresponding waveforms are captured. The skyrocket of the three phase multilevel output voltage of the proposed converter is shown in Fig.6. And its zoom is represented in Fig.7. These results, which show that when the frequency of switching is low, then switching pulses are visualized. The load current and its harmonic spectrum without filters are shown in the Fig.8. Due to high starting torque of induction motor, initially it draws more current and after some time it will come to steady state. The symmetrical five level balanced voltage will regulate the voltage of the second bus. The speed and torque waveforms are 11 4089

Figure 5: Voltage across the capacitor voltage Figure 6: Output voltage of the proposed CHB three phase inverter Figure 7: Zoomed waveform of the output voltage of the proposed CHB three phase inverter 12 4090

Figure 8: (a) Load current of inverter for induction motor load (b) THD spectrum of load current in R phase shown in Fig.9. Which shows that the induction motor starting torque is 12 times the rated torque starting. Figure 9: Speed and torque waveforms of induction motor with proposed converter 13 4091

5 CONCLUSION In this paper a new sensor less voltage controlling technique is suggested for the multilevel inverter fed induction motor with single DC source and a capacitor for each phase. The capacitor is charged in the second bus up to half of source voltage, when it is connected to the DC source and an induction motor. Without having any feedback from DC links and loads it will provide five level output voltage. By integrating it with the switching technique industrial products are implemented with a very less number of switches and one DC source and capacitor per phase. The demerits of diode clamped and flying capacitor inverters like capacitor voltage balancing, isolated DC sources are eliminated by this converter. This method is simulated in Matlab, the results shows the good dynamic performance of this method for induction motor load. The power quality is improved. References [1] L. G. Franquelo, J. Rodriguez, J. I. Leon, S. Kouro, R. Portillo, and M. A. M. Prats, The age of multilevel converters arrives, IEEE Ind. Electron. Mag., vol. 2, pp. 28-39, 2008. [2] H. Abu-Rub, M. Malinowski, and K. Al-Haddad, Power electronics for renewable energy systems, transportation and industrial applications: John Wiley & Sons, 2014. [3] B. Singh, A. Chandra, and K. Al-Haddad, Power Quality: Problems and Mitigation Techniques: John Wiley & Sons, 2014. [4] H. Abu-Rub, J. Holtz, J. Rodriguez, and G. Baoming, Medium voltage multilevel convertersstate of the art, challenges, and requirements in industrial applications, IEEE Trans. Ind. Electron., vol. 57, pp. 2581-2596, 2010. [5] M. Sharifzade, H. Vahedi, A. Sheikholeslami, H. Ghoreyshi, and K. Al-Haddad, Modified selective harmonic elimination employed in four-leg NPC inverters, in IECON 2014-40th 14 4092

Annual Conference of the IEEE Industrial Electronics Society, 2014, pp. 5196-5201. [6] F. Sebaaly, H. Vahedi, H. Kanaan, N. Moubayed, and K. Al-Haddad, Sliding-mode current control design for a gridconnected three-level NPC inverter, in Renewable Energies for Developing Countries (REDEC), 2014 International Conference on, 2014, pp. 217-222. [7] M. Sharifzadeh, H. Vahedi, A. Sheikholeslami, P.-A. Labbe, and K. Al-Haddad, Hybrid SHM-SHE Modulation Technique for Four-Leg NPC Inverter with DC Capacitors Self-Voltage- Balancing, IEEE Trans. Ind. Electron., vol. 62, pp. 4890-4899, 2015. [8] J. Rodriguez, S. Bernet, P. K. Steimer, and I. E. Lizama, A survey on neutral-point-clamped inverters, IEEE Trans. Ind. Electron., vol. 57, pp. 2219-2230, 2010. [9] M. Malinowski, K. Gopakumar, J. Rodriguez, and M. A. Perez, A survey on cascaded multilevel inverters, IEEE Trans. Ind. Electron., vol. 57, pp. 2197-2206, 2010. [10] Y.-S. Lai and F.-S. Shyu, Topology for hybrid multilevel inverter, IEE Proc. Electric Power Applications, vol. 149, pp. 449-458, 2002. [11] V. Guennegues, B. Gollentz, F. Meibody-Tabar, S. Rael, and L. Leclere, A converter topology for high speed motor drive applications, in Power Electronics and Applications, 2009. EPE 09. 13th European Conference on, 2009, pp. 1-8. [12] A. Nami, F. Zare, A. Ghosh, and F. Blaabjerg, A hybrid cascade converter topology with series-connected symmetrical and asymmetrical diode-clamped H-bridge cells, IEEE Trans. Power Electron., vol. 26, pp. 51-65, 2011. [13] E. Najafi and A. H. M. Yatim, Design and implementation of a new multilevel inverter topology, IEEE Trans. Ind. Electron., vol. 59, pp. 4148-4154, 2012. 15 4093

[14] K. Gupta and S. Jain, Topology for multilevel inverters to attain maximum number of levels from given DC sources, IET Power Electron., vol. 5, pp. 435-446, 2012. [15] H. Vahedi, S. Rahmani, and K. Al-Haddad, Pinned Mid- Points Multilevel Inverter (PMP): Three-Phase Topology with High Voltage Levels and One Bidirectional Switch, in IECON 2013-39th Annual Conference on IEEE Industrial Electronics Society, Austria, 2013, pp. 100-105. [16] H. Vahedi and K. Al-Haddad, Half-Bridge Based Multilevel Inverter Generating Higher Voltage and Power, in Electric Power and Energy Conference (EPEC), Canada, 2013, pp. 51-56. [17] H. Vahedi, K. Al-Haddad, P.-A. Labbe, and S. Rahmani, Cascaded Multilevel Inverter with Multicarrier PWM Technique and Voltage Balancing Feature, in ISIE 2014-23rd IEEE International Symposium on Industrial Electronics, Turkey, 2014, pp. 2151-2156. [18] M. F. Kangarlu and E. Babaei, A Generalized Cascaded Multilevel Inverter Using Series Connection of Sub multilevel Inverters, IEEE Trans. Power Electron., vol. 28, p. 625, 2013. [19] M. F. Kangarlu, E. Babaei, and M. Sabahi, Cascaded crossswitched multilevel inverter in symmetric and asymmetric conditions, IET Power Electron., vol. 6, pp. 1041-1050, 2013. [20] E. Babaei and S. S. Gowgani, Hybrid multilevel inverter using switched capacitor units, IEEE Trans. Ind. Electron., vol. 61, pp. 4614-4621, 2014. [21] M. F. Escalante, J. C. Vannier, and A. Arzande, Flying capacitor multilevel inverters and DTC motor drive applications, IEEE Trans. Ind. Electron., vol. 49, pp. 809-815, 2002. [22] A. Shukla, A. Ghosh, and A. Joshi, Improved multilevel hysteresis current regulation and capacitor voltage balancing schemes for flying capacitor multilevel inverter, IEEE Trans. Power Electron., vol. 23, pp. 518-529, 2008. 16 4094

[23] M. Ben Smida and F. Ben Ammar, Modeling and DBC- PSC-PWM control of a three-phase flying-capacitor stacked multilevel voltage source inverter, IEEE Trans. Ind. Electron., vol. 57, pp. 2231-2239, 2010. [24] P. Roshankumar, P. Rajeevan, K. Mathew, K. Gopakumar, J. I. Leon, and L. G. Franquelo, A Five-Level Inverter Topology with Single- DC Supply by Cascading a Flying Capacitor Inverter and an HBridge, IEEE Trans. Power Electron., vol. 27, pp. 3505-3512, 2012. [25] Y. Hinago and H. Koizumi, A single-phase multilevel inverter using switched series/parallel dc voltage sources, IEEE Trans. Ind. Electron., vol. 57, pp. 2643-2650, 2010. [26] H. Vahedi, K. Al-Haddad, Y. Ounejjar, and K. Addoweesh, Crossover Switches Cell (CSC): A New Multilevel Inverter Topology with Maximum Voltage Levels and Minimum DC Sources, in IECON 2013-39th Annual Conference on IEEE Industrial Electronics Society, Austria, 2013, pp. 54-59. [27] H. Vahedi, K. Al-Haddad, and H. Y. Kanaan, A New Voltage Balancing Controller Applied on 7-Level PUC Inverter, in IECON 2014-40th Annual Conference on IEEE Industrial Electronics Society, USA, 2014, pp. 5082-5087. [28] Z. Du, L. M. Tolbert, J. N. Chiasson, and B. Ozpineci, A cascade multilevel inverter using a single DC source, in Applied Power Electronics Conference and Exposition, 2006. APEC 06. Twenty- First Annual IEEE, 2006, p. 5 pp. [29] S. Vazquez, J. I. Leon, L. G. Franquelo, J. J. Padilla, and J. M. Carrasco, DC-voltage-ratio control strategy for multilevel cascaded converters fed with a single DC source, IEEE Trans. Ind. Electron., vol. 56, pp. 2513-2521, 2009. [30] H. Sepahvand,J. Liao, M. Ferdowsi, and K. A. Corzine, Capacitor voltage regulation in single-dc-source cascaded H-bridge multilevel converters using phase-shift modulation, IEEE Trans. Ind. Electron., vol. 60, pp. 3619-3626, 2013. 17 4095

[31] Z. Du, L. M. Tolbert, B. Ozpineci, and J. N. Chiasson, Fundamental frequency switching strategies of a seven-level hybrid cascaded Hbridge multilevel inverter, IEEE Trans. Power Electron., vol. 24, pp. 25-33, 2009. [32] H. Sepahvand, J. Liao, and M. Ferdowsi, Investigation on capacitor voltage regulation in cascaded H-bridge multilevel converters with fundamental frequency switching, IEEE Trans. Ind. Electron., vol. 58, pp. 5102-5111, 2011. [33] Z. Du, L. M. Tolbert, J. N. Chiasson, B. Ozpineci, H. Li, and A. Q. Huang, Hybrid cascaded H-bridges multilevel motor drive control for electric vehicles, in 37th IEEE Power Electronics Specialists Conference (PESC), 2006, pp. 1-6. [34] F. Khoucha, A. Ales, A. Khoudiri, K. Marouani, M. Benbouzid, and A. Kheloui, A 7-level single DC source cascaded H-bridge multilevel inverters control using hybrid modulation, in International Conference on Electrical Machines (ICEM), 2010, pp. 1-5. 18 4096

4097

4098