Lars Ohlsson 018-10-0 F9 Differential and Multistage Amplifiers Outline MOS differential pair Common mode signal operation Differential mode signal operation Large signal operation Small signal operation Differential and common mode half-circuits Common mode rejection DC offset Differential amplifier w/ current mirror load Multistage amplifiers Reading Guide Sedra/Smith 7ed int Chapter 8 Problems Sedra/Smith 7ed int P8., 8.8, 8.17(a-b), 8.18, 8.84 1
Common and Differential Mode Signals (recap) Two signal sources v 1 : reference signal minus a (half) component v : reference signal plus a (half) component Differential mode signal component, v Id = v v 1 Typically the interesting part of the signal Common mode signal component, v Icm = 1 v 1 + v Typically a reference or noise level, not desired Common mode rejection ratio (CMRR) Differential to common mode power gain ratio, CMRR = 0 log 10 A d A cm Observe the split and polarity of the differential sources.
MOS Differential Pair Two balanced transistors Same technology, k n Same threshold, V tn Same size, W/L Arranged symmetrically Equal load, R D Share one current sink, I Source terminals joined, V S Equal gate bias, V G Equal overdrive bias, V OV = V GS V tn Differential ports Input over gates Output over drains The MOSFETs in the differential pair (and current sink) must be operated in saturation mode. 3
Common Mode Operation Drain level: constant Forced current through load Resistance sets voltage drop V D1, V D = V DD R DI Gate overdrive: constant Forced current through saturated MOSFETs Materials and design sets overdrive I D1, I D = 1 k n W L V OV = I Source level: varies with CM input Sink must absorb gate voltage offsets V OV ቚ ID1 =I D = I = k n I W L V S = V CM V GS = V CM V tn V OV The MOSFETs in the differential pair share one current sink. 4
Differential Mode Operation Difference signal between Q1 and Q Input over gates, v id = v G1 v G Output over drains, v od = v D v D1 V OV ቚ ID1 =I D = I = k n I W L Positive(/ negative) differential input Different overdrive in Q1 and Q Redistribution of current towards Q1(/ Q) branch of the pair Limit of operation Steering all current to one transistor V OV < v id < V OV 5
Large Signal Operation Gate overdrive level determines differential voltage window i D1, = I D1, ± i d = I ± I V OV v id 1 v id V OV i d = v id V OV g m v id g m = I D1, V OV = I V OV 6
Small Signal Operation Small signal differential input voltage, superimposed on bias point v G1,G = V CM ± v id Small signal perturbation of current i D1,D = I ± g v id m Differential voltage developed over drain terminals I v D1,D = V DD R D ± g v id m Differential gain results g m = I D1, V OV = I V OV v id = v g1 v g V OV v id i d = i d1 = i d = g m v od = v d v d1 = g m v id R D A d = v od v id = g m R D 7
How does a finite MOSFET output resistance affect the gain expression? A d = v od v id = g m R D 8
(Small Signal Analysis Directly on the Circuit Schematic) You may save some ink and time or make grave mistakes A d = v od v id = g m r o R D Imagine the small signal model and work on the original schematic (experienced users only). 9
Differential and Common Mode Half Circuits Differential mode: Push-pull anti-symmetry Source output resistance: virtual ground No differential current flow Constant bias condition Load resistance: split Half the voltage level Half the impedance value Common mode: Push-push symmetry Source output resistance: split Half the current level Twice the impedance value Load resistance ignored Same voltage on both sides Half circuits are only valid if pair and load are symmetric. 10
MOS Differential Pair w/ Active Load Improved performance as compared to passive load, essentially a differential CS amplifier w/ active load A d = v od v id = g m1 r o1 r o3 A d = g m1 R on R op 11
BREAK 1
Common Mode Gain and CMRR Differential gain, A d A d = g m R D Common mode gain, A cm Arises from mismatch A cm = R D R SS ΔR D R D + Δg m g m Common mode rejection ratio (CMRR) Ratio of differential to common mode gain CMRR = A d A cm = ΔR D R D g m R SS + Δg m g m Device matching and high current source resistance keeps CMRR high. 13
DC Offset Imperfectly balanced pair Unequal load, ΔR D = R D1 R D Unequal size, Δ W L = W L 1 W L Unequal threshold, ΔV tn = V tn1 V tn Output non-zero at zero input, as current not balanced Input referred offset voltage, V OS Input that cancels offset V OS = V O V Id =0 A d V OS n V OSn = V OV ΔR D R D + V OV Δ Τ W L Τ W L + ΔV tn 14
Differential to Single Ended Conversion? Option 1: Trash input branch current A convenient but sub-optimal approach Although successfully converting to single ended, half of the signal current is lost to the supply. 15
How to reflect differential pair input branch current to output branch?? 16
MOS Differential Amplifier w/ Current Mirror Load Option : Mirror current to output Superimposes both branch currents KCL magic at output node Differential mode currents cleverly forced into load i d = I + i d I i d = i d Common mode and dc currents must ignore load i CM = I + i cm I + i cm = 0 Current mirror does not load the differential pair symmetrically. 17
Differential Amplifier: Short Circuit Transconductance Identify equivalent transconductance amplifier Infinite input resistance Transconductance Finite output resistance A d = G m R o 1 g mr o = 1 A 0 G m = i d v id g m 18
Differential Amplifier: Output Resistance Identify equivalent transconductance amplifier Infinite input resistance Transconductance Finite output resistance A d = G m R o 1 g mr o = 1 A 0 R o = v x i x r o r o4 19
Differential Amplifier: Common Mode Gain and CMRR Asymmetrical loading Diode connected transistor Common source transistor CMRR = A d A cm g m r o g m R SS Mirror approximately buffers current Common gate source/ load transformations useful A d = v od v id = G m R o g m r o r o4 A cm = v o v icm = 1 A m G mcm R om R o 1 g m R SS 0
Multistage Amplifiers Multistage seen as functional blocks Noise/ CM rejection Signal gain (small signal) Power (linearity) Differential input and interstage Differential gain CM (noise or interference) rejection Single ended output stages Gain and power level Resistance transformation Single ended output typically Load to ground Multistage amplifier is co-desiged system, its stages dedicated to specific tasks. 1
Two-Stage CMOS Op Amp Bias current steering circuit Input stage: differential PMOS pair Gain and single ended conversion NMOS current mirror load Output stage: common source NMOS Gain w/ active load Stability Frequency compensation feedback capacitor Compact, moderate gain, but rather high output impedance
Four Stage BJT Op Amp Bias current steering circuit Input stage: differential NPN pair Differential in/ out gain Second stage: differential NPN pair Gain and single-ended conversion Third stage: degenerated common emitter PNP Gain and level shift Output stage: emitter follower Low output impedance Higher gain, lower output impedance 3