February 23, 2005 Silicon Storage Technology SST39VF800A 8 Mbit Multi-Purpose Flash Memory Structural Analysis For questions, comments, or more information about this report, or for any additional technical needs concerning semiconductor technology, please call Sales at Chipworks.
8 Mbit Multi-Purpose Flash Memory Structural Analysis Table of Contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Introduction 1.4 Device Summary 1.4 Process Summary 2 Device Overview 2.1 Package and Die 2.2 Die Features 3 Process Analysis 3.1 General Device Structure 3.2 Bond Pads 3.3 Dielectrics 3.4 Metallization 3.5 Vias and Contacts 3.6 Peripheral Transistors and Poly 3.7 Flash Cell Transistors 3.8 High Voltage Transistors 3.9 Isolation 3.10 Wells and Substrate 4 Flash Cell Analysis 4.1 Flash Cell in Plan-View 4.2 Cross-Sectional Analysis (Perpendicular to Word Line) 4.3 Cross-Sectional Analysis (Parallel to Word Line) 5 Materials Analysis 5.1 SIMS Analysis of Dielectrics 5.2 TEM-EDS Analysis of Dielectrics 5.3 TEM-EDS Analysis of Metal 1 5.4 TEM-EDS Polycide and Contacts
8 Mbit Multi-Purpose Flash Memory Structural Analysis 6 Critical Dimensions 6.1 Horizontal Dimensions 6.2 Vertical Dimensions 7 Report Evaluation
8 Mbit Multi-Purpose Flash Memory Overview 1 Overview 1.1 List of Figures 2.1.1 Top and Bottom Package Photographs 2.1.2 Plan-View Package X-Ray 2.1.3 Die Photograph 2.1.4 Die Markings 2.1.5 Annotated Die Photograph 2.2.1 Die Corner 1 2.2.2 Die Corner 2 2.2.3 Die Corner 3 2.2.4 Die Corner 4 2.2.5 Minimum Pitch Bond Pads 2.2.6 I/O Bond Pads 2.2.7 Dummy Metal Patterns 3.1.1 General View of SST39WF800A 3.1.2 Die Edge 3.1.3 Die Seal 3.2.1 Bond Pad 3.2.2 Right End Bond Pad 3.3.1 Passivation 3.3.2 Passivation Over Closely Spaced Metal 2 Lines 3.3.3 IMD 3.3.4 PMD 3.4.1 Minimum Pitch Metal 2 3.4.2 Minimum Pitch Metal 1 3.4.3 TEM Metal TiN Cap Layer 3.4.4 TEM Metal 1 TiN Barrier and Ti Adhesion Layers 3.5.1 Minimum Pitch Via 1 s 3.5.2 Minimum Pitch Contacts to Diffusion 3.5.3 TEM Contact Top 3.5.4 TEM Contact Bottom 3.5.5 Contact to Polycide 3.6.1 Minimum Gate Length NMOS Transistor 3.6.2 Minimum Gate Length PMOS Transistor 3.6.3 Peripheral Transistor Glass Etch 3.6.4 Minimum Pitch Poly 2 3.7.1 Flash Cell 1-1
8 Mbit Multi-Purpose Flash Memory Overview 3.7.2 TEM Flash Cell 3.7.3 TEM Floating and Select Gates 3.7.4 TEM Tunnel Oxide 3.7.5 TEM Select Gate Oxide 3.7.6 TEM Floating Gate Oxide 3.8.1 High Voltage Transistor 3.8.2 High Voltage Transistor Glass Etch 3.9.1 Minimum Width STI 3.9.2 Poly 2 on STI 3.9.3 Line of Polycide Over STI 3.10.1 Peripheral N-well 3.10.2 SRP of Peripheral N-well 3.10.3 SRP of Peripheral P-well 3.10.4 SRP of Array P-well 4.0.1 Split-Gate Flash Cell Schematic 4.1.1 Metal 2 Word Line Straps 4.1.2 Metal 1 Bit Lines 4.1.3 Flash Cell at Poly 4.1.4 Select and Floating Gates 4.1.5 Flash Array at Diffusion 4.2.1 Flash Array in Cross-Section 4.2.2 Flash Cell 4.2.3 Flash Cell Delineated with Glass Etch 4.3.1 Poly 2 Word Line and Floating Gate 4.3.2 Floating Gate 4.3.3 Select Gate 4.3.4 Bit Line Contacts 5.1.1 SEM Cross-Section Showing SIMs Analysis of IMD and PMD Layers 5.1.2 Sims Plot of IMD and PMD Layers 5.2.1 TEM-EDS Spectra of Nitride and Oxide Passivation 5.2.2 TEM-EDS Spectra of IMD Oxide and SOG Layers 5.2.3 TEM-EDS Spectra of PMD Oxide, BPGS and Nitride Layers 5.3.1 TEM-EDS Metal 1 TiN Barrier and Cap plus Ti Adhesion Layer 5.4.1 TEM-EDS Cobalt Silicided Gate Polysilicon 5.4.2 TEM-EDS Cobalt Silicided S/D Contact Diffusion 1-2
8 Mbit Multi-Purpose Flash Memory Overview 1.2 List of Tables 3.3.1 Dielectric Thickness 3.4.1 Metallization Vertical Dimensions 3.4.2 Metallization Horizontal Dimensions 3.5.1 Via and Contact Dimensions 3.6.1 Transistor and Polycide Dimensions 3.7.1 Split-Gate Transistor Dimensions 4.2.1 Flash Cell Dimensions 1-3
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