Topics Memory Reliability and Yield Control Logic
Reliability and Yield
Noise Sources in T DRam BL substrate Adjacent BL C WBL α-particles WL leakage C S electrode C cross
Transposed-Bitline Architecture BL9 C cross BL BL SA BL99 (a) Straightforward bit-line routing BL9 C cross BL BL SA BL99 (b) Transposed bit-line architecture
Alpha-particles (or Neutrons) α-particle WL V DD BL n + + + - - - + - + - + - + SiO 2 Particle ~ Million Carriers
Redundancy Redundant columns Redundant rows Memory Array Row Address Row Decoder Fuse : Bank Column Decoder Column Address
Error-Correcting Codes Example: Hamming Codes e.g. B3 Wrong with = 3
Redundancy and Error Correction 6Mbit DRAMs [Kalter9]
Data Retention in SRAM.3u I leakage.u 9n 7n 5n Factor 7.3 mm CMOS (A) 3n n.8 m CMOS m..6.2.8 V DD SRAM leakage increases with technology scaling
Suppressing Leakage in SRAM sleep V DD low-threshold transistor V DD V DDL V DD,int sleep V DD,int SRAM cell SRAM cell SRAM cell SRAM cell SRAM cell SRAM cell sleep V SS,int Inserting Extra Resistance Reducing the supply voltage
Data Retention in DRAM 2 2 2 I ACT I AC 2 3 2 4 2 5 I DC Cycle time : 5 ns T 5 75 C,S 2 6 5M 64M 255M G 4G 5G 64G Capacity (bit) 3.3 2.5 2..5.2..8 Operating voltage (V).53.4.32.24.9.6.3 Extrapolated threshold voltage at 25 C (V) From [Itoh]
Semiconductor Memory Trends (up to the 9 s) Memory Size as a function of time: x 4 every three years
Semiconductor Memory Trends (updated) From [Itoh]
Trends in Memory Cell Area From [Itoh]
Control Logic Finite State Machines Logic Implementations PLA ROM Multilevel Logic
State Machines Moore Machine Outputs are dependent only on current state Inputs Logic Current State Next State Memory Logic Outputs
State Machines Mealy Machine Outputs are dependent on current state and inputs Inputs Logic Outputs Current State Next State Memory
State Machine Design Moore Machine ON ON ON TRIGGER ON ON ON TRIGGER 2 ALARM ON TRIGGER ON TRIGGER
State Machine Design Mealy Machine ON ON ON TRIGGER ON ON ON TRIGGER 2 ON TRIGGER/ALARM ON TRIGGER/ALARM
State Machine Design S S ON TRIGGER NS NS ALARM X X X X X X X X X NS = ON TRIGGER + S S ON NS= S ON TRIGGER + S ON TRIGGER ALARM = S S
Programmable Logic Array x x Product terms AND plane x 2 OR plane f f x x x 2
PLA Design NS = ON TRIGGER + S S ON NS = S ON TRIGGER + S ON TRIGGER S S ON TRIGGER NS NS
Two-Level Logic Every logic function can be expressed in sum-of-products format (AND-OR) minterm Inverting format (NOR- NOR) more effective
PLA Design NS = ON + TRIGGER + S+ S + ON NS = S+ ON + TRIGGER + S + ON + TRIGGER S S ON TRIGGER NS NS
PLA Design
PLA versus ROM Programmable Logic Array structured approach to random logic two level logic implementation NOR-NOR (product of sums) NAND-NAND (sum of products) IDENTICAL TO ROM! Main difference ROM: fully populated PLA: one element per minterm Note: Importance of PLA s has drastically reduced. slow 2. better software techniques (mutli-level logic synthesis)
Programmable Logic Array Pseudo-NMOS PLA GND GND GND GND V DD GND GND GND V DD X X X X X 2 X 2 f f AND-plane OR-plane
Dynamic PLA f AND GND V DD f OR V DD f AND X X X X X 2 X 2 f f GND f OR AND-plane OR-plane
Clock Signal Generation for self-timed dynamic PLA f f Dummy AND row f AND f AND t pre t eval f AND Dummy AND row f OR f OR (a) Clock signals (b) Timing generation circuitry
PLA Layout V DD And-Plane Or-Plane φ GND x x x x x 2 x 2 Pull-up devices f f Pull-up devices
State Machine Design Other Control Implementation Microcode (ROM) Multilevel Logic
Next class HW5 due March 29th Clocking Read Chapter