RESPONSIBILITY OF THE SEMICONDUCTOR DESIGN INFRASTRUCTURE C O N S U L T I N G I N E L E C T R O N I C D E S I G N Lucio Lanza gave a keynote at IC CAD 2010 that caught a lot of people s attention. In that keynote he made two key points. All of the members of the Semiconductor Infrastructure have their individual responsibilities (see Figure 1). They are all being measured by Moore s Law. Figure 1 - The Semiconductor Infrastructure The Semiconductor Infrastructure Computer Resources Embedded Software EDA VC Funding Design Methodology The Semiconductor Cycle Educational System Process R&D Semiconductor Manufacturing Equipment Foundry Packaging & Assembly Source: Gary Smith EDA June 2011 Electronic Design Automation If you look at EDA you can say it has a spotty record over the last two decades. First of all we need to define their responsibility. EDA is Responsible for developing design tools that enable the IC design process. If you look at it from the semiconductor side you can say that designers have been able to tape out designs at each new semiconductor node when first introduced. That indicates that the EDA industry has been successful in meeting their responsibilities. But if you look a little closer you ll find that these initial designs use in-house developed tools to solve many of the challenges faced with using the latest semiconductor node. Now the EDA Industry is getting better. EDA vendors are now producing a high percentage of the PAGE 1
tools needed, but still they typically don t have a complete set of tools until a year after the node is introduced. That doesn t sound too bad unless you understand that the new tools need to be available at least a year before the node goes into production, in order for the design engineers to tape out, in time to go into production when the new node is available. That is why you can say that EDA has a spotty record. They are getting better but still only the Power Users, with CAD organizations, can take advantage of the state-of-the-art processes. In the last ten years the design world has come across a new problem, the cost of design is starting to have an impact on the entire Semiconductor Infrastructure. The Cost of Design In 2002 the cost of design passed a critical point on the cost curve. At that time the cost of design passed the $25,000,000 point (see Figure 2). That impacted the Venture Capital community. When looking at new semiconductor start-up the general rule of thumb is that a $25,000,000 investment is about all you can fund in order to get the required pay-back. The result funding dropped and the number of start-ups declined. Figure 2 The ITRS Cost Chart 2010 ITRS Cost Chart 2010 ($Ms) $120 $100 $80 $60 $40 $20 $0 IC Implementa on Tool set RTL Func onal Verif. Tool Suite Transac on Level Modeling Very Large Block Reuse SMP Parallel Processing Intelligent Testbench So ware Virtual Prototype Silicon Virtual Prototype AMP Parallel Processing Many Core Devel. Tools Concurrent Memory System Design Automa on Executable Specifica on 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 Total HW Engineering Costs EDA Tool Costs Total SW Engineering Costs ESA Tool Costs 2018 2019 2020 2021 2022 Green: Start-Ups stop Red: most SoC design stops 2023 2024 2025 -Post CMOS - Source: ITRS December 2010 (modified by Gary Smith EDA) PAGE 2
Unfortunately it gets worse. In 2008 design costs passed the $50,000,000 mark. At that point we started to see even the large IDMs cut back on their design starts. This of course impacts the entire semiconductor infrastructure including the EDA industry. The Great Recession was blamed for the downturn but a major factor was that the overall semiconductor infrastructure was in trouble. What is EDA s Responsibility? That brings up the definition of EDA s responsibility to the semiconductor infrastructure. Is it EDA is Responsible for developing design tools that enable the IC design process. Or is it EDA is Responsible for developing design tools that enable the IC design process, at a design cost that allows the ecosystem to operate at a profit? It s not the cost of tools that is causing the problem. The key factor in design cost is the number of engineers and the length of the design cycle. So the problem is in the level of automation and the performance of the design tools. In fact the cost of the tools really needs to increase to allow the EDA vendors to fund the R&D necessary to keep up with Moore s Law. A Look at a Design Team It is not uncommon for SoC design teams to range from 100 to 200 hardware design engineers. It s also not uncommon for design cycles to stretch out to 18 months or more. Both are an indication of a design project that is out of control. The ITRS (History of the ITRS blog) surveys their members and reports the costs for an average high end SoC design. In order to determine cost you need to know design time, cost of engineering, and their tools, and the size and complexity of the design. The target for a SoC design time is nine months to a year. Today it s not uncommon for the designs to take thirteen months, however the ITRS has chosen to use a twelve month design cycle for their calculations. They do not include derivative designs in the calculations. Derivative designs are tweaks of an already existing design which typically takes three to four months. PAGE 3
This year the results show that a design team, for a 104 million gate design, contained 30 hardware engineers at a cost of $18.7 million and 160 software engineers at $56.4 million. This gives you a total cost of $75.1 million, way over the $50 million dollar maximum target. It s easy for the hardware design world to say that the software design costs are killing us, and they are; however that s a topic for another paper. Let s concentrate on the hardware design problem. It is encouraging that the EDA vendors are starting to provide solutions to the software automation problem also. The software engineers can use all the help they can get. How Should R&D Solve the HW Cost Problem First the EDA vendors need to understand the problem. One of the key issues is that many R&D engineers don t understand how their tools are being used. That is one of the advantages that EDA start-ups have had over the larger vendors. They must have an intimate relationship with their customer s design team to survive. There are five basic parameters that the R&D groups need to know about a design. The number of blocks in a design. The amount of reuse in a design. The size of the blocks. The number of engineers per block. How many gates must an EDA tool handle to support these parameters? The Number of Blocks The ideal number of blocks is five. Usually it ends up to be more like 35. Anything over that slows down the design significantly, which drives up the cost. That usually means your design must be hierarchical. The Amount of Reuse That brings up the topic of reuse. Today s designs are based on previous designs or use an already existing platform to form a base for the design. These platforms are either developed in-house or are purchased from a semiconductor vendor. The ideal here is to only have to design ten to twenty present of the SoC from scratch. And even then the design engineers often use predesigned IP blocks in their new block s design. Unfortunately the average reuse is now around seventy percent of the SoC. Still in today s multimillion gate design reuse is the major driver of design productivity. PAGE 4
Block Size is Important 1. In a 100 million gate design 90% reuse gives you five 2 million gate blocks. 2. At 80% reuse that goes up to five 4 million gate blocks. 3. That s six engineers verses twelve engineers. 4. If you add a six engineer integration team. 5. Then you double those numbers, by adding the required verification engineers. 6. That gives you twenty four engineers verses thirty six engineers. 7. That s the difference from meeting your design cost budget or exceeding your budget. How many gates Should an EDA tool Handle? In this test case a design engineer needs a tool that can handle (in an acceptable length of time) at least four million gates. In reality a design engineer wants a tool that can work on the entire new block, twenty million gates. But this is for an average high end design. Keep in mind the EDA vendors should be enabling a design engineer to use all of the available silicon within the required cost constraints (see Figure 3). Figure 3 Max Gates per Silicon Node Millions of Gates Let s do the Math Using Max Gates per node Source: ITRS December 2010 and Gary Smith EDA PAGE 5
So at the 32 nm node, which is where most high end designs are today, we need tools that can handle 44 million gates at a time. And at 22 nm, where designs are going next, they would need to handle 88 million gates. Are we even close? The Future of the Semiconductor Infrastructure As you can see the EDA industry has a lot of work to do before the health of the Semiconductor Infrastructure can be restored. There are a few things the Design community needs to consider as they address their next design. First of all is design efficiency. How does your design methodology measure up to your competition? If you are throwing engineers at the problem and going to the lowest cost countries to keep your costs down, you are going in the wrong direction. Off-shoring builds in communications inefficiencies that often outweigh the cost of engineers. Design automation is the key to low cost design. Second if you pride yourself on the cost of your design tools you are in trouble. Design tools are lunch money compared to the cost of your engineering resources. Surveys have shown that the lowest cost for an extra week of design time to be $157,000. That was an old survey. Today you can expect your one week cost to be in the millions of dollars. You can buy a lot of EDA tools for a million bucks. Keep in mind the lower your price the sooner the lack of EDA R&D funding will be impacting your future. And third is the concept of design efficiency. Many companies focus on design tool integration. What they fail to understand is that a key component of design efficiency is tool performance. One sub-optimal tool can easily cause a tightly integrated flow to be noncompetitive, especially if it is one of the major tools in the chain. One start up introduced a timing analyzer that was ten to thirty times faster than the major EDA vendors timing engine. As timing analysis is used throughout the design flow that improvement quickly made up for any integration efficiencies. An investment in a CAD Group is easily made up by your increase in design productivity. There are many other examples which point out the advantages of not limiting yourself to a one vendor flow. It also points out the importance of EDA start-ups in design tool innovation. PAGE 6
In Conclusion There is a lot of work to be done to restore health to the Semiconductor Infrastructure. The ITRS Cost Chart predicts that it will take until 2021 until we see significant improvement. The actions of the EDA vendors and the design community, over the next ten years, will determine the size of the Semiconductor Infrastructure going into the next decade. We can change the rate of automation improvement, and therefore the cost of design, but we can t do it without a major increase in EDA s R&D. GARY SMITH PHONE +1 (408) 985-2929 FAX +1 (408) 985-6611 www.garysmitheda.com 2011 Gary Smith EDA. All Rights Reserved. gary@garysmitheda.com PAGE 7