Rockchip RK3188 Mobile Application Processor GF 28 nm SLP Gate First HKMG CMOS Process Process Review FEOL Analysis 1891 Robertson Road, Suite 500, Ottawa, ON K2H 5B7 Canada Tel: 613-829-0414 www.chipworks.com
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Process Review FEOL Analysis Table of Contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Company Profiles 1.4 Introduction 1.5 Device Summary 1.6 Process Summary 2 Device Overview 2.1 Package and Die 2.2 Die Features 3 Process Analysis 3.1 Analysis Locations 3.2 General Device Structure 3.3 Bond Pad Cross Section 3.4 Dielectrics 3.5 Isolation 3.6 Metallization 3.7 Vias and Contacts 3.8 Transistor Overview 3.9 NMOS Transistors 3.10 PMOS Transistors 3.11 MOS Capacitor 3.12 Wells and Substrate 4 SRAM Layout 4.1 6T SRAM Schematic 4.2 Plan-View 6T SRAM Analysis 5 Critical Dimensions 5.1 Horizontal Dimensions 5.2 Vertical Dimensions 6 References 7 Statement of Measurement Uncertainty and Scope Variation About Chipworks
Overview 1-1 1 Overview 1.1 List of Figures 2 Device Overview 2.1.1 RK3188 Package Top 2.1.2 RK3188 Package Bottom 2.1.3 RK3188 Package X-Ray Side View 2.1.4 RK3188 Package X-Ray Plan View 2.1.5 RK3188 Die Photograph 2.1.6 Die Markings 2.2.1 Die Corner A 2.2.2 Die Corner B 2.2.3 Die Corner C 2.2.4 Die Corner D 2.2.5 Minimum Pitch Bond Pads 2.2.6 Long Bond Pad with Two Ball Bonds 2.2.7 Bond Pads and Test Pads at the Die Edge 2.2.8 Logic NAND Gate 3 Process Analysis 3.1.1 Die Analysis Locations 3.2.1 General Structure of the RK3188 3.2.2 Die Edge 3.3.1 Bond Pad Cross Section SEM 3.3.2 Bond Pad Edge 3.3.3 Edge of the Ball Bond on the Bond Pad 3.4.1 ILD 7, ILD 8, and Passivation SEM 3.4.2 ILD 6 TEM 3.4.3 ILD 5 TEM 3.4.4 ILD 4 TEM 3.4.5 ILD 3 TEM 3.4.6 ILD 2 TEM 3.4.7 ILD 1 TEM 3.4.8 PMD SEM 3.4.9 PMD TEM 3.5.1 STI TEM 3.6.1 Metal 9 Thickness SEM 3.6.2 Metal 9 Barrier Layers TEM 3.6.3 Top Metal Minimum Observed Width and Pitch Plan-View Optical Image 3.6.4 Metal 3 Body and Barrier Thickness TEM 3.6.5 Minimum Pitch Metal 3 TEM 3.6.6 Metal 1 Width and Thickness TEM 3.6.7 Metal 1 Liner TEM 3.7.1 Minimum Pitch Via 8 SEM 3.7.2 Minimum Observed Width and Pitch Via 7s SEM 3.7.3 Overview of Via 5 Through Via 1 SEM
Overview 1-2 3.7.4 Minimum Width Via 1 and Minimum Pitch Metal 1 TEM 3.7.5 Minimum Width Via 2 TEM 3.7.6 Minimum Pitch Via 1 SEM 3.7.7 NMOS S/D Contact TEM 3.7.8 Bottom of PMOS S/D Contact TEM 3.7.9 Bottom of NMOS S/D Contact TEM 3.8.1 Minimum NMOS Contacted Gate Pitch TEM 3.8.2 Minimum PMOS Contacted Gate Pitch TEM 3.8.3 Transistor SWS TEM 3.9.1 NMOS Logic Transistor Overview TEM 3.9.2 NMOS Gate Metals and Dielectrics TEM 3.10.1 PMOS Logic Transistor Gate Overview TEM 3.10.2 PMOS Transistor Minimum Gate Length TEM 3.10.3 PMOS Gate Metals and Dielectrics TEM 3.11.1 MOS Capacitor Edge TEM 3.11.2 MOS Capacitor Gate Metals and Dielectrics HRTEM 3.12.1 N-Type Dopant SIMS 3.12.2 P-Type Dopant SIMS 3.12.3 Logic Region SCM 3.12.4 SRAM Region SCM 4 SRAM Layout 4.1.1 SRAM Circuit Schematic 4.2.1 SRAM Plan-View SEM Image at the Metal 3 Level 4.2.2 SRAM Plan-View SEM Image at the Metal 2 Level 4.2.3 SRAM Plan-View SEM Image at the Metal 1 Level 4.2.4 SRAM Plan-View SEM Image at Polysilicon Level 4.2.5 Plan-View SEM Image at the Diffiusion Level 4.2.6 Overlaid Colorized SEM Images of the SRAM at Polysilicon over Diffusion 4.2.7 Overlaid Colorized SEM Images of SRAM at Metal 1 over Polysilicon 4.2.8 Overlaid Colorized SEM Images of SRAM at Metal 2 over Metal 1 4.2.9 Overlaid Colorized SEM Images of SRAM at Metal 3 over Metal 2
Overview 1-3 1.2 List of Tables 1 Overview 1.4.1 Device Identification 1.5.1 Device Summary 1.6.1 Process Summary 2 Device Overview 2.2.1 Die and Bond Pad Sizes 3 Process Analysis 3.4.1 Dielectric Thicknesses 3.6.1 Metallization Vertical Dimensions 3.6.2 Metallization Horizontal Dimensions 3.7.1 Vias and Contact Horizontal and Vertical Dimensions 3.8.1 Transistor Horizontal Dimensions 3.8.2 Transistor and Silicide Vertical Dimensions 3.12.1 Die Thickness and Well Depths 5 Critical Dimensions 5.1.1 Die and Bond Pad Sizes 5.1.2 Metallization Horizontal Dimensions 5.1.3 Vias and Contact Dimensions 5.1.4 Transistor Horizontal Dimensions 5.2.1 Dielectric Thicknesses 5.2.2 Metallization Vertical Dimensions 5.2.3 Transistor and Silicide Vertical Dimensions 5.2.4 Die Thickness and Well Depths
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