University of Toronto Faculty of Applied Science and Engineering. Digital Electronics. Winter Final Exam. Instructor: R.

University of Toronto Faculty of Applied Science and Engineering ECE 334 - Digital Electronics Winter 2017 Final Exam Instructor: R. Genov Duration: 150 minutes Closed book; A hand-written 8.5"xl1"one-page aid-sheet is allowed. Only silent, non-communicating, non-programmable calculators are permitted. Turn all cell phones off. Cell phones are not permitted as watches or calculators. Only the last sheet (parameter sheet) is allowed to be removed from the test book. Answer all questions in the space provided. No additional exam sheets for answers are permitted. Attempt all questions, since a blank answer will certainly get a mark of 0. Write clearly. It is not the marker's job to decipher your answers through pages of scribble. Marks assigned to each question are indicated inside [ ]. Write your name and student number in the space below. Do the same on the top of each sheet of this exam book. Name: (Underline last name) Student Number: QI [/10] Q2 [/11] Q3 [/7] Q4[I9] Q5[I7] Q6[I6] Total [/50] Page 1 of 14

Question 1. [10] Find the MTBF for each of the three synchronizers depicted below, if the delay of each inverter is 25ps, the clock period is 400ps, trd = lops, and if the input toggles at 100MHz. The flip flops are identical and have clock-to-q contamination time of 60ps, and Ts = 20ps. Sketch the CLK, and CLK2 waveforms in the provided space. Hint: You need to use the fact that CLKi and CLK2 are delayed and inverted versions of CLK in (b) and (C) respectively. CLK D D Q (a) l0qb L1i CLK D j D L:SC LK, CLK D [ II I,j ro jclk2 CLK CLK Page 2 of 14

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Question 2. [11] The schematic of a flip-flop implemented in a 180nm CMOS process is depicted below. Label properly the gate terminals of all transmission gates (in the dotted boxes) to make the flipflop positive-edge triggered. For the given process parameters find the hold time of the flip-flop, if all PMOS transistors have Wp = 8A, all NMOS transistors have Wn = 4A, and all transistor lengths are Lmin = 2A. Assume 70% settling condition for the delay calculations. Process parameters: VDD = 1.2V pncox = 3ppCox = 300pNV2 Vtn = lvtpj = 0.4V Cdp Cgp = 1fF/pm DL D J CLK (P thold = Page 4 of 14

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Question 3. [7] The layout of a circuit block is depicted below. Draw the corresponding transistor level schematic and figure out the function of the circuit. Also give the proper names to Node 1, Node 2, and Node 3. Node 2 I Node 1 Node 3 I Circuit function: 0115674 rm Node 2: Page 6 of 14

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Question 4. [9] An SRAM designed with the minimum size transistors (W = 4A, L = 2A) in a 130nm CMOS process has a IM-bit memory and 32-bit word-length. Verify the read stability and writability conditions for the SRAM, and find the read time if the sense amplifier requires a minimum differential voltage of 100mV between BL and BL. Process parameters: VDD = 1.2V PnCox = 3ppCox = 300pNV2 Vt = lvtpj = O.4V Cdp = Cgp = 1fF/pm Tread Page 8 of 14

Question 5. [7] A schematic of a logic gate is depicted below. What is the name of the CMOS circuit family used to implement the gate and what is the name of the gate? If all NMOS transistors are minimum-size, find the best-case and the worst-case equivalent pull-down resistances. A minimumsize NMOS transistor equivalent resistance is defined as Rmin. Circuit family: Gate: RpD-worst = X Rmjn RpD-best = x Rmrn Page 10 of 14

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Question 6. [6] Consider the three-inverter circuit depicted below, with the shown DC transfer characteristics of a single inverter. Between the input voltages of 0.45V and 0.55V the transfer curve of an inverter can be assumed to be linear with the slope of -7. All three inverters are identical. What are the noise margins of a single inverter, if VOL = 0.05V and VOH = 0.95V? What are the noise margins of the three-inverter circuit, if VOL = 0.05V and VoH = 0.95V at node 0? Hint: For the three-inverter circuit, you have to calculate VIH and VIL at node A. Inverter DC transfer characteristics 1 A *O--*O---*O-- Q 0.5 Inverter NML: NMH: Three-inverter circuit NML: BM Page 12 of 14

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ECE334 Digital Electronics Equation Sheet Constaats:k = 1. 38 x 1O 23 19 JKt q 1,602 x C, V= kt/q26rnvat3oo K 8.854 x lo F/rn k Ok, = 19 1 caps: C = Cj * ('f /(l -- 1'R/+0) \MOS f ii,,( ( If IL) I 0 I I)s ~ 0 (mode) 1) = 1(( - t ) - (I7/2)) (au) 'n 0 1( - (triode) va,,!~- (' V) (active) (V V:n) V = V + T (subthreshold) If) = V (1 e ) PMOS: P = 1C0\( f*7l.) V, < 0I' ~ 0,(triode) '8-1(( s V)I' Ip (V (triode) Ir>s ~ f',,) (active) Vi ~ (" I',) Simple cap model: C co,,wl if Cg C( Lrn*n Cg 5/2)).(acthe) '8 OSIp(JiS 11 ('.*1OS inverter: I' =(I'Dj) V,,,-- 1,r)/(l + r) I r RC delay est td =t4f, = I 2r t = RcqC R q = 2 5/(p,0( /1( DD V )) R, = 2 /(1iC( If /l)( DD + E 4,)) = (nit delay est: r'an = (L21L) X Min delay: dela~ = r(c/c) total f = C'/C usually! 4 Power diss: = ' dp = fldd'pear + Elmore Delay: T1 dist RC, t RC/2 Interconnect: R = pi)/(:w) R = p1t, C (cw/)/t C = \!(w//z -- 0.77t 1.06()r/h) + I06(,/h) 0 ) Max delay constraint: 7'. ~ i + PN ~ Mlii Delay constraint:, + t Metastability: MTBF * e /( tf8f K ) SRAM: M3 is cell access transistor, Ml is inverter NMOS. M5 is inverter PMOS. SR4M read: W 1/W 3 > (V, V IY/(2((F')[) 1)1A - I/2)) I A in * SRAM write: W 3/W Page 14 of 14