Precision Low Power Single-Supply JFET Amplifier FEATURES SC7 package Very low IB: pa max Single-supply operation: 5 V to 26 V Dual-supply operation: ±2.5 V to ±3 V Rail-to-rail output Low supply current: 63 µa/amp typ Low offset voltage: 5 µv max Unity gain stable No phase reversal APPLICATIONS Photodiode amplifiers ATE Line-powered/battery-powered instrumentation Industrial controls Automotive sensors Precision filters Audio NC 8-Lead SOIC (R-8 Suffix) IN 2 7 V+ AD8627 +IN 3 6 OUT OUT A V 4 5 NC IN A +IN A NC = NO CONNECT 2 3 8-Lead SOIC (R-8 Suffix) AD8626 PIN CONFIGURATIONS 8 NC V+ OUT B IN B V 4 5 +IN B 4-Lead SOIC (R-Suffix) 8 7 6 OUT A V +IN OUT A IN A +IN A V 2 3 5-Lead SC7 (KS Suffix) AD8627 8-Lead MSOP (RM-Suffix) 4 AD8626 8 5 4-Lead TSSOP (RU-Suffix) 5 4 V+ IN V+ OUT B IN B +IN B GENERAL DESCRIPTION The AD862x is a precision JFET input amplifier. It features true single-supply operation, low power consumption, and rail-to-rail output. The outputs remain stable with capacitive loads of over 5 pf; the supply current is less than 63 µa/amp. Applications for the AD862x include photodiode transimpedance amplification, ATE reference level drivers, battery management, both line powered and portable instrumentation, and remote sensor signal conditioning including automotive sensors. OUT A 4 OUT D OUT A IN A 2 3 IN D IN A +IN A +IN A 3 2 +IN D V+ AD8625 +IN B V+ 4 V IN B +IN B 5 +IN C OUT B IN B 6 9 IN C OUT B 7 8 OUT C Figure. 4 AD8625 7 8 OUT D IN D +IN D V +IN C IN C OUT C 323-B- The AD862x s ability to swing nearly rail-to-rail at the input and rail-to-rail at the output enables it to be used to buffer CMOS DACs, ASICs, and other wide output swing devices in single-supply systems. The 5 MHz bandwidth and low offset are ideal for precision filters. The AD862x is fully specified over the industrial temperature range. ( 4 to +85 ) The AD8627 is available in both 5-lead SC7 and 8-lead SOIC surface-mount packages. The SC7 packaged parts are available in tape and reel only. The AD8626 is available in an MSOP package. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 96, Norwood, MA 62-96, U.S.A. Tel: 78.329.47 www.analog.com Fax: 78.326.873 4 Analog Devices, Inc. All rights reserved.
TABLE OF CONTENTS Specifications... 3 Electrical Characteristics... 3 Electrical Characteristics... 4 Absolute Maximum Ratings... 5 Typical Performance Characteristics... 6 Applications... 3 Minimizing Input Current... 5 Photodiode Preamplifier Application... 5 Output Amplifier for Digital-to-Analog Converters... 5 Eight-Pole Sallen Key Low-Pass Filter... 6 Outline Dimensions... 8 Ordering Guide... 9 REVISION HISTORY /4 Data sheet changed from Rev. A to Rev. B Change to General Description... Change to Figure... 7 Change to Figure3... 7 Change to Figure 37... Changes to Figure 38...2 Change to Output Amplifier for DACs section...5 Updated Outline Dimensions...9 /3 Data sheet changed from Rev. to Rev. A Addition of two new parts. Universal Change to General Description.... Changes to Pin Configurations... Change to Specifications table..3 Changes to Figure 3... Changes to Figure 32..... Changes to Figure 38...2 Changes to Figure 46...6 Changes to Figure 47..... 6 Changes to Figure 49..... 7 Updated Outline Dimensions..8 Changes to Ordering Guide..... 9 Rev. B Page 2 of
SPECIFICATIONS ELECTRICAL CHARACTERISTICS Table. @VS = 5 V, VCM =.5 V, TA = 25 C, unless otherwise noted. Parameter Symbol Conditions Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage VOS.5.5 mv 4 C < TA < +85 C.2 mv Input Bias Current IB.25 pa 4 C < TA < +85 C 6 pa Input Offset Current IOS.5 pa 4 C < TA < +85 C 25 pa Input Voltage Range 3 V Common-Mode Rejection Ratio CMRR VCM = V to 2.5 V 66 87 db Large Signal Voltage Gain AVO RL = kω, VO =.5 V to 4.5 V 23 V/mV Offset Voltage Drift VOS/ T 4 C < TA < +85 C 2.5 µv/ C OUTPUT CHARACTERISTICS Output Voltage High VOH 4.92 V IL = 2 ma, 4 C < TA < +85 C 4.9 V Output Voltage Low VOL.75 V IL = 2 ma, 4 C < TA < +85 C.8 V Output Current IOUT ± ma POWER SUPPLY Power Supply Rejection Ratio PSRR VS = 5 V to 26 V 8 4 db Supply Current/Amplifier ISY 63 785 µa 4 C < TA < +85 C 8 µa DYNAMIC PERFORMANCE Slew Rate SR 5 V/µs Gain Bandwidth Product GBP 5 MHz Phase Margin ØM 6 Degrees NOISE PERFORMANCE Voltage Noise en p-p. Hz to Hz.9 µv p-p Voltage Noise Density en f = khz 7.5 nv/ Hz Current Noise Density in f = khz.4 fa/ Hz Channel Separation Cs f = khz 4 db Rev. B Page 3 of
ELECTRICAL CHARACTERISTICS Table 2. @VS = ±3 V; VCM = V; TA = 25 C, unless otherwise noted. Parameter Symbol Conditions Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage VOS.35.75 mv 4 C < TA < +85 C.35 mv Input Bias Current IB.25 pa 4 C < TA < +85 C 6 pa Input Offset Current IOS.5 pa 4 C < TA < +85 C 25 pa Input Voltage Range 3 + V Common-Mode Rejection Ratio CMRR VCM = 3 V to + V 76 5 db Large Signal Voltage Gain AVO RL = kω, VO = V to + V 5 3 V/mV Offset Voltage Drift VOS/ T 4 C < TA < +85 C 2.5 µv/ C OUTPUT CHARACTERISTICS Output Voltage High VOH +2.92 V VOH IL = 2 ma, 4 C < TA < +85 C +2.9 V Output Voltage Low VOL 2.92 V VOL IL = 2 ma, 4 C < TA < +85 C 2.9 V Output Current IOUT ±5 ma POWER SUPPLY Power Supply Rejection Ratio PSRR VS = ± 2.5 V to ± 3 V 8 4 db Supply Current/Amplifier ISY 7 85 µa 4 C < TA < +85 C 9 µa DYNAMIC PERFORMANCE Slew Rate SR 5 V/µs Gain Bandwidth Product GBP 5 MHz Phase Margin ØM 6 Degrees NOISE PERFORMANCE Voltage Noise en p-p. Hz to Hz 2.5 µv p-p Voltage Noise Density en f = khz 6 nv/ Hz Current Noise Density in f = khz.5 fa/ Hz Channel Separation Cs f = khz 5 db Rev. B Page 4 of
ABSOLUTE MAXIMUM RATINGS Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute maximum ratings apply at 25 C, unless otherwise noted. Table 3. Stress Ratings Parameter Rating Supply Voltage 27 V Input Voltage VS to VS+ Differential Input Voltage ± Supply Voltage Output Short Circuit Duration Indefinite Storage Temperature Range, R Package 65 C to + 25 C Operating Temperature Range 4 C to + 85 C Junction Temperature Range, R Package 65 C to 5 C Lead Temperature Range (Soldering, 6 sec) 3 C Table 4. Package Type θja θjc Unit 5-Lead SC7 (KS) 376 26 C/W 8-Lead MSOP (RM) 45 C/W 8-Lead SOIC (R) 58 43 C/W 4-Lead SOIC (R) 36 C/W 4-Lead TSSOP (RU) 8 35 C/W θja is specified for worst case conditions when devices are soldered in circuit boards for surface-mount packages. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. B Page 5 of
TYPICAL PERFORMANCE CHARACTERISTICS NUMBER OF AMPLIFIERS 25 5 5 V SY = ±2V T A = 25 C 6 4 4 6 VOLTAGE (µv) 323-B-2 NUMBER OF AMPLIFIERS 6 4 2 8 6 4 2 OFFSET VOLTAGE (µv/ C) V SY = +3.5V/.5V 2 3 4 5 6 7 8 9 323-B-5 Figure 2. Input Offset Voltage Figure 5. Offset Voltage Drift 2 V SY = ±3V 5 4 V SY = ±3V T A = 25 C 3 NUMBER OF AMPLIFIERS 8 6 4 2 2 3 4 5 6 7 8 9 OFFSET VOLTAGE (µv/ C) 323-B-3 INPUT BIAS CURRENT (pa) 3 4 5 5. 2.5. 7.5 5. 2.5 2.5 5. 7.5. 2.5 5. V CM (V) 323-B-6 Figure 3. Offset Voltage Drift Figure 6. Input Bias Current vs. VCM 8 6 V SY = +3.5V/.5V. V SY = ±3V T A = 25 C NUMBER OF AMPLIFIERS 4 2 8 6 4 INPUT BIAS CURRENT (pa).2.3.4.5.6.7 2 4 3 3 VOLTAGE (µv) 323-B-4.8.9 5. 2.5. 7.5 5. 2.5 2.5 5. 7.5. 2.5 5. V CM (V) 323-B-7 Figure 4. Input Offset Voltage Figure 7. Input Bias Current vs. VCM Rev. B Page 6 of
V SY = ±3V V CM = V 5 4 V SY = 5V INPUT BIAS CURRENT (pa). 5 25 25 5 75 25 5 TEMPERATURE ( C) 323-B-8 INPUT OFFSET VOLTAGE (µv) 3 3 4 5 2 3 4 V CM (V) 323-B- Figure 8. Input Bias Current vs. Temperature Figure. Input Offset Voltage vs. VCM 2..5 V SY = +5V OR ±5V M INPUT BIAS CURRENT (pa)..5.5. OPEN-LOOP GAIN (V/V) M k V SY = ±3V V SY = +5V.5 2. 5 4 3 2 2 3 5 5 V CM (V) Figure 9. Input Bias Current vs. VCM 323-B-9 k. LOAD RESISTANCE (kω) Figure 2. Open-Loop Gain vs. Load Resistance 323-B-2 9 V SY = ±3V a INPUT OFFSET VOLTAGE (µv) 8 7 6 5 4 3 5 2 9 6 3 3 6 9 2 5 V CM (V) 323-B- OPEN-LOOP GAIN (V/mV) d b c e a. V SY = ±3V, V O = ±V, R L = kω b. V SY = ±3V, V O = ±V, R L = 2kΩ c. V SY = +5V, V O = +.5V/+4.5V, R L = 2kΩ d. V SY = +5V, V O = +.5V/+4.5V, R L = kω e. V SY = +5V, V O = +.5V/+4.5V, R L = 6Ω 4 25 95 25 TEMPERATURE ( C) 323-B-3 Figure. Input Offset Voltage vs. VCM Figure 3. Open-Loop Gain vs. Temperature Rev. B Page 7 of
6 5 V SY = ±3V k V SY = ±3V OFFSET VOLTAGE (µv) 4 3 R L = kω R L = 6Ω R L = kω V SY OUTPUT VOLTAGE (mv) k V OL V OH 3 4 5 5 5 5 OUTPUT VOLTAGE (V) Figure 4. Input Error Voltage vs. Output Voltage for Resistive Loads 323-B-4... LOAD CURRENT (ma) Figure 7. Output Saturation Voltage vs. Load Current 323-B-7 INPUT VOLTAGE (µv) 25 5 5 5 5 R L = kω POS RAIL R L = kω R L = kω R L = kω R L = kω NEG RAIL V SY = ±5V V SY OUTPUT VOLTAGE (mv) k k V SY = 5V V OL V OH 25 5 5 25 3 OUTPUT VOLTAGE FROM SUPPLY RAILS (mv) Figure 5. Input Error Voltage vs. Output Voltage within 3 mv of Supply Rails 323-B-5... LOAD CURRENT (ma) Figure 8. Output Saturation Voltage vs. Load Current 323-B-8 QUIESCENT CURRENT (µa) 8 7 +25 C 6 55 C +25 C 5 4 3 4 8 2 6 24 28 TOTAL SUPPLY VOLTAGE (V) 323-B-6 GAIN (db) 7 6 5 4 3 GAIN V SY = ±3V R L = 2kΩ C L = 4pF PHASE 3 35 k k M M 5M 35 27 225 8 35 9 45 45 9 PHASE (Degrees) 323-B-9 Figure 6. Quiescent Current vs. Supply Voltage at Different Temperatures Figure 9. Open-Loop Gain and Phase Margin vs. Frequency Rev. B Page 8 of
7 6 5 V SY = 5V R L = 2kΩ C L = 4pF 35 27 225 4 V SY = ±3V GAIN (db) 4 3 GAIN PHASE 8 35 9 45 PHASE (Degrees) CMRR (db) 8 6 4 45 9 3 35 k k M M 5M Figure. Open Loop Gain and Phase Margin vs. Frequency 323-B- 4 6 k k k M M Figure 23. CMRR vs. Frequency 323-B-23 7 6 5 V SY = ±3V R L = 2kΩ C L = 4pF 4 V SY =5V GAIN (db) 4 3 G = G = CMRR (db) 8 6 4 G = 3 k k k M M 5M Figure 2. Closed-Loop Gain vs. Frequency 323-B-2 4 6 k k k M M Figure 24. CMRR vs. Frequency 323-B-24 7 6 5 V SY = 5V R L = 2kΩ C L = 4pF 4 V SY = ±3V GAIN (db) 4 3 G = G = PSRR (db) 8 6 4 PSRR +PSRR G = 3 k k k M M 5M Figure 22. Closed-Loop Gain vs. Frequency 323-B-22 4 6 k k k M M Figure 25. PSRR vs. Frequency 323-B-25 Rev. B Page 9 of
4 V SY =5V INPUT V SY = ±3V PSRR (db) 8 6 4 PSRR +PSRR VOLTAGE (V/DIV) OUTPUT 4 6 k k k M M 323-B-26 TIME (4µs/DIV) 323-B-29 Figure 26. PSRR vs. Frequency Figure 29. No Phase Reversal Z OUT (Ω) 3 V SY = ±3V 27 24 8 5 9 G = G = 6 G = 3 k k k M M M Figure 27. Output Impedance vs. Frequency 323-B-27 OUTPUT SWING (V) 5 5 5 TS + (%) TS (%) TS + (.%) TS (.%) 5.5..5 2. 2.5 SETTLING TIME (µs) Figure 3. Output Swing and Error vs. Settling Time 323-B-3 Z OUT (Ω) 3 V SY =5V 27 24 8 5 9 G = G = 6 G = 3 k k k M M M Figure 28. Output Impedance vs. Frequency 323-B-28 OVERSHOOT (%) 7 6 5 4 3 V S = ±3V R L = kω V IN = mv p-p A V = + OS OS+ k CAPACITANCE (pf) Figure 3. Small Signal Overshoot vs. Load Capacitance 323-B-3 Rev. B Page of
OVERSHOOT (%) 7 6 5 4 3 V S = ±2.5V R L = kω V IN = mv p-p A V = + OS+ OS k CAPACITANCE (pf) Figure 32. Small Signal Overshoot vs. Load Capacitance 323-B-32 VOLTAGE (nv) 56 49 42 35 28 2 4 7 V SY = ±3V 9.7nV/ Hz 2 3 4 5 6 7 8 9 FREQUENCY (khz) Figure 35. Voltage Noise Density 323-B-35 V SY = ±3V A VO =,V/V 56 49 V SY = 5V VOLTAGE (5mV/DIV) VOLTAGE (nv) 42 35 28 2 6.7nV/ Hz 4 TIME (s/div) Figure 33.. Hz to Hz Noise 323-B-33 7 2 3 4 5 6 7 8 9 FREQUENCY (khz) Figure 36. Voltage Noise Density 323-B-36 V SY = ±2.5V A VO =,V/V 4 5 VOLTAGE (5mV/DIV) NOISE (db) 6 7 8 9 V SY = ±5V, V IN = 9V p-p V SY = ±3V, V IN = 8V p-p TIME (s/div) Figure 34.. Hz to Hz Noise 323-B-34 V SY = ±2.5V, V IN = 4.5V p-p k k k Figure 37. Total Harmonic Distortion + Noise vs. Frequency 323-B-37 Rev. B Page of
kω 2kΩ V IN 2kΩ 2kΩ 8 9 GAIN (db) 3 V IN = 9V p-p V IN = 4.5V p-p V IN = 8V p-p 4 5 6 k k k 323-B-49 Figure 38. Channel Separation Rev. B Page 2 of
APPLICATIONS The AD862x is one of the smallest and most economical JFETs offered. It has true single-supply capability and has an input voltage range that extends below the negative rail, allowing the part to accommodate input signals below ground. The rail-to-rail output of the AD862x provides the maximum dynamic range in many applications. To provide a low offset, low noise, high impedance input stage, the AD862x uses n-channel JFETs The input common-mode voltage extends from.2 V below VS to 2 V below +VS. Driving the input of the amplifier, configured in unity gain buffer, closer than 2 V to the positive rail causes an increase in common-mode voltage error, as illustrated in Figure 5, and a loss of amplifier bandwidth. This loss of bandwidth causes the rounding of the output waveforms shown in Figure 39 and Figure 4, which have inputs that are V and V from +VS, respectively. VOLTAGE (2V/DIV) V SY =5V INPUT OUTPUT TIME (2µs/DIV) Figure 39. Unity Gain Follower Response to V to 4 V Step 323-B-38 The AD862x will not experience phase reversal with input signals close to the positive rail, as shown in Figure 29. For input voltages greater than +VSY, a resistor in series with the AD862x s noninverting input prevents phase reversal at the expense of greater input voltage noise. This current limiting resistor should also be used if there is a possibility of the input voltage exceeding the positive supply by more than 3 mv, or if an input voltage is applied to the AD862x when ±VSY =. Either of these conditions will damage the amplifier if the condition exists for more than seconds. A kω resistor allows the amplifier to withstand up to V of continuous overvoltage, while increasing the input voltage noise by a negligible amount. VOLTAGE (2V/DIV) V SY =5V INPUT OUTPUT 323-B-39 TIME (2µs/DIV) Figure 4. Unity Gain Follower Response to V to 5 V Step Rev. B Page 3 of
The AD862x can safely withstand input voltages 5 V below VSY if the total voltage between the positive supply and the input terminal is less than 26 V. Figure 4 through Figure 43 show the AD862x in different configurations accommodating signals close to the negative rail. The amplifier input stage typically maintains picoamp-level input currents across that input voltage range. kω V mv 3mV kω +5V kω V SY = 5V kω +5V V SY = 5V, V V 2.5V VOLTAGE (mv/div) VOLTAGE (V/DIV) TIME (2µs/DIV) Figure 43. Gain of Two Inverter Response to mv Step, Centered mv below Ground 323-B-42 TIME (2µs/DIV) Figure 4. Gain of Two Inverter Response to 2.5 V Step, Centered.25 V below Ground 323-B-4 The AD862x is designed for 6 nv/ Hz wideband input voltage noise and maintains low noise performance to low frequencies, as shown in Figure 35. This noise performance, along with the AD862x s low input current and current noise, means that the AD862x contributes negligible noise for applications with large source resistances. 6mV mv V 5V 6Ω The AD862x has a unique bipolar rail-to-rail output stage that swings within 5 mv of the rail when up to 2 ma of current is drawn. At larger loads, the drop-out voltage increases as shown in Figure 7 and Figure 8. The AD862x s wide bandwidth and fast slew rate allows it to be used with faster signals than previous single-supply JFETs. Figure 44 shows the response of AD862x, configured in unity gain, to a VIN of V p-p at 5 khz. The FPBW of the part is close to khz. V SY = ±3V R L = 6Ω VOLTAGE (mv/div) V SY = 5V R L = 6Ω TIME (2µs/DIV) Figure 42. Unity Gain Follower Response to 4 mv Step, Centered 4 mv above Ground 323-B-4 VOLTAGE (5V/DIV) 323-B-43 TIME (5µs/DIV) Figure 44. Unity Gain Follower Response to V, 5 khz Input Signal Rev. B Page 4 of
MINIMIZING INPUT CURRENT The AD862x is guaranteed to pa max input current with a ±3 V supply voltage at room temperature. Careful attention to how the amplifier is used will maintain or possibly better this performance. The amplifier s operating temperature should be kept as low as possible. Like other JFET input amplifiers, the AD862x s input current doubles for every C rise in junction temperature, as illustrated in Figure 8. On-chip power dissipation raises the device operating temperature, causing an increase in input current. Reducing supply voltage to cut power dissipation reduces the AD862x s input current. Heavy output loads can also increase chip temperature; maintaining a minimum load resistance of kω is recommended. The AD862x is designed for mounting on PC boards. Maintaining picoampere resolution in those environments requires a lot of care. Both the board and the amplifier s package have finite resistance. Voltage differences between the input pins and other pins as well as PC board metal traces may cause parasitic currents larger than the AD862x s input current, unless special precautions are taken. For proper board layout to ensure the best result, refer to the ADI website for proper layout seminar material. Two common methods of minimizing parasitic leakages that should be used are guarding of the input lines and maintaining adequate insulation resistance. Contaminants such as solder flux on the board s surface and the amplifier s package can greatly reduce the insulation resistance between the input pin and traces with supply or signal voltages. Both the package and the board must be kept clean and dry. PHOTODIODE PREAMPLIFIER APPLICATION The low input current and offset voltage levels of the AD862x, together with its low voltage noise, make this amplifier an excellent choice for preamplifiers used in sensitive photodiode applications. In a typical photovoltaic preamp circuit, shown in Figure 45, the output of the amplifier is equal to where: V OUT = ID(Rf) = R (P)Rf ID = photodiode signal current (A) Rp = photodiode sensitivity (A/W) Rf = value of the feedback resistor, in Ω P = light power incident to photodiode surface, in W The amplifier s input current, IB, contributes an output voltage error proportional to the value of the feedback resistor. The offset voltage error, VOS, causes a small current error due to the photodiode s finite shunt resistance, RD. p The resulting output voltage error, VE, is equal to R f VE = + VOS + Rf(I R D A shunt resistance on the order of MΩ is typical for a small photodiode. Resistance RD is a junction resistance that typically drops by a factor of two for every C rise in temperature. In the AD862x, both the offset voltage and drift are low, which helps minimize these errors. With IB values of pa and VOS of 5 mv, VE for Figure 45 is very negligible. Also, the circuit in Figure 45 results in an SNR value of 95 db for a signal bandwidth of 3 khz. PHOTODIODE R D MΩ I B C4 5pF I B V OS C F 5pF B R F.5MΩ ) AD8627 Figure 45. A Photodiode Model Showing DC Error OUTPUT OUTPUT AMPLIFIER FOR DIGITAL-TO-ANALOG CONVERTERS Many system designers use amplifiers as buffers on the output of amplifiers to increase the DAC s output driving capability. The high resolution current output DACs need high precision amplifiers on their output as current to voltage converters (I/V). Additionally, many DACs operate with a single supply of 5 V. In a single-supply application, selection of a suitable op amp may be more difficult because the output swing of the amplifier does not usually include the negative rail, in this case AGND. This can result in some degradation of the DAC s specified performance unless the application does not use codes near zero. The selected op amp needs to have very low offset voltage for a 4-bit DAC, the DAC LSB is 3 µv with a 5 V reference to eliminate the need for output offset trims. Input bias current should also be very low because the bias current multiplied by the DAC output impedance (about kω in some cases) adds to the zero code error. Rail-to-rail input and output performance is desired. For fast settling, the slew rate of the op amp should not impede the settling time of the DAC. Output impedance of the DAC is constant and code independent, but in order to minimize gain errors, the input impedance of the output amplifier should be as high as possible. The AD862x, with very high input impedance, IB of pa, and fast slew rate, is an ideal amplifier for these types of applications. A typical configuration with a popular DAC is shown in Figure 46. In these situations, the amplifier adds another time constant to the system, increasing the settling time of the output. The AD862x, with 5 MHz of BW, helps in achieving a faster effective settling time of the combined DAC and amplifier. 323-B-44 Rev. B Page 5 of
SERIAL INTERFACE.µF *AD5552 ONLY V DD V REFF * V REFS * CS DIN 5V 2.5V SCLK LDAC* DGND.µF µf AD555/AD5552 AGND OUT Figure 46. Unipolar Output AD8627 UNIPOLAR OUTPUT In applications with full 4-quadrant multiplying capability or a bipolar output swing, the circuit in Figure 47 can be used. In this circuit, the first and second amplifiers provide a total gain of 2, which increases the output voltage span to V. Biasing the external amplifier with a V offset from the reference voltage results in a full 4-quadrant multiplying circuit. V VREF ADR kω 5kΩ kω +3V /2 AD8626 5V 323-B-45 V OUT V < V OUT < +V EIGHT-POLE SALLEN KEY LOW-PASS FILTER The AD862x s high input impedance and dc precision make it a great selection for active filters. Due to the very low bias current of the AD862x, high value resistors can be used to construct low frequency filters. The AD862x s picoamp-level input currents contribute minimal dc errors. Figure 49 shows an example, a Hz, 8-pole Sallen Key filter constructed using the AD862x. Different numbers of the AD862x can be used depending on the desired response, which is shown in Figure 48. The high value used for R minimizes interaction with signal source resistance. Pole placement in this version of the filter minimizes the Q associated with the lower pole section of the filter. This eliminates any peaking of the noise contribution of resistors in the preceding sections, minimizing the inherent output voltage noise of the filter. VOLTAGE (V).2.8.4 V4 V2 V V3 3V V DD V REF X R FB X ONE CHANNEL AD5544 V SS A GND F A GND X DIGITAL INTERFACE CONNECTIONS OMITTED FOR CLARITY /2 AD8626 323-B-46. k Figure 48. Frequency Response Output at Different Stages of the Low-Pass Filter 323-B-47 Figure 47. 4-Quadrant Multiplying Application Circuit Rev. B Page 6 of
R 62.3kΩ C µf V IN V3 D C2 96.9µF R2 62.3kΩ 3 D 2 V DD 4 U V EE R3 25kΩ V /4 AD8625 R 9.4kΩ C4 69.4µF R5 9.4kΩ D C3 µf U2 /4 AD8625 R4 25kΩ V2 R 286.5kΩ C6 3.86µF R7 286.5kΩ C5 µf U3 /4 AD8625 V3 R2 85.8kΩ R9 85.8kΩ C7 µf U4 V4 D R6 25kΩ C8 3.85µF D /4 AD8625 R8 25kΩ 323-B-48 Figure 49. Hz, 8-Pole Sallen Key Low-Pass Filter Rev. B Page 7 of
OUTLINE DIMENSIONS 2. BSC 8.75 (.3445) 8.55 (.3366).25 BSC 5 4 2 3 2. BSC 4. (.575) 3.8 (.496) 4 8 7 6. (.244) 5.8 (.2283)..9.7. MAX PIN.3.5. COPLANARITY.65 BSC. MAX SEATING PLANE.22.8.46 8 4 COMPLIANT TO JEDEC STANDARDS MO-3AA Figure 5. 5-Lead Plastic Surface-Mount Package [SC7] (KS-5) Dimensions shown in millimeters.36.26.25 (.98). (.39) COPLANARITY..27 (.5) BSC.5 (.).3 (.22).75 (.689).35 (.53) SEATING PLANE.25 (.98).7 (.67) COMPLIANT TO JEDEC STANDARDS MS-2AB CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN 8.5 (.97) 45.25 (.98).27 (.5).4 (.57) Figure 53. 4-Lead Standard Small Outline Package [SOIC] Narrow Body (R-4) Dimensions shown in millimeters and (inches) 4. (.574) 3.8 (.497) 5. (.968) 4.8 (.89) 8 5 4 6. (.244) 5.8 (.2284) 5. 5. 4.9 4 8.25 (.98). (.4) COPLANARITY..27 (.5) BSC SEATING PLANE.75 (.688).35 (.532).5 (.).3 (.22).25 (.98).7 (.67) 8.5 (.96).25 (.99) 45.27 (.5).4 (.57) COMPLIANT TO JEDEC STANDARDS MS-2AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Figure 5. 8-Lead Standard Small Outline Package [SOIC] Narrow Body (R-8) 3. BSC.5..8 4.5 4.4 4.3 PIN.5.5.65 BSC.3.9 7 6.4 BSC. MAX SEATING PLANE..9 COPLANARITY. 8 COMPLIANT TO JEDEC STANDARDS MO-53AB- Figure 54. 4-Lead Thin Shrink Small Outline Package [TSSOP] (RU-4) Dimensions shown in millimeters.75.6.45 3. BSC 8 5 4 4.9 BSC PIN.65 BSC.5..38.22 COPLANARITY.. MAX SEATING PLANE.23.8 8 COMPLIANT TO JEDEC STANDARDS MO-87AA.8.6.4 Figure 52. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters Rev. B Page 8 of
ORDERING GUIDE Model Temperature Range Package Description Package Option Branding AD8627AKS-REEL 4 C to +85 C 5-Lead SC7 KS-5 B9A AD8627AKS-REEL7 4 C to +85 C 5-Lead SC7 KS-5 B9A AD8627AKS-R2 4 C to +85 C 5-Lead SC7 KS-5 B9A AD8627AR 4 C to +85 C 8-Lead SOIC R-8 AD8627AR-REEL 4 C to +85 C 8-Lead SOIC R-8 AD8627AR-REEL7 4 C to +85 C 8-Lead SOIC R-8 AD8626ARM-REEL 4 C to +85 C 8-Lead MSOP RM-8 BJA AD8626ARM-R2 4 C to +85 C 8-Lead MSOP RM-8 BJA AD8626AR 4 C to +85 C 8-Lead SOIC R-8 AD8626AR-REEL 4 C to +85 C 8-Lead SOIC R-8 AD8626AR-REEL7 4 C to +85 C 8-Lead SOIC R-8 AD8625ARU 4 C to +85 C 4-Lead TSSOP RU-4 AD8625ARU-REEL 4 C to +85 C 4-Lead TSSOP RU-4 AD8625AR 4 C to +85 C 4-Lead SOIC R-4 AD8625AR-REEL 4 C to +85 C 4-Lead SOIC R-4 AD8625AR-REEL7 4 C to +85 C 4-Lead SOIC R-4 Rev. B Page 9 of
NOTES 4 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C323--/4(B) Rev. B Page of