FEATURES SYMBOL QUICK REFERENCE DATA Low threshold voltage s V DS = -6 V Fast switching Logic level compatible I D = -.3 A Subminiature surface mount g package R DS(ON) 2.5 Ω (V GS = - V) d GENERAL DESCRIPTION PINNING SOT23 P-channel, enhancement mode, PIN DESCRIPTION logic level, field-effect power transistor. This device has low gate threshold voltage and extremely fast switching making it ideal for 2 source battery powered applications and high speed digital interfacing. 3 drain 3 Top view The is supplied in the SOT23 subminiature surface mounting package. 2 LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 34) SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT V DS Drain-source voltage - -6 V V DGR Drain-gate voltage R GS = 2 kω - -6 V V GS Gate-source voltage - ± 2 V I D Drain current (DC) T a = 25 C - -.3 A T a = C - -.9 A I DM Drain current (pulse peak value) T a = 25 C - -.2 A P tot Total power dissipation T a = 25 C -.47 W T a = C -.7 W T stg, T j Storage & operating temperature - 55 5 C THERMAL RESISTANCES SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT R th j-a Thermal resistance junction to FR4 board, minimum 3 - K/W ambient footprint August 998 Rev.
ELECTRICAL CHARACTERISTICS T j = 25 C unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT V (BR)DSS Drain-source breakdown V GS = V; I D = - µa -6 - - V voltage V GS(TO) Gate threshold voltage V DS = V GS ; I D = - ma - -.9 - V T j = 5 C -.4 - - V R DS(ON) Drain-source on-state V GS = - V; I D = -6 ma - 2. 2.5 Ω resistance V GS = -4.5 V; I D = -8 ma - 2.7 3.75 Ω V GS = - V; I D = -6 ma; T j = 5 C - 3.6 4.25 Ω g fs Forward transconductance V DS = -48 V; I D = -6 ma..35 - S I GSS Gate source leakage current V GS = ±2 V; V DS = V - ± ± na I DSS Zero gate voltage drain V DS = -48 V; V GS = V; - -5 - na current T j = 5 C - -.3 - µa Q g(tot) Total gate charge I D = -.5 A; V DD = - V; V GS = - V - 3 - nc Q gs Gate-source charge -.5 - nc Q gd Gate-drain (Miller) charge -.4 - nc t d on Turn-on delay time V DD = - V; I D = -.5 A; - 2 - ns t r Turn-on rise time V GS = - V; R G = 6 Ω - 4.5 - ns t d off Turn-off delay time Resistive load - 45 - ns t f Turn-off fall time - 2 - ns C iss Input capacitance V GS = V; V DS = -48 V; f = MHz - 7 - pf C oss Output capacitance - 5 - pf C rss Feedback capacitance - 5 - pf REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS T j = 25 C unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT I DR Continuous reverse drain T a = 25 C - - -.3 A current I DRM Pulsed reverse drain current - - -.2 A V SD Diode forward voltage I F = -.38 A; V GS = V - -.97 -.3 V t rr Reverse recovery time I F = -.25 A; -di F /dt = A/µs; - 38 - ns Q rr Reverse recovery charge V GS = V; V R = -48 V - 58 - nc August 998 2 Rev.
2 Normalised Power Dissipation, PD (%) Peak Pulsed Drain Current, IDM (A) 8 6 4 2 25 5 75 25 5 Ambient Temperature, Ta (C) Fig.. Normalised power dissipation. PD% = P D /P D 25 C = f(t a ). D =.5.2..5.2 single pulse E-6 E-5 E-4 E-3 E-2 E- E+ E+ Pulse width, tp (s) P D Fig.4. Transient thermal impedance. Z th j-a = f(t); parameter D = t p /T tp T D = tp/t 2 8 6 4 2 Normalised Drain Current, ID (%) 25 5 75 25 5 Ambient Temperature, Ta (C) Fig.2. Normalised continuous drain current. ID% = I D /I D 25 C = f(t a ); conditions: V GS - V - -.8 -.6 -.4 -.2 Drain current, ID (A) -.5 - -.5 Drain-Source Voltage, VDS (V) VGS = - V -4.5 V -2.5 V -2.3 V -2. V -.9 V -.7 V -.5 V Fig.5. Typical output characteristics, T j = 25 C. I D = f(v DS ); parameter V GS -2... Peak Pulsed Drain Current, IDM (A) RDS(on) = VDS/ ID d.c. tp = us us ms ms ms Drain-Source Voltage, VDS (V) Fig.3. Safe operating area. T a = 25 C I D & I DM = f(v DS ); I DM single pulse; parameter t p 9 8 7 6 5 4 3 2 Drain-Source On Resistance, RDS(on) (Ohms) -.5 V -.7 V -.9 V -2. V -2.3 V -2.5 V -. -.2 -.3 -.4 Drain Current, ID (A) PHP222-4.5 V VGS = - V -.5 Fig.6. Typical on-state resistance, T j = 25 C. R DS(ON) = f(i D ); parameter V GS August 998 3 Rev.
Drain Current, ID (A) - -.9 VDS > ID X RDS(on) -.8 -.7 -.6 -.5 -.4 -.3 -.2 -. -.5 - -.5-2 -2.5-3 -3.5-4 Gate-Source Voltage, VGS (V) 5 C -4.5 Fig.7. Typical transfer characteristics. I D = f(v GS ) -5-5.5.8.6.4.2.8.6.4.2 Threshold Voltage, VGS(to), (V) typical minimum 25 5 75 25 5 Junction Temperature, Tj (C) Fig.. Gate threshold voltage. V GS(TO) = f(t j ); conditions: I D = ma; V DS = V GS.7.6.5.4.3 Transconductance, gfs (S) VDS > ID X RDS(on) 5 C E- E-2 E-3 E-4 Drain Current, ID (A) VDS = -5 V.2 E-5. -. -.2 -.3 -.4 -.5 -.6 -.7 Drain Current, ID (A) -.8 -.9 Fig.8. Typical transconductance, T j = 25 C. g fs = f(i D ) - E-6 E-7-2.5-2 -.5 - Gate-Source Voltage, VGS (V) Fig.. Sub-threshold drain current. I D = f(v GS) ; conditions: T j = 25 C.9 2.8.7.6.5.4.3.2..9.8.7.6.5 Normalised Drain-Source On Resistance RDS(ON) @ Tj RDS(ON) @ 25C VGS = - V -4.5 V 25 5 75 25 5 Junction Temperature, Tj (C) Fig.9. Normalised drain-source on-state resistance. R DS(ON) /R DS(ON)25 C = f(t j ) Capacitances, Ciss, Coss, Crss (pf) Ciss Coss Crss -. -. -. -. Drain-Source Voltage, VDS (V) Fig.2. Typical capacitances, C iss, C oss, C rss. C = f(v DS ); conditions: V GS = V; f = MHz August 998 4 Rev.
-4-2 - Gate-source voltage, VGS (V) VDD = V RD = 2 Ohms 3.5 3 2.5 Source-Drain Diode Current, IF (A) -8-6 -4-2 2 3 4 5 Gate charge, (nc) Fig.3. Typical turn-on gate-charge characteristics. V GS = f(q G ) 2.5.5 5 C.5.5 2 Drain-Source Voltage, VSDS (V) Fig.4. Typical reverse diode current. I F = f(v SDS ); conditions: V GS = V; parameter T j August 998 5 Rev.
MECHANICAL DATA Plastic surface mounted package; 3 leads SOT23 D B E A X H E v M A 3 Q A A 2 c e bp w M B Lp e detail X 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A max.. mm..9 b p c D E e e H E L p Q v w.48.38.5.9 3. 2.8.4.2.9.95 2.5 2..45.5.55.45.2. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE SOT23 97-2-28 Fig.5. SOT23 surface mounting package. Notes. This product is supplied in anti-static packaging. The gate-source input must be protected against static discharge during transport or handling. 2. Refer to SMD Footprint Design and Soldering Guidelines, Data Handbook SC8. 3. Epoxy meets UL94 V at /8". August 998 6 Rev.
DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications. Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 34). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. Philips Electronics N.V. 998 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. August 998 7 Rev.
Go to ' home page Select Catalog & Datasheets of 2 Sta & Go... part Catalog by Function Discrete semiconductors Audio Clocks and Watches Data communications Microcontrollers Peripherals Standard analog Video Wired communications Wireless communications ; Description Features Datasheet Products, packages, availability and ordering Find similar products Support & tools Inf To be Catalog by System Automotive Consumer Multimedia Systems Communications PC/PC-peripherals Cross reference Models Packages Application notes Selection guides Other technical documentation End of Life information Datahandbook system Relevant Links About catalog tree About search About this site Subscribe to enews Catalog & Datasheets Search Description P-channel, enhancement mode, logic level, field-effect power transistor. This device voltage and extremely fast switching making it ideal for battery powered applications digital interfacing. The is supplied in the SOT23 subminiature surface mounting package. Features Low threshold voltage Fast switching Logic level compatible Subminiature surface mount package Datasheet Type nr. Title P-channel enhancement mode Publication release date Datasheet status -Aug-98 Product Specification Page count File size (kb 7 5 Products, packages, availability and ordering Partnumber North American Partnumber T/R Order code (2nc) 934 547 725 marking/packing package device statu Standard Marking * Reel Pack, SMD, Low Profile Standard SOT23 Full producti
2 of 2 /T3 934 547 7235 Standard Marking * Reel Pack, SMD, Low Profile, Large SOT23 Full producti Find similar products: links to the similar products page containing an overview of products function or related to the part number(s) as listed on this page. The similar products products from the same catalog tree(s), relevant selection guides and products from category. Support &tools Spice model of Copyright 2 Royal Philips Electronics All rights reserved. Terms and conditions.