Datasheet N-channel 600 V, 85 mω typ., 30 A, MDmesh M6 Power MOSFET in a TO LL HV package Features Order code V DS R DS(on) max. I D 600 V 99 mω 30 A Drain (TAB) Reduced switching losses Lower R DS(on) per area vs previous generation Low gate input resistance 100% avalanche tested Zener-protected High-creepage package Excellent switching performance thanks to the extra driving source pin Gate(1) Driver source (2) Power source (3, 4, 5, 6, 7,8) N-chG1DS2PS345678DTABZ Product status link Applications Switching applications Description The new MDmesh M6 technology incorporates the most recent advancements to the well-known and consolidated MDmesh family of SJ MOSFETs. STMicroelectronics builds on the previous generation of MDmesh devices through its new M6 technology, which combines excellent R DS(on) per area improvement with one of the most effective switching behaviors available, as well as a user-friendly experience for maximum end-application efficiency. Product summary Order code Marking Package Packing 36N60M6 TO-LL HV Tape and reel DS12120 - Rev 2 - October 2018 For further information contact your local STMicroelectronics sales office. www.st.com
Electrical ratings 1 Electrical ratings Table 1. Absolute maximum ratings Symbol Parameter Value Unit V GS Gate-source voltage ±25 V I D Drain current (continuous) at T C = 25 C 30 A I D Drain current (continuous) at T C = 100 C 19 A I (1) DM Drain current (pulsed) 102 A P TOT Total dissipation at T C = 25 C 230 W dv/dt (2) Peak diode recovery voltage slope 15 V/ns dv/dt (3) MOSFET dv/dt ruggedness 100 V/ns T stg T j Storage temperature range Operating junction temperature range -55 to 150 C 1. Pulse width limited by safe operating area. 2. I SD 30 A, di/dt 400 A/µs, V DS(peak) < V (BR)DSS, V DD = 400 V 3. V DS 480 V Table 2. Thermal data Symbol Parameter Value Unit R thj-case Thermal resistance junction-case 0.54 C/W R (1) thj-pcb Thermal resistance junction-pcb 46 C/W 1. When mounted on an FR-4 board of 1 inch², 2oz Cu. Table 3. Avalanche characteristics Symbol Parameter Value Unit I AR E AS Avalanche current, repetitive or not repetitive (pulse width limited by T jmax ) Single pulse avalanche energy (starting T j = 25 C, I D = I AR, V DD = 50 V) 5 A 750 mj DS12120 - Rev 2 page 2/14
Electrical characteristics 2 Electrical characteristics T C = 25 C unless otherwise specified Table 4. On/off states Symbol Parameter Test conditions Min. Typ. Max. Unit V (BR)DSS Drain-source breakdown voltage V GS = 0 V, I D = 1 ma 600 V V GS = 0 V, V DS = 600 V 1 µa I DSS Zero gate voltage drain current V GS = 0 V, V DS = 600 V, T C = 125 C (1) 100 µa I GSS Gate-body leakage current V DS = 0 V, V GS = ±25 V ±5 µa V GS(th) Gate threshold voltage V DS = V GS, I D = 250 µa 3.25 4 4.75 V R DS(on) Static drain-source on-resistance V GS = 10 V, I D = 15 A 85 99 mω 1. Defined by design, not subject to production test. Table 5. Dynamic Symbol Parameter Test conditions Min. Typ. Max. Unit C iss Input capacitance - 1960 - pf C oss Output capacitance V DS = 100 V, f = 1 MHz, V GS = 0 V - 93 - pf C rss Reverse transfer capacitance - 6 - pf C oss eq. (1) Equivalent output capacitance V DS = 0 to 480 V, V GS = 0 V - 332 - pf R G Intrinsic gate resistance f = 1 MHz, I D = 0 A - 1.6 - Ω Q g Total gate charge V DD = 480 V, I D = 30 A, - 44.3 - nc Q gs Gate-source charge V GS = 0 to 10 V - 10.1 - nc (see Figure 14. Test circuit for gate Q gd Gate-drain charge charge behavior) - 25 - nc 1. C oss eq. is defined as a constant equivalent capacitance giving the same charging time as C oss when V DS increases from 0 to 80% V DSS Table 6. Switching times Symbol Parameter Test conditions Min. Typ. Max. Unit t d(on) Turn-on delay time V DD = 300 V, I D = 15 A, - 15.2 - ns t r Rise time R G = 4.7 Ω, V GS = 10 V - 5.3 - ns t d(off) Turn-off delay time (see Figure 13. Switching times test circuit for resistive load and - 50.2 - ns t f Fall time Figure 18. Switching time waveform) - 7.3 - ns DS12120 - Rev 2 page 3/14
Electrical characteristics Table 7. Source-drain diode Symbol Parameter Test conditions Min. Typ. Max. Unit I SD Source-drain current - 30 A I (1) SDM Source-drain current (pulsed) - 102 A V (2) SD Forward on voltage V GS = 0 V, I SD = 30 A - 1.6 V t rr Reverse recovery time I SD = 30 A, di/dt = 100 A/µs, - 340 ns Q rr Reverse recovery charge V DD = 60 V - 5.3 µc I RRM Reverse recovery current (see Figure 15. Test circuit for inductive load switching and diode - 31 A recovery times) t rr Reverse recovery time I SD = 30 A, di/dt = 100 A/µs, - 430 ns Q rr Reverse recovery charge V DD = 60 V, T j = 150 C - 7.7 µc I RRM Reverse recovery current (see Figure 15. Test circuit for inductive load switching and diode recovery times) - 36 A 1. Pulse width is limited by safe operating area. 2. Pulse test: pulse duration = 300 μs, duty cycle 1.5%. DS12120 - Rev 2 page 4/14
Electrical characteristics (curves) 2.1 Electrical characteristics (curves) Figure 1. Safe operating area Figure 2. Thermal impedance I D (A) GADG240920181102SOA K δ = 0.5 Zthjc_opt6_9x 10 2 10 1 10 0 Operation in this area is limited by RDS(on) T j 150 C T c = 25 C single pulse t p =1 µs t p =10 µs t p =100 µs t p =1 ms t p =10 ms 10-1 10-2 δ = 0.2 δ = 0.1 δ = 0.05 δ = 0.02 δ = 0.01 Single pulse 10-1 10-1 10 0 10 1 10 2 V DS (V) 10-3 10-6 10-5 10-4 10-3 10-2 10-1 t p (s) Figure 3. Output characteristics Figure 4. Transfer characteristics I D (A) 100 GADG220320170910OCH V GS = 9, 10V I D (A) 100 GADG220320170910TCH 80 80 V DS = 18V 60 V GS = 8V 60 40 20 V GS = 6V V GS = 7V 40 20 V 0 GS = 5V 0 2 4 6 8 10 12 14 16 V DS (V) 0 3 4 5 6 7 8 9 V GS (V) Figure 5. Gate charge vs gate-source voltage Figure 6. Static drain-source on-resistance V GS (V) 12 GADG030220171159QVG V DS (V) V DD = 480 V 600 I D = 30 A RDS(on) mω 91 VGS =10 V GADG010220171211RID 10 V DS 500 89 8 400 87 6 300 85 4 200 83 2 100 81 0 0 10 20 30 40 50 0 Q g (nc) 79 0 5 10 15 20 25 30 I D (A) DS12120 - Rev 2 page 5/14
Electrical characteristics (curves) C (pf) Figure 7. Capacitance variations 10 4 GADG220320170921CVR Figure 8. Normalized gate threshold voltage vs temperature V GS(th) (norm.) 1.1 I D = 250 µa GIPG300920151316VTH 10 3 C ISS 1.0 10 2 f= 1MHz C OSS 0.9 0.8 10 1 C RSS 0.7 10 0 10-1 10 0 10 1 10 2 V DS (V) 0.6-75 -25 25 75 125 T J ( C) Figure 9. Normalized on-resistance vs temperature Figure 10. Normalized V (BR)DSS vs temperature R DS(on) (norm.) 2.2 GIPG300920151317RON V GS = 10 V V (BR)DSS (norm.) 1.08 I D = 1 ma GIPG300920151318BDV 1.8 1.04 1.4 1.00 1.0 0.96 0.6 0.92 0.2-75 -25 25 75 125 T J ( C) 0.88-75 -25 25 75 125 T J ( C) Figure 11. Output capacitance stored energy Figure 12. Source-drain diode forward characteristics EOSS (µj) GADG010220171214EOS V SD (V) GADG010220171212SDF 16 1.1 1.0 T J = -50 C 12 0.9 T J = 25 C 8 0.8 0.7 T J = 150 C 4 0.6 0 0 100 200 300 400 500 600 VDS (V) 0.5 0 5 10 15 20 25 30 I SD (A) DS12120 - Rev 2 page 6/14
Test circuits 3 Test circuits Figure 13. Switching times test circuit for resistive load Figure 14. Test circuit for gate charge behavior VDD RL PW VGS VD RG RL + D.U.T. 2200 µf 3.3 µf VDD VGS pulse width 2200 μf + IG= CONST 2.7 kω 47 kω 100 Ω D.U.T. VG GND1 (driver signal) GND2 (power) 1 kω AM15855v1 GND1 GND2 GADG180720181011SA Figure 15. Test circuit for inductive load switching and diode recovery times Figure 16. Unclamped inductive load test circuit 25Ω G A D D.U.T. S B A FAST DIODE B G A B L=100µH D 3.3 1000 µf + µf VDD VD ID L + 2200 µf 3.3 µf VDD RG S D.U.T. Vi D.U.T. GND1 GND2 AM15857v1 Pw GND1 GND2 AM15858v1 Figure 17. Unclamped inductive waveform Figure 18. Switching time waveform V(BR)DSS t on t off VD t d(on) t r t d(off) t f 90% 90% IDM ID 0 10% V DS 10% VDD VDD V GS 90% AM01472v1 0 10% AM01473v1 DS12120 - Rev 2 page 7/14
Package information 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. DS12120 - Rev 2 page 8/14
TO-LL (HV) package information 4.1 TO-LL (HV) package information Figure 19. TO-LL HV package outline DM00276569_3 DS12120 - Rev 2 page 9/14
TO-LL (HV) package information Table 8. TO-LL HV package mechanical data Dim. mm Min. Typ. Max. A 2.20 2.30 2.40 A1 0.40 0.48 0.60 b 0.80 c 0.46 c1 0.15 C 10.28 10.38 10.48 C2 2.35 2.45 2.55 C3 0.71 D 9.80 9.90 10.00 D2 3.30 3.53 3.73 D3 9.30 9.40 9.50 D4 8.26 8.46 8.66 D5 9.50 9.70 9.90 D6 7.40 D7 2.20 e 1.20 E 11.48 11.68 11.88 E1 5.09 E2 5.66 E3 5.14 E4 0.90 E5 0.72 E6 6.54 6.74 6.94 E7 1.45 E8 0.50 0.70 0.90 K 1.70 1.90 2.10 L 1.05 1.20 1.35 L1 0.25 0.35 0.45 L2 0.40 0.60 0.80 θ 11 DS12120 - Rev 2 page 10/14
TO-LL (HV) package information Figure 20. TO-LL HV recommended footprint (dimensions are in mm) DM00276569_3 DS12120 - Rev 2 page 11/14
Revision history Table 9. Document revision history Date Revision Changes 21-Apr-2017 1 First release. 08-Oct-2018 2 Updated Section 1 Electrical ratings, Section 2 Electrical characteristics and Section 3 Test circuits. Updated Section 4.1 TO-LL (HV) package information. Minor text changes DS12120 - Rev 2 page 12/14
Contents Contents 1 Electrical ratings...2 2 Electrical characteristics...3 2.1 Electrical characteristics (curves)... 5 3 Test circuits...7 4 Package information...8 4.1 TO-LL HV package information...8 Revision history...12 DS12120 - Rev 2 page 13/14
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