Applications l High frequency DC-DC converters l UPS and Motor Control l Lead-Free Benefits l Low Gate-to-Drain Charge to Reduce Switching Losses l Fully Characterized Capacitance Including Effective C OSS to Simplify Design, (See App. Note AN) l Fully Characterized Avalanche Voltage and Current l Typical R DS(on) = 2mΩ Absolute Maximum Ratings PD - 95505 SMPS MOSFET HEXFET Power MOSFET V DSS R DS(on) max I D V 5mΩ 80A TO-220AB Parameter Max. Units I D @ T C = 25 C Continuous Drain Current, V GS @ V 80h I D @ T C = C Continuous Drain Current, V GS @ V 57 A I DM Pulsed Drain Current c 320 P D @T C = 25 C Power Dissipation 260 W Linear Derating Factor.8 W/ C V GS Gate-to-Source Voltage ± 20 V dv/dt Peak Diode Recovery dv/dt e 6 V/ns T J Operating Junction and -55 to 75 T STG Storage Temperature Range C Soldering Temperature, for seconds Mounting torque, 6-32 or M3 screw 300 (.6mm from case ).() N m (lbf in) Thermal Resistance Parameter Typ. Max. Units R θjc Junction-to-Case 0.57 R θcs Case-to-Sink, Flat, Greased Surface 0.50 C/W R θja Junction-to-Ambient 62 Notes through are on page 8 www.irf.com 07/06/04
Static @ T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units V (BR)DSS Drain-to-Source Breakdown Voltage V V (BR)DSS / T J Breakdown Voltage Temp. Coefficient 0. V/ C R DS(on) Static Drain-to-Source On-Resistance 2 5 mω V GS(th) Gate Threshold Voltage 2.0 4.0 V I DSS Drain-to-Source Leakage Current 20 µa 250 I GSS Gate-to-Source Forward Leakage 200 na Gate-to-Source Reverse Leakage -200 Dynamic @ T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions gfs Forward Transconductance 82 V V DS = 25V, I D = 45A Q g Total Gate Charge 8 20 I D = 80A Q gs Gate-to-Source Charge 22 nc V DS = 80V Q gd Gate-to-Drain ("Miller") Charge 26 V GS = V f t d(on) Turn-On Delay Time 5 V DD = 50V t r Rise Time 30 I D = 80A t d(off) Turn-Off Delay Time 6 ns R G = 39Ω t f Fall Time 20 V GS = V f C iss Input Capacitance 3830 V GS = 0V C oss Output Capacitance 480 V DS = 25V C rss Reverse Transfer Capacitance 59 pf ƒ =.0MHz C oss Output Capacitance 3830 V GS = 0V, V DS =.0V, ƒ =.0MHz C oss Output Capacitance 280 V GS = 0V, V DS = 80V, ƒ =.0MHz C oss eff. Effective Output Capacitance 530 V GS = 0V, V DS = 0V to 80V e Avalanche Characteristics Parameter Typ. Max. Units E AS Single Pulse Avalanche Energydh 3 mj I AR Avalanche Currentc 45 A E AR Repetitive Avalanche Energy c 26 mj Diode Characteristics Parameter Min. Typ. Max. Units Conditions V GS = 0V, I D = 250µA Reference to 25 C, I D = ma V GS = V, I D = 45A f V DS = V GS, I D = 250µA V DS = V, V GS = 0V V DS = V, V GS = 0V, T J = 25 C V GS = 20V V GS = -20V Conditions I S Continuous Source Current 80 MOSFET symbol D (Body Diode) A showing the I SM Pulsed Source Current 320 integral reverse G S (Body Diode)ch p-n junction diode. V SD Diode Forward Voltage.3 V T J = 25 C, I S = 80A, V GS = 0V f t rr Reverse Recovery Time 99 50 ns T J = 50 C, I F = 80A, V DD = 50V Q rr Reverse RecoveryCharge 460 700 nc di/dt = A/µs f t on Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LSLD) 2 www.irf.com
I D, Drain-to-Source Current (Α) I D, Drain-to-Source Current (A) I D, Drain-to-Source Current (A) 0 VGS TOP 5V 2V V 6.0V 5.5V 5.0V 4.5V BOTTOM 4.0V VGS TOP 5V 2V V 6.0V 5.5V 5.0V 4.5V BOTTOM 4.0V 4.0V 4.0V 0. 20µs PULSE WIDTH Tj = 25 C 0. V DS, Drain-to-Source Voltage (V) Fig. Typical Output Characteristics 20µs PULSE WIDTH Tj = 75 C 0. V DS, Drain-to-Source Voltage (V) Fig 2. Typical Output Characteristics 3.5 I D = 80A T J = 75 C 3.0 T J = 25 C V DS = 50V 20µs PULSE WIDTH 2.0 4.0 6.0 8.0.0 2.0 4.0 6.0 V GS, Gate-to-Source Voltage (V) R DS(on), Drain-to-Source On Resistance (Normalized) 2.5 2.0.5.0 0.5 V GS = V 0.0-60 -40-20 0 20 40 60 80 20 40 60 80 T J, Junction Temperature ( C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance Vs. Temperature www.irf.com 3
I D, Drain-to-Source Current (A) C, Capacitance(pF) V GS, Gate-to-Source Voltage (V) 00 0 V GS = 0V, f = MHZ C iss = C gs C gd, C ds SHORTED C rss = C gd C oss = C ds C gd C iss 2 8 I D = 80A V DS = 80V V DS = 50V V DS = 20V 6 C oss 4 C rss 2 V DS, Drain-to-Source Voltage (V) 0 0 20 40 60 80 Q G Total Gate Charge (nc) Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage 0 OPERATION IN THIS AREA LIMITED BY R DS (on) I SD, Reverse Drain Current (A) T J = 75 C T = 25 J C V GS = 0 V 0. 0.0 0.5.0.5 2.0 V SD,Source-to-Drain Voltage (V) 0. Tc = 25 C Tj = 75 C Single Pulse µsec msec msec V DS, Drain-to-Source Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area 4 www.irf.com
80 LIMITED BY PACKAGE V DS R D V GS D.U.T. 60 R G - V DD I D, Drain Current (A) 40 20 Fig a. Switching Time Test Circuit V DS 90% V Pulse Width µs Duty Factor 0. % 0 25 50 75 25 50 75 T, Case Temperature ( C C) Fig 9. Maximum Drain Current Vs. Case Temperature % V GS t d(on) t r t d(off) t f Fig b. Switching Time Waveforms Thermal Response (Z thjc ) 0. D = 0.50 0.20 0. 0.05 t 2 SINGLE PULSE 0.02 Notes: 0.0 (THERMAL RESPONSE). Duty factor D = t / t 2 2. Peak T J = P DM x Z thjc T C 0.0 0.0000 0.000 0.00 0.0 0. t, Rectangular Pulse Duration (sec) P DM t Fig. Maximum Effective Transient Thermal Impedance, Junction-to-Case www.irf.com 5
5V 600 I D V DS L DRIVER 500 TOP BOTTOM 8A 32A 45A R G D.U.T I AS - V DD A 20V tp 0.0Ω Fig 2a. Unclamped Inductive Test Circuit V (BR)DSS tp E AS, Single Pulse Avalanche Energy (mj) 400 300 200 0 25 50 75 25 50 75 Starting Tj, Junction Temperature ( C) I AS Fig 2c. Maximum Avalanche Energy Vs. Drain Current Fig 2b. Unclamped Inductive Waveforms Current Regulator Same Type as D.U.T. V Q GS Q G Q GD 2V.2µF 50KΩ.3µF D.U.T. V - DS V G V GS 3mA Charge Fig 3a. Basic Gate Charge Waveform I G I D Current Sampling Resistors Fig 3b. Gate Charge Test Circuit 6 www.irf.com
Peak Diode Recovery dv/dt Test Circuit D.U.T ƒ - Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer - - R G dv/dt controlled by R G Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test - V DD Driver Gate Drive Period P.W. D = P.W. Period V GS =V * D.U.T. I SD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt V DD Re-Applied Voltage Inductor Curent Body Diode Forward Drop Ripple 5% I SD * V GS = 5V for Logic Level Devices Fig 4. For N-Channel HEXFET Power MOSFETs www.irf.com 7
TO-220AB Package Outline Dimensions are shown in millimeters (inches) 2.87 (.3) 2.62 (.3).54 (.45).29 (.405) 3.78 (.49) 3.54 (.39) - A - 4.69 (.85) 4.20 (.65) - B -.32 (.052).22 (.048) 5.24 (.600) 4.84 (.584) 4.09 (.555) 3.47 (.530) 2 3 4 6.47 (.255) 6. (.240).5 (.045) MIN 4.06 (.60) 3.55 (.40) LEAD ASSIGNMENTS LEAD ASSIGNMENTS HEXFET IGBTs, CoPACK - GATE - GATE 2 - DRAIN - GATE 2- DRAIN 3 - SOURCE 2- COLLECTOR 3- SOURCE 4 - DRAIN 3- EMITTER 4- DRAIN 4- COLLECTOR.40 (.055) 3X.5 (.045) 2.54 (.) 2X 3X 0.93 (.037) 0.69 (.027) 0.36 (.04) M B A M 0.55 (.022) 3X 0.46 (.08) 2.92 (.5) 2.64 (.4) NOTES: DIMENSIONING & TOLERANCING PER ANSI Y4.5M, 982. 3 OUTLINE CONFORMS TO JEDEC OUTLINE TO-220AB. 2 CONTROLLING DIMENSION : INCH 4 HEATSINK & LEAD MEASUREMENTS DO NOT INCLUDE BURRS. TO-220AB Part Marking Information EXAMPLE: THIS IS AN IRF LOT CODE 789 ASSEMBLED ON WW 9, 997 IN THE ASSEMBLY LINE "C" Note: "P" in assembly line position indicates "Lead-Free" INTERNATIONAL RECTIFIER LOGO ASSEMBLY LOT CODE PART NUMBER DATE CODE YEAR 7 = 997 WEEK 9 LINE C Notes: Repetitive rating; pulse width limited by max. junction temperature. Starting T J = 25 C, L = 0.3mH, R G = 25Ω, I AS = 45A. ƒ I SD 45A, di/dt A/µs, V DD V (BR)DSS, T J 75 C. TO-220 package is not recommended for Surface Mount Application. Pulse width 300µs; duty cycle 2%. C oss eff. is a fixed capacitance that gives the same charging time as C oss while V DS is rising from 0 to 80% V DSS. Calculated continuous current based on maximum allowable junction temperature. Package limitation current is 75A. Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (3) 252-75 TAC Fax: (3) 252-7903 Visit us at www.irf.com for sales contact information.07/04 8 www.irf.com
Note: For the most current drawings please refer to the IR website at: http://www.irf.com/package/