Device Engineering Incorporated 35 East Alamo Drive Chandler, AZ 5225 Phone: (40) 303-022 Fax: (40) 303-024 E-mail: admin@deiaz.com DEI2 CH PROGRAMMABLE DISCRETE INTERFACE IC FEATURES Eight discrete inputs o Individually configurable as either GND/OPEN or 2/OPEN (or 2/GND) format input. o Input threshold and hysteresis per AirBus ABD000H specification. GND/OPEN mode: 4.5/0.5 threshold, 3 hysteresis 2/OPEN mode: 6/2 threshold, 3 hysteresis o ma input current to prevent dry relay contacts. o Internal isolation diode for GND/OPEN configuration o Inputs protected from Lightning Induced Transients per DO60E, Section 22, Cat A3 and B3, plus Waveform 5A. Serial I/O interface to read data register and write configuration register o Direct interface to Serial Peripheral Interface (SPI) port. o TTL/CMOS compatible inputs and Tristate output o 0MHz Max Data Rate o Serial input to expand Shift Register Logic Supply oltage (CC): 3.3 +/-5% Analog Supply oltage (DD): 5 +/-0% 6L SOIC EP package PIN ASSIGNMENTS DIN DIN2 DIN3 DIN4 DIN5 DIN6 DIN7 DIN DEI2 6 DD GND CC /CS Figure DEI2 Pin Assignment (6 Lead SOIC) 2009 Device Engineering Inc. of 3 DS-MW-02-0 Rev. A 0/0/2009
FUNCTIONAL DESCRIPTION DEI2 is an eight-channel discrete-to digital interface IC implemented in an H DIMOS technology. It senses eight discrete signals of the type commonly found in avionic systems and converts them to serial logic data. Each input can be individually configured as either GND/OPEN or 2/OPEN format input via a serial data input. The discrete data is read from the device via an eight-bit serial shift register with 3-state output. This serial interface is compatible with the industry standard Serial Peripheral Interface (SPI) bus. The discrete inputs are implemented with High oltage technology to provide immunity to lightning induced transients (DO60E Level 3) without the need for additional protection components. Table Pin Descriptions PINS NAME DESCRIPTION - DIN[:] Discrete Inputs. Eight discrete signals which can be individually configured as either GND/OPEN or 2/OPEN format inputs. 9 Logic Output. Serial Data Output. This pin is the output from MSB (Bit ) of the selected shift register (Data/Configuration). It is clocked by the rising edge of. This is a 3-state output enabled by /CS. 0 Logic Input. Serial Shift Clock. A low-to-high transition on this input shifts data on the serial data input into Bit of the selected shift register. The selected shift register is shifted from Bit to Bit. Bit of the selected shift register is driven on DOUT. /CS Logic Input. Chip Select. A low level on this input enables the 3- state output and the selected shift register. A high level on this input forces DOUT to the high impedance state and disables the shift registers so transitions have no effect. When the Data Register is selected, a high-to-low transition causes the Discrete Input data to be loaded into the Data Register. When the Configuration Register is selected, a low-tohigh transition causes the Serial Configuration Register data to be loaded into the parallel configuration outputs. 2 Logic Input. Serial Data Input. Data on this input is shifted into the LSB (Bit ) of the selected shift register on the rising edge of the when /CS input is low. 3 Logic Input. Selects between the Data Register and Configuration Register. H = DATA, L = CONF. 4 CC Logic Supply oltage. 3.3+/-5% 5 GND Logic/Signal Ground 6 DD Analog Supply oltage. +5+/-0% ORDERING INFORMATION Table 2 Ordering Information Part Number Marking Package Burn In Temperature DEI2-SES DEI2-SES 6 EP SOIC No -55 / +5 ºC DEI2-SMS DEI2-SMS 6 EP SOIC No -55 / +25 ºC DEI reserves the right to make changes to any products or specifications herein. DEI makes no warranty, representation, or guarantee regarding suitability of its products for any particular purpose. 2009 Device Engineering Inc. 2 of 3 DS-MW-02-0 Rev. A 0/0/2009
/ CS Control Logic MU ENB SFT/LD SCK CONFIGURATION REG bit Shift Register w/ latched parallel output PDO[:] (D0) DIN [ : ] DD CC CFG_[:] DISCRETE AFE Channels to DIN[:] DOUT[:] GND SFT/LD SCK PDI[:] DATA REG bit Shift Register w/ Parallel Input (D0) Figure 2 FUNCTION DIAGRAM dd 00K 2K DIN N 0K dpd 7 dn dpda 200 0K REFERENCE ECT threshold dd cc + - Comparator DOUTN qna 0v CFG_ N Figure 3 DISCRETE AFE FUNCTION DIAGRAM 2009 Device Engineering Inc. 3 of 3 DS-MW-02-0 Rev. A 0/0/2009
Table 3 Truth Table Serial Interface Operation /CS DIN[:] Description H HI Z Not Selected H L alid DIN[] DR[:] DIN[:] H L DR[] DR[] DR[n+] DR[n], DR[] L L CR[] CR[] CR[n+] CR[n], CR[] L L HI Z CL[:] CR[:] Legend: DR = Data Register CR = Configuration Register CL = Configuration Latch = Don t Care DIN[:] Discrete AFE The Discrete Input Analog Front End circuit function is represented in Figure 3. Each DINn signal is conditioned by the resistor / diode network and presented to a comparator with hysteresis. When the input is configured for GND/OPEN operation, the pull-up resistor and diode is enabled and comparator threshold voltage is selected. When configured for 2/OPEN operation, the pull-down resistor is enabled and the comparator is appropriately configured. Some notable features are: The input current is ~ ma. This current will prevent a dry relay contact. The input threshold voltage and hysteresis: o 2/OPEN Low-to-high threshold voltage: 2 > th > 0.5. High-to-low threshold voltage: 6 < th < 7.5. o Hysteresis: hys > 3. GND/OPEN Low-to-high threshold voltage: 0.5 > th > 9. High-to-low threshold voltage: 4.5 < th < 6. Hysteresis: hys > 3. Input noise immunity is maximized with a combination of voltage hysteresis and use of a slow input voltage comparator The inputs can withstand continuous input voltages of 49 minimum. The isolation diode breakdown voltage is greater than 42. The 0K Ohm input resistor is designed to limit diode breakdown current to safe levels during transient events. 2009 Device Engineering Inc. 4 of 3 DS-MW-02-0 Rev. A 0/0/2009
Data Register The -bit Data Register is a parallel-input, serial-output register that samples the input channels and reads-out the data to the Serial Data Output. The register is read via the output as described in Figure 4 and Figure 5. A low DIN input level results in a Logic 0, and a high input level results in a Logic. Configuration Register The -bit Configuration Register is a serial-input, parallel-output with data latch register that individually configures each AFE input as either GND/OPEN or 2/OPEN format. The register is programmed via the serial data input as described in Figure 6 and Figure 7. Logic 0 sets the respective input to 2/OPEN mode (pull-down); Logic sets the respective input to GND/OPEN mode (pull-up). The register is reset to 0 s when the CC Logic Supply voltage transitions from low to high. Serial Interface The DEI2 incorporates a serial IO interface for programming the Discrete Input configuration and for reading the Discrete Input status. Refer to Figure 2. The interface is SPI compatible and consists of /CS,,,, and signals. Waveform Figures 4 7 depict the Data Read sequence and Configuration Write sequence for both -Bit cycles and also 6 bit daisy chain applications. Power Up Initialization The DEI2 incorporates an on-chip power-up reset circuit and power sequencing provisions to force the DIN inputs to a high impedance state at power up; the AFE pull-up and pull-down circuits are disabled. The reset circuit monitors the CC logic supply and forces the AFE to the high impedance state while CC is stabilizing. It will remain in this state until the Configuration Register is programmed by the first Write Configuration Register cycle, when the pull-up or pull-down state is determined. /CS DIN[:] ALID DIN DIN7 DIN6 DIN5 DIN4 DIN3 DIN2 DIN DIN inputs latched into DATA S-Reg Figure 4 Read Data Register 2009 Device Engineering Inc. 5 of 3 DS-MW-02-0 Rev. A 0/0/2009
/CS DIN[:] ALID SI SI7 SI6 SI5 SI4 SI3 SI2 SI DIN DIN7 DIN6 DIN5 DIN4 DIN3 DIN2 DIN SI Si7 SI6 SI5 SI4 SI3 SI2 SI DIN inputs latched into DATA S-Reg data shifted to after bit delay Figure 5 Read Data Register, 6 Bit Daisy Chain /CS DIN[:] 7 6 5 4 3 2 7 6 5 4 3 2 PDO[:] Internal Config Latch Present Configuration n = New Configuration Data Bits n = Present Configuration Bits New Configuration Figure 6 Write Configuration Register /CS DIN[:] 7 6 5 4 3 2 7 6 5 4 3 2 7 6 5 4 3 2 7 6 5 4 3 2 PDO[:] Internal Config Latch n = Daisy Chain Data Bits n = New Configuration Data Bits n = Present Configuration Bits Present Configuration New Configuration Figure 7 Write Configuration Register, 6 bit Daisy Chain 2009 Device Engineering Inc. 6 of 3 DS-MW-02-0 Rev. A 0/0/2009
LIGHTNING PROTECTION DINn inputs are designed to survive lightning induced transients as defined by RTCA DO60E, Section 22, Cat A3 and B3, Waveforms 3, 4, and 5A. See waveforms below. 50% /I 25% to 75% of Largest Peak Peak T = 6.4uS T2 = 70uS 0 t 50% F = MHZ and 0MHZ 0 T T2 t Figure oltage / Current Waveform 3 Figure 9 oltage Waveform 4 /I Waveform Source Impedance characteristics: Waveform 3 oc/isc = 600 / 24A => 25 Ohms Waveform 4 oc/isc = 300 / 60 A => 5 Ohms Waveform 5A oc / Isc = 300 / 300A => Ohm Peak T=40uS T2=20uS 50% 0 T T2 t Figure 0 Current/oltage Waveform 5A 2009 Device Engineering Inc. 7 of 3 DS-MW-02-0 Rev. A 0/0/2009
ELECTRICAL DESCRIPTION Table 4 Absolute Maximum Ratings PARAMETER MIN MA UNITS CC Supply oltage -0.3 +5.0 DD Supply oltage -0.3 Operating Temperature Plastic Package -55 +25 C Storage Temperature Plastic Package -55 +50 C Input oltage DIN[:] Continuous DO60E, Waveform 3, Level 3 DO60E, Waveform 4 and 5, Level 3 DO60E, Abnormal Surge oltage, 00ms -0-600 -300 +49 +600 +300 0 CC +.5 CC + 0.5 Logic Inputs DOUT -.5-0.5 Power Dissipation @ 25 C, steady state 6L SOIC 0.5 W Junction Temperature: Tjmax, Plastic Packages 45 C ESD per JEDEC A4-A Human Body Model Logic and Supply pins DIN pins 2000 000 Peak Body Temperature (0 sec duration) 235 C Notes:. Stresses above absolute maximum ratings may cause permanent damage to the device. 2. oltages referenced to Ground Table 5 Recommended Operating Conditions PARAMETER SYMBOL CONDITIONS Supply oltage CC DD 3.3±5% 5±0% Logic Inputs and Outputs 0 to CC Discrete Inputs DIN[:] 0 to 49 Operating Temperature Ta Plastic -55 to +25 ºC 2009 Device Engineering Inc. of 3 DS-MW-02-0 Rev. A 0/0/2009
Table 6 DC Electrical Characteristics SYMBOL PARAMETER CONDITIONS () LIMITS UNIT Logic Inputs/Outputs MIN NOM MA IH HI level input voltage CC = 3.3 2.0 IL LO level input voltage 0. Ihst Input hysteresis voltage, (3) 50 m input OH HI level output voltage IOUT = -20uA CC 0. IOUT = -4mA, CC = 3 2.4 OL LO level output voltage IOUT = 20uA 0. IOUT = 4mA, CC = 3 0.4 I IN Input leakage IN = CC or GND -0 0 ua I OZ 3-state leakage current Output in Hi Impedance state. OUT = IHmin, ILmax -0 0 ua Discrete Inputs, Configured as Ground/Open (internal pull-up) IH HI level input voltage 0.5 49 T LH Input threshold, LO to HI 9.0 0.5 R IH HI level Din-to-GND resistance Resistor from Din to GND to guarantee HI input condition. 50K Ohms I IH HI level input current IN = 2, DD = 5 ua IN = 49, DD = 5 0. ma IL LO level input voltage -3.0 4.5 T HL Input threshold, HI to LO 4.5 6.0 R IL LO level Din-to-GND resistance Resistor from Din to GND to guarantee LO input condition. 500 Ohms I IL LO level input current IN = 0, DD = 5 -. ma Ihst Input hysteresis voltage 3 Discrete Inputs, Configured as 2/Open (internal pull-down) IH HI level input voltage 2.0 49 T LH Input threshold, LO to HI 0.5 2 I IH HI level input current IN = 2, DD = 5 0..3. ma IL LO level input voltage -3 6.0 T HL Input threshold, HI to LO 6.0 7.5 I IL LO level input current IN =, DD = 5 0 50 ua Ihst Input hysteresis voltage 3 Power Supply ICC Max quiescent logic supply IN(logic) = CC or GND IDD current Max quiescent analog supply current IN[:]= open. 3 ma IN(logic) = CC or GND IN[:]= Open 5 24 IN[:]= GND, All ma configured as Ground/Open 22 33 Notes:. Ta = -55 to +25 ºC. DD = +5±0%, CC = 3.3+/-5% unless otherwise noted. 2. Current flowing into device is +. Current flowing out of device is -. oltages are referenced to Ground. 3. Guaranteed by design. Not production tested. 2009 Device Engineering Inc. 9 of 3 DS-MW-02-0 Rev. A 0/0/2009
Table 7 AC Electrical Characteristics (4) SYMBOL PARAMETER CONDITIONS (6,7) LIMITS UNIT MIN MA f MA frequency. (50% duty cycle) (5) 0. 0 MHz t W pulse width. (5) 50 ns t su Setup time, low to /CS. 30 ns t h Hold time, /CS to. 25 ns t su2 Setup time, DIN valid to /CS. 500 ns t h2 Hold time, /CS to DIN not valid. 5 ns t su3 Setup time, N valid to. 25 ns t h3 Hold time, to N not valid. 25 ns t su4 Setup time, valid to /CS. 30 ns t h4 Hold time, valid to /CS. 25 ns t p Propagation delay, /CS to DOUT valid.() 05 ns t p2 Propagation delay, to DOUT valid.() 90 ns t p3 Propagation delay, /CS to DOUT HI-Z. () (2) (3) 0 ns t p4 Delay time between /CS active. (5) 20 ns C in Maximum logic input pin Capacitance. (5) 0 pf C out Maximum DOUT pin capacitance, output in 5 pf HI-Z state. (5) Notes:. DOUT loaded with 50pF to GND. 2. DOUT loaded with K Ohms to GND for Hi output, K Ohms to CC for Low output. 3. Timing measured at 25%CC for 0 to Hi-Z, 75%CC for to Hi-Z. 4. Sample tested on lot basis. 5. Not tested 6. Ta = -55 to +25ºC. CC = 3, DD = 5, IL = 0, IH = CC unless otherwise noted. 7. Measurements made at 50%CC. tsu4 t h4 /CS tsu th tw tp4 tsu2 th2 /fmax DIN[:] valid tsu3 th3 valid tp tp2 tp3 D/C0 D/C Figure Switching Waveforms 2009 Device Engineering Inc. 0 of 3 DS-MW-02-0 Rev. A 0/0/2009
APPLICATION INFORMATION Discrete Input Filtering The DEI2 Analog Front End provides a moderate level of noise immunity via a combination hysteresis and limited bandwidth. The Hysteresis is 3 minimum and the comparator bandwidth is approximately 0MHz. Many applications provide additional noise immunity by means of debounce/filtering in software or in digital circuitry (i.e.: FPGA). Common input debounce techniques are readily found with a web search of the term software debounce and range from simple detectors of two or more sequential stable readings to FIR filters emulating RC time constants. Input Current Characteristics The DIN Input Current vs. oltage characteristics for the 2/OPEN Mode and GND/OPEN Mode are shown in Figure 2 and Figure 3. 2.50 Discrete Input Characteristics (2/OPEN) 2.00 Input Current (ma).50.00 0.50 0.00-0.50 -.00-0.00 0.00 0.00 20.00 30.00 40.00 50.00 Discrete Input oltage () Figure 2 2/Open Mode Input I Characteristics (DD=5).0 Discrete Input Characteristics (GND/OPEN) 0.5 Input Current (ma) 0.0-0.5 -.0 -.5-2.0-2.5-0.0 0.0 0.0 20.0 30.0 40.0 50.0 Discrete Input oltage () Figure 3 GND/OPEN Mode Input I Characteristics (DD=5) 2009 Device Engineering Inc. of 3 DS-MW-02-0 Rev. A 0/0/2009
Package Power Dissipation The DEI2 power dissipation varies with channel configuration and operating conditions. Figure 4 shows the device package power dissipation for various conditions. This includes the contributions from Supply currents and Input currents. The four curves are as follows: CURE ID +2/OPEN-Nom Table Legend for Power Dissipation Curves SUPPLY OLTAGE, TEMPERATURE, IC ARIATION 3.3, 2 / 27ºC / typical IC parameters +2/OPEN-Wst 3.3, 6.5 / 25ºC / Worst case IC parameters GND/OPEN-Nom 3.3, 2 / 27ºC / typical IC parameters GND/OPEN-Wst 3.3, 6.5 / 25ºC / Worst case IC parameters Notes: The active channels are forced to Ground for GND/OPN type and forced to 2 for 2/OPN type. Figure 4 Power Dissipation for arious Conditions 2009 Device Engineering Inc. 2 of 3 DS-MW-02-0 Rev. A 0/0/2009
PACKAGE DESCRIPTION - 6L Narrow Body EP SOIC Moisture Sensitivity: Θja: Θjc: Lead Finish: Exposed Pad: Level 2 / 235 C per JEDEC J-STD-020A ( yr floor life) ~40 C/W (Mounted on 4 layer PCB with exposed pad soldered to PCB land with thermal vias to internal GND plane) ~0 C/W SnPb plated Electrically Isolated from IC terminals. The PCB design and layout is a significant factor in determining thermal resistance (Θja) of the IC package. Use maximum trace width on all power and signal connections at the IC. These traces serve as heat spreaders which improve heat flow from the IC leads. The exposed heat sink pad of the SOIC package should be soldered to a heat-spreader land pattern on the PCB. The IC exposed pad is electrically isolated, so the PCB land may be at any potential, typically GND, for the best heat sink. Maximize the PCB land size by extending it beyond the IC outline if possible. A grid of thermal IAs, which drop down and connect to the buried copper plane(s), should be placed under the heat-spreader land. A typical IA grid is 2mil holes on a 50mil pitch. The barrel is plated to about.0 ounce copper. Use as many IAs as space allows. IAs should be plugged to prevent voids being formed between the exposed pad and PCB heat-spreader land due to solder escaping by the capillary effect. This can be avoided by tenting the IAs with solder mask. Figure 5 6 Lead Narrow Body EP SOIC Outline 2009 Device Engineering Inc. 3 of 3 DS-MW-02-0 Rev. A 0/0/2009