DEI1054 Six Channel Discrete-to-Digital Interface Sensing 28 Volt/Open
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1 Device Engineering Incorporated 385 East Alamo Drive Chandler, AZ Phone: (480) Fax: (480) DEI1054 Six Channel Discrete-to-Digital Interface Sensing 28 Volt/Open Features Small footprint (16L SOIC NB) Senses six 28V/Open discrete logic signals Inputs are Lightning Protected to DO-160D Level 3 TTL/CMOS-Compatible Tri-state Outputs Package / Temperature Options: 16L 150mil SOIC, -55 C/+85 C 16L Ceramic 300mil SOP, -55 C/+125 C Functional Description The DEI1054 is a six channel discrete-to-digital interface BiCMOS device. It s six 28V/Open discrete signals of the type commonly found in avionics systems. The inverted outputs are TTL/CMOS compatible and are enabled via the CE and OE pins. The input pins of this small, 16-lead narrow body SOIC device are lightning protected to meet the requirements of DO160D waveforms 3, 4, and 5, level 3. See figures 5-7. With its reliability, low cost, operating range, and lightning protection, the DEI1054 meets a large variety of interface requirements for aerospace and industrial applications. Figure 1: Function Diagram Figure 2: Pinout Diagram 2015 Device Engineering Inc. Page 1 of 7 DS-MW Rev. D
2 Table 1: Absolute Maximum Ratings (Note 1) PARAMETER MIN MAX UNITS Supply Voltage V DD V Discrete Input Voltage (Pins 1-6) Continuous (Note 2): V Lightning Protection (Pins 1-6): DO160D, Waveform 3; Level 3 DO160D, Waveforms 4 and 5; Level V V Digital Input Voltage (CE and OE ) V SS V DD V Storage Temperature Junction Temperature TJMAX 145 Operating Free Air Temperature Peak Body Temp per J-STD-020-C Plastic Ceramic 16L SOIC NB G 16L CSOP Notes: 1. Absolute Maximum Ratings are those values beyond which the life of the device may be impaired. 2. The DEI1054 will withstand the transient surge DC voltage step function loci limits for category B equipment per MIL-STD-704A. 3. The DEI1054 contains circuitry to protect inputs against damage due to high voltage static discharge. It has been characterized per JEDEC A114-A Human Body Model tlass 1. Observe precautions for handling and storing Electrostatic Sensitive Devices. Table 2: DEI1054 Device Operating Characteristics PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Voltage V DD V Free Air Operating Temp. Plastic Ceramic T A V DD = V Logic Output Sink Current I OL V DD = V 5.0 ma Logic Output Source Current I OH V DD = V -5.0 ma o C Table 3: DEI1054 Logic Truth Table CE (Chip Enable) OE (Output Enable) IN 1-6 Input OUT 1-6 Output 0 0 Open Volts 0 1 X X High Z X 1 X High Z 2015 Device Engineering Inc. Page 2 of 7 DS-MW Rev. D
3 Table 4a: DEI1054 (Plastic) Electrical Characteristics (T A = -55 C TO +85 C, V DD = 4.5 TO 5.5 V, Unless otherwise noted) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Current Thermal Resistance IN 1-6 input voltage for Open IN 1-6 input current for Open IN 1-6 input voltage for 28V input IN 1-6 input current for 28V input IN 1-6 Input Resistance I DD JA JC V SO I SOmax V S28 I S28min R IN Power Supply and Thermal Data IN 1-6 = 0V OE, CE, V DD = 5.5 V Junction to Ambient (4L PCB) Junction tase Discrete Input Characteristics High Output. Maximum input current to Low Output. Minimum input current to Discrete input resistance. 0V < IN 1-6 < 16V 5 10 ma ~ 73 ~ 29 C/W V 80 ua V 187 ua K IN 1-6 Input current at 28V I IN28 V IN = 28V 502 A Logic Input Characteristics CE, OE input logic 1 level V IH 2.0 V CE, OE input logic 0 level V IL 0.8 V DC Output Characteristics Output logic 1 level (TTL) V OH I OH = -5 ma. 2.4 V Output logic 0 level (TTL) V OL I OL = 5 ma. 0.4 V Output logic 1 level (CMOS) V OH I OH = -100 A (Note 1) V DD 50mV V Output logic 0 level (CMOS) V OL I OL = 100 A (Note 1) V SS + 50mV V Off-state Output Current I OZ OE = V DD V DD = 5.5 V V OUT = 0 or V DD Switching Characteristics (Note 1) +/-10 A I/O propagation delay t HL, t LH Refer to Figure ns (with output low) to output HI-Z (with output HI-Z) to output low (with output high) to output HI -Z t LZ Refer to Figure ns t ZL Refer to Figure ns t HZ Refer to Figure ns (with output HI-Z) to output high t ZH Refer to Figure ns NOTES: 1. This parameter is guaranteed by design and not tested Device Engineering Inc. Page 3 of 7 DS-MW Rev. D
4 Table 4b: DEI1054 (Ceramic) Electrical Characteristics (T A = -55 C TO +125 C, V DD = 4.5 TO 5.5 V, Unless otherwise noted) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Current Thermal Resistance IN 1-6 input voltage for Open IN 1-6 input current for Open IN 1-6 input voltage for 28V input IN 1-6 input current for 28V input IN 1-6 Input Resistance I DD JA JC V SO I SOmax V S28 I S28min R IN Power Supply and Thermal Data IN 1-6 = 0V OE, CE, V DD = 5.5 V Junction to Ambient (4L PCB) Junction tase Discrete Input Characteristics High Output. Maximum input current to Low Output. Minimum input current to Discrete input resistance. 0V < IN 1-6 < 16V 5 10 ma TBD 23 C/W V 80 ua V 187 ua K IN 1-6 Input current at 28V I IN28 V IN = 28V 502 A Logic Input Characteristics CE, OE input logic 1 level V IH 2.0 V CE, OE input logic 0 level V IL 0.8 V DC Output Characteristics Output logic 1 level (TTL) V OH I OH = -5 ma. 2.4 V Output logic 0 level (TTL) V OL I OL = 5 ma. 0.4 V Output logic 1 level (CMOS) V OH I OH = -100 A (Note 1) V DD 50mV V Output logic 0 level (CMOS) V OL I OL = 100 A (Note 1) V SS + 50mV V Off-state Output Current I OZ OE = V DD V DD = 5.5 V V OUT = 0 or V DD Switching Characteristics (Note 1) +/-10 A I/O propagation delay t HL, t LH Refer to Figure ns (with output low) to output HI-Z (with output HI-Z) to output low (with output high) to output HI -Z t LZ Refer to Figure ns t ZL Refer to Figure ns t HZ Refer to Figure ns (with output HI-Z) to output high t ZH Refer to Figure ns NOTES: 1. This parameter is guaranteed by design and not tested Device Engineering Inc. Page 4 of 7 DS-MW Rev. D
5 Figure 3: Enable to Output Propagation Delay Figure 4: Input to Output Propagation Delay Figure 5: DO160D Voltage Waveform #3 V OC = 600V, I SC = 24A, Frequency = 1.0MHZ ±20% Figure 6: DO160D Voltage Waveform #4 V OC = 300V, I SC = 60A Figure 7: DO160D Voltage Waveform # Device Engineering Inc. Page 5 of 7 DS-MW Rev. D
6 Ordering Information Table 5: Ordering Information DEI Part Number Marking Package Op. Temp. Range Processing DEI1054-G DEI1054 E4 16 lead SOIC NB G -55 / +85 C Standard DEI1054-SMS-G DEI1054-SMS (1) E4 16 lead SOIC NB G -55 / +125ºC Standard DEI1054-WMS DEI1054-WMS 16 lead ceramic SOP -55 / +125ºC Standard DEI1054-WMB DEI1054-WMB 16 lead ceramic SOP -55 / +125ºC Burn-In, C NOTES: 1. Alternate marking for up-screened part: the SMS is replaced with a blue dot DEI reserves the right to make changes to any products or specifications herein. DEI makes no warranty, representation, or guarantee regarding suitability of its products for any particular purpose. Package Descriptions PACKAGE TYPE Table 6: Package Characteristics 16 Lead SOIC Narrow Body, Green 16 Lead Ceramic SOP REFERENCE 16L SOIC NB G 16L CSOP THERMAL RESISTANCE: JA (4 layer PCB with Power Planes) ~73 C/W - JC ~29 C/W 23 C/W JEDEC MOISTURE SENSITIVITY LEVEL (MSL) LEAD FINISH MATERIAL / JEDEC Pb-free CODE MSL 1 / 260 C NiPdAu e4 Hermetic Pb-Free DESIGNATION RoHS Compliant Pb Free JEDEC REFERENCE MS-012-AC - Au e Device Engineering Inc. Page 6 of 7 DS-MW Rev. D
7 16L 150mil SOIC Figure 8: 16L SOIC Mechanical Outline 16L 300mil CSOP Figure 9: 16L CSOP Mechanical Outline 2015 Device Engineering Inc. Page 7 of 7 DS-MW Rev. D
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NOTE: This product has been replaced with UT28F256QLE or SMD device types 09 and 10.
NOTE: This product has been replaced with UT28F256QLE or SMD 5962-96891 device types 09 and 10. 1 Standard Products UT28F256 Radiation-Hardened 32K x 8 PROM Data Sheet December 2002 FEATURES Programmable,
ICS NETWORKING AND PCI CLOCK SOURCE. Description. Features. Block Diagram DATASHEET
DATASHEET Description The is a low cost frequency generator designed to support networking and PCI applications. Using analog/digital Phase Locked-Loop (PLL) techniques, the device uses a standard fundamental
IDT5V60014 LOW PHASE NOISE ZERO DELAY BUFFER. Description. Features. Block Diagram DATASHEET
DATASHEET IDT5V60014 Description The IDT5V60014 is a high speed, high output drive, low phase noise Zero Delay Buffer (ZDB) which integrates IDT s proprietary analog/digital Phase Locked Loop (PLL) techniques.
MK SPREAD SPECTRUM MULTIPLIER CLOCK. Description. Features. Block Diagram DATASHEET
DATASHEET MK1714-01 Description The MK1714-01 is a low cost, high performance clock synthesizer with selectable multipliers and percentages of spread spectrum designed to generate high frequency clocks
MK SPREAD SPECTRUM MULTIPLIER CLOCK. Description. Features. Block Diagram DATASHEET
DATASHEET MK1714-02 Description The MK1714-02 is a low cost, high performance clock synthesizer with selectable multipliers and percentages of spread designed to generate high frequency clocks with low
ICS LOW EMI CLOCK GENERATOR. Description. Features. Block Diagram DATASHEET
DATASHEET ICS180-51 Description The ICS180-51 generates a low EMI output clock from a clock or crystal input. The device uses IDT s proprietary mix of analog and digital Phase-Locked Loop (PLL) technology
ICS GLITCH-FREE CLOCK MULITPLEXER. Features. Description. Block Diagram DATASHEET
DATASHEET ICS580-01 Description The ICS580-01 is a clock multiplexer (mux) designed to switch between two clock sources with no glitches or short pulses. The operation of the mux is controlled by an input
Features VDD 2. 2 Clock Synthesis and Control Circuitry. Clock Buffer/ Crystal Oscillator GND
DATASHEET Description The is a low cost, low jitter, high performance clock synthesizer for networking applications. Using analog Phase-Locked Loop (PLL) techniques, the device accepts a.5 MHz or 5.00
8K x 8 Static RAM CY6264. Features. Functional Description
8K x 8 Static RAM Features 55, 70 ns access times CMOS for optimum speed/power Easy memory expansion with CE 1, CE 2, and OE features TTL-compatible inputs and outputs Automatic power-down when deselected
Ultrafast TTL Comparators AD9696/AD9698
a FEATURES 4.5 ns Propagation Delay 200 ps Maximum Propagation Delay Dispersion Single +5 V or 5 V Supply Operation Complementary Matched TTL Outputs APPLICATIONS High Speed Line Receivers Peak Detectors
ICS511 LOCO PLL CLOCK MULTIPLIER. Description. Features. Block Diagram DATASHEET
DATASHEET ICS511 Description The ICS511 LOCO TM is the most cost effective way to generate a high quality, high frequency clock output from a lower frequency crystal or clock input. The name LOCO stands
MK74CB218 DUAL 1 TO 8 BUFFALO CLOCK DRIVER. Description. Features. Block Diagram DATASHEET. Family of IDT Parts
DTSHEET MK74CB218 Description The MK74CB218 Buffalo is a monolithic CMOS high speed clock driver. It consists of two identical single input to eight low-skew output, non-inverting clock drivers. This eliminates
LMS485 5V Low Power RS-485 / RS-422 Differential Bus Transceiver
5V Low Power RS-485 / RS-422 Differential Bus Transceiver General Description The LMS485 is a low power differential bus/line transceiver designed for high speed bidirectional data communication on multipoint
MK3722 VCXO PLUS AUDIO CLOCK FOR STB. Description. Features. Block Diagram DATASHEET
DATASHEET MK3722 Description The MK3722 is a low cost, low jitter, high performance VCXO and PLL clock synthesizer designed to replace expensive discrete VCXOs and multipliers. The patented on-chip Voltage
Features. Applications
PCIe Fanout Buffer 267MHz, 8 HCSL Outputs with 2 Input MUX PrecisionEdge General Description The is a high-speed, fully differential 1:8 clock fanout buffer optimized to provide eight identical output
1M Words By 8 bit. Rev. No. History Issue Date Remark 1.0 Initial issue Aug.17,2016
Revision History Rev. No. History Issue Date Remark 1.0 Initial issue Aug.17,2016 i Rev. 1.0 PRODUCT DESCRIPTION... 1 FEATURES... 1 PRODUCT FAMILY... 1 PIN CONFIGURATIONS... 2 FUNCTIONAL BLOCK DIAGRAM...
NB3N502/D. 14 MHz to 190 MHz PLL Clock Multiplier
4 MHz to 90 MHz PLL Clock Multiplier Description The NB3N502 is a clock multiplier device that generates a low jitter, TTL/CMOS level output clock which is a precise multiple of the external input reference
SERIALLY PROGRAMMABLE CLOCK SOURCE. Features
DATASHEET ICS307-02 Description The ICS307-02 is a versatile serially programmable clock source which takes up very little board space. It can generate any frequency from 6 to 200 MHz and have a second
MAX15070A/MAX15070B 7A Sink, 3A Source, 12ns, SOT23 MOSFET Drivers
General Description The /MAX15070B are high-speed MOSFET drivers capable of sinking 7A and sourcing 3A peak currents. The ICs, which are an enhancement over MAX5048 devices, have inverting and noninverting
TC4427 TC A DUAL HIGH-SPEED POWER MOSFET DRIVERS 1.5A DUAL HIGH-SPEED POWER MOSFET DRIVERS TC4426 TC4426 GENERAL DESCRIPTION FEATURES
FEATURES High Peak Output Current....A Wide Operating Range....V to V High Capacitive Load Drive Capability... pf in nsec Short Delay Time... < nsec Typ. Consistent Delay Times With Changes in Supply Voltage
14-Bit Registered Buffer PC2700-/PC3200-Compliant
14-Bit Registered Buffer PC2700-/PC3200-Compliant Features Differential Clock Inputs up to 280 MHz Supports LVTTL switching levels on the RESET pin Output drivers have controlled edge rates, so no external
ICS663 PLL BUILDING BLOCK. Description. Features. Block Diagram DATASHEET
DATASHEET ICS663 Description The ICS663 is a low cost Phase-Locked Loop (PLL) designed for clock synthesis and synchronization. Included on the chip are the phase detector, charge pump, Voltage Controlled
128K x 8 Static RAM CY7C1019B CY7C10191B. Features. Functional Description. Logic Block Diagram. Pin Configurations
128K x 8 Static RAM Features High speed t AA = 10, 12, 15 ns CMOS for optimum speed/power Center power/ground pinout Automatic power-down when deselected Easy memory expansion with and OE options Functionally
UT54LVDS032 Quad Receiver Data Sheet September 2015
Standard Products UT54LVDS032 Quad Receiver Data Sheet September 2015 The most important thing we build is trust FEATURES INTRODUCTION >155.5 Mbps (77.7 MHz) switching rates +340mV nominal differential
AD9300 SPECIFICATIONS ELECTRICAL CHARACTERISTICS ( V S = 12 V 5%; C L = 10 pf; R L = 2 k, unless otherwise noted) COMMERCIAL 0 C to +70 C Test AD9300K
a FEATURES 34 MHz Full Power Bandwidth 0.1 db Gain Flatness to 8 MHz 72 db Crosstalk Rejection @ 10 MHz 0.03 /0.01% Differential Phase/Gain Cascadable for Switch Matrices MIL-STD-883 Compliant Versions
SP1481E/SP1485E. Enhanced Low Power Half-Duplex RS-485 Transceivers
SP1481E/SP1485E Enhanced Low Power Half-Duplex RS-485 Transceivers +5V Only Low Power BiCMOS Driver/Receiver Enable for Multi-Drop configurations Low Power Shutdown Mode (SP1481E) Enhanced ESD Specifications:
RoHS compliant, Pb-free Industrial temperature range: 40 to +85 C Footprint-compatible with CDCLVC , 2.5, or 3.3 V operation 16-TSSOP
1:8 LOW JITTER CMOS CLOCK BUFFER (
I/O 1 I/O 2 I/O 3 A 10 6
Features High speed 12 ns Fast t DOE CMOS for optimum speed/power Low active power 495 mw (Max, L version) Low standby power 0.275 mw (Max, L version) 2V data retention ( L version only) Easy memory expansion
MM74HCU04 Hex Inverter
MM74HCU04 Hex Inverter General Description The MM74HCU04 inverters utilize advanced silicon-gate CMOS technology to achieve operating speeds similar to LS-TTL gates with the low power consumption of standard