FETURE a) dopting new 5th generation (CSTBT) chip, which performance is improved by 1µm fine rule process. r example, typical ce(sat)=1.9 @Tj=125 b) I adopt the over-temperature conservation by Tj detection of CSTBT chip, and error output is possible from all each conservation upper and lower arm of IPM. 3φ 25, 10 Current-sense type inverter Monolithic gate drive & protection logic Detection, protection & status indication circuits for, shortcircuit, over-temperature & under-voltage (P- available from upper arm devices) coustic noise-less 3.7kW class inverter application PPLICTION General purpose inverter, servo drives and other motor controls PCKGE LINES Dimensions in mm 1 7 106 19.75 3.25 16 3-2 16 3-2 16 15.25 3-2 6-2 2-φ5.5 MOUNTING HOLES 35 6-φ6 N P 10.75 B U W 32.75 23 23 23 Terminal code 1. UPC 2. UFO 3. UP 4. UP1 5. PC 6. FO 7. P 8. P1 9. WPC 10. WFO 11. WP 12. WP1 13. NC 14. N1 15. NC 16. UN 17. N 18. WN 19. 19-0.5 31 6 6 13 32 55
INTERNL FUNCTIONS BLOCK DIGRM NC NC WN N1 N UN WP WP1 WPC WFO P P1 PC FO UP UP1 UPC UFO NC N W U P MXIMUM RTINGS (Tj = 25, unless otherwise noted) INERTER PRT CES ±IC ±ICP PC Tj Collector-Emitter oltage Collector Current Collector Current (Peak) Collector Dissipation Junction Temperature D = 15, CIN = 15 TC = 25 TC = 25 TC = 25 (Note-2) Ratings 10 25 50 116 ~ +150 W CONTROL PRT Ratings D Supply oltage pplied between : UP1-UPC P1-PC, WP1-WPC, N1-NC CIN FO O put oltage Fault Output Supply oltage Fault Output Current pplied between : UP-UPC, P-PC WP-WPC, UN N WN-NC pplied between : UFO-UPC, FO-PC, WFO-WPC FO-NC nk current at UFO, FO, WFO, FO terminals m
TL SYSTEM Ratings CC(PR) Supply oltage Protected by D = 13.5 ~ 16.5, verter Part, SC Tj = +125 Start 800 CC(surge) TC Tstg iso Supply oltage (Surge) Module Case Operating Temperature Storage Temperature Isolation oltage pplied between : P-N, Surge value (Note-2) 60Hz, nusoidal, Charged part to Base, C 1 min. 1000 ~ +100 40 ~ +125 2500 rms THERML RESISTNCES Min. Typ. Max. Rth(j-c)Q verter (per 1 element) (Note-1) 0.83 Rth(j-c)F Junction to case Thermal verter (per 1 element) (Note-1) 1.36 Rth(j-c)Q Resistances verter (per 1 element) (Note-2) 1.08 Rth(j-c)F verter (per 1 element) (Note-2) 1.77 /W Rth(c-f) Contact Thermal Resistance Case to fin, (per 1 module) Thermal grease applied 0.038 (Note-1) TC measurement point is just under the chips (Bottom view). If you use this value, Rth(f-a) should be measured just under the chips. (Note-2) TC measurement point is as shown below (Top view). Table1 : TC measurement point of just under the chips. ( : mm) arm UP P WP UN N WN axis X Y 29.0 7.1 29.3 1.5 65.0 7.1 65.5 85.6 7.1 85.9 37.8 5.1 37.5 4.5 55.2 5.1 55.7 4.5 75.8 5.1 75.3 4.5 Bottom view U W Top view B N P TC (Base plate) ELECTRICL CHRCTERISTICS (Tj = 25, unless otherwise noted) INERTER PRT CE(sat) EC ton trr tc(on) toff tc(off) ICES Collector-Emitter Saturation oltage rward oltage Switching Time Collector-Emitter Cutoff Current D = 15, IC = 25 Tj = 25 CIN = 0, Pulsed (Fig. 1) Tj = 125 IC = 25, D = 15, CIN = 15 (Fig. 2) D = 15, CIN = 0 15 CC = 600, IC = 25 Tj = 125 ductive Load (Fig. 3,4) CE = CES, CIN = 15 (Fig. 5) Tj = 25 Tj = 125 Min. Typ. Max. 0.5 1.8 1.9 1.0 0.5 0.4 0.7 2.3 2.4 3.5 0.8 1.0 3.0 1.2 1 10 µs m
CONTROL PRT ID th(on) th(off) SC toff(sc) r U Ur O(H) O(L) Circuit Current put ON Threshold oltage put OFF Threshold oltage Short Circuit Trip Level Short Circuit Current Delay Time Over Temperature Protection Supply Circuit Under-oltage Protection Fault Output Current N1-NC D = 15, CIN = 15 XP1-XPC pplied between : UP-UPC, P-PC, WP-WPC UN N WN-NC Tj 125, D = 15 (Fig. 3,6) D = 15 (Fig. 3,6) Trip level Detect Tj of chip Reset level Trip level Tj 125 Reset level D = 15, CIN = 15 (Note-3) Minimum Fault Output Pulse tfo D = 15 (Note-3) 1.0 1.8 ms Width (Note-3) Fault output is given only when the internal SC, & U protections schemes of either upper or lower arm device operate to protect it. Min. 1.2 1.7 50 135 11.5 Typ. 15 5 1.5 0.2 145 125 1 1 10 Max. 25 10 1.8 2.3 155 1 0.01 15 m µs m MECHNICL RTINGS ND CHRCTERISTICS Mounting torque Mounting torque Weight Main terminal Mounting part screw : M5 screw : M5 Min. Typ. Max. 3.0 3.0 380 3.5 3.5 N m N m g RECOMMENDED CONDITIONS FOR USE CC D CIN(ON) CIN(OFF) fpwm Supply oltage Control Supply oltage put ON oltage put OFF oltage PWM put Frequency rm Shoot-through Blocking Time pplied across P-N terminals pplied between : UP1-UPC, P1-PC WP1-WPC, N1-NC (Note-4) pplied between : UP-UPC, P-PC, WP-WPC UN N WN-NC Using pplication Circuit of Fig. 8 r IPM s each input signals (Fig. 7) Recommended value 800 15.0 ± 1.5 0.8 9.0 khz µs (Note-4) With ripple satisfying the following conditions dv/dt swing ±5/µs, ariation 2 peak to peak
PRECUTIONS FOR TESTING 1. Before appling any control supply voltage (D), the input terminals should be pulled up by resistores, etc. to their corresponding supply voltage and each input signal should be kept off state. fter this, the specified ON and OFF level setting for each input signal should be done. 2. When performing SC tests, the turn-off surge voltage spike at the corresponding protection operation should not be allowed to rise above CES rating of the device. (These test should not be done by using a curve tracer or its equivalent.) P, (U,,W) P, (U,,W) CIN (0) IN CIN (15) IN U,,W, (N) D (all) Fig. 1 CE(sat) Test U,,W, (N) D (all) Fig. 2 EC Test a) Lower rm Switching P CIN (15) CIN (Upper rm) (Lower rm) U,,W CS cc 90% trr Irr 90% CE b) Upper rm Switching CIN CIN (15) (Upper rm) (Lower rm) D (all) D (all) N P U,,W Fig. 3 Switching time and SC test circuit N CS cc 10% 10% 10% 10% tc (on) tc (off) CIN td (on) tr td (off) tf (ton= td (on) + tr) (toff= td (off) + tf) Fig. 4 Switching time test waveform CIN Short Circuit Current P, (U,,W) Constant Current CIN (15) IN Pulse CE SC D (all) U,,W, (N) Fig. 5 ICES Test toff(sc) Fig. 6 SC test waveform IPM input signal CIN (Upper rm) 0 1.5 2 1.5 t IPM input signal CIN (Lower rm) 0 2 1.5 2 t 1.5: put on threshold voltage th(on) typical value, 2: put off threshold voltage th(off) typical value Fig. 7 Dead time measurement point example
P D D kω 10µ UP1 UP UPC P1 P PC cc cc U + M D kω 10µ WP1 WP WPC UN cc cc W N kω 10µ N cc D kω 10µ N1 WN cc NC NC NC 5 1kΩ : terface which is the same as the U-phase Fig. 8 pplication Example Circuit NES FOR STBLE ND SFE OPERTION ; Design the PCB pattern to minimize wiring length between opto-coupler and IPM s input terminal, and also to minimize the stray capacity between the input and output wirings of opto-coupler. Connect low impedance capacitor between the cc and GND terminal of each fast switching opto-coupler. Fast switching opto-couplers: tplh, tphl 0.8µs, Use High CMR type. Slow switching opto-coupler: CTR > 100% Use 4 isolated control power supplies (D). lso, care should be taken to minimize the instantaneous voltage charge of the power supply. Make inductance of DC bus line as small as possible, and minimize surge voltage using snubber capacitor between P and N terminal. Use line noise filter capacitor (ex. 4.7nF) between each input C line and ground to reject common-mode noise from C line and improve noise immunity of the system.