A Fast ad Precise Blid I/Q Mismatch Compesatio for Image Rejectio i Direct-Coversio Receiver Sua Kim, Dae-Youg Yoo, Hyug Chul Park, Giwa Yoo, ad Sag-Gug Lee I this paper, we propose a ew digital blid iphase/quadrature-phase (I/Q) mismatch compesatio techique for image rejectio i a direct-coversio receiver (DCR). The proposed image-rejectio circuit adopts DC offset cacellatio ad a sig-sig least mea squares (LMS) algorithm with a uique step size adaptatio both for a fast ad precise I/Q mismatch estimatio. I additio, several performace-optimizig desig cosideratios related to accuracy, speed, ad hardware simplicity are discussed. The implemetatio of the proposed circuit i a FPGA results i a imagerejectio ratio (IRR) of 65 db, which is the best performace with modulated sigals, alog with a adaptatio time of 0.9 secods, which is a tefold icrease i the compesatio speed as compared to previously reported circuits. The proposed techique will be a promisig solutio i the area of image rejectio to icrease both the speed ad accuracy of future DCRs. Keywords: Image rejectio, I/Q gai mismatch, I/Q phase mismatch, DC offset, direct-coversio receiver, DCR, low-if, zero-if, LMS algorithm, adaptive step size. Mauscript received Apr. 05, 013; revised Oct. 14, 013; accepted Oct. 1, 013. This work was supported by the Ceter for Itegrated Smart Sesors fuded by the Miistry of Sciece, ICT & Future Plaig as Global Frotier Project (CISS-01M3A6A54195). Sua Kim (phoe: +8 4 350 5491, sua.kim@kaist.ac.kr), Dae-Youg Yoo (dyyoo07@kaist.ac.kr), Giwa Yoo (gwyoo@ee.kaist.ac.kr), ad Sag-Gug Lee (sglee@ee.kaist.ac.kr) are with the Departmet of Electrical egieerig, KAIST, Daejeo, Rep. of Korea. Hyug Chul Park (hcpark@seoultech.ac.kr) is with the Departmet of Electroic ad IT Media Egieerig, Seoul Natioal Uiversity of Sciece ad Techology, Seoul, Rep. of Korea. I. Itroductio The direct-coversio receiver (DCR), referred to as a low itermediate frequecy (low-if) or zero itermediate frequecy (zero-if) receiver, has bee a preferred choice for may wireless commuicatio systems of today due to its simple architecture ad low power cosumptio. However, the iphase/quadrature-phase (I/Q) mismatch, which degrades image sigal rejectio performace, has bee a chroic problem i DCRs, particularly those with a low-if receiver [1]. Some image-rejectio techiques based o aalog circuits have bee cosidered as less competitive due to I/Q mismatches, which stem from a imperfectly balaced layout ad process ad voltage ad temperature variatios []. Curretly, wireless commuicatio systems typically require multi-mode multibad (MMMB) sigle chip solutios. Ufortuately, aalog calibratio circuits for a MMMB sigle chip result i relatively high power cosumptio ad a large chip size, thus icreasig the cost to the difficulty i sharig multiple stadards. For this reaso, some I/Q mismatch compesatio techiques have bee ivestigated. These adopt digital or hybrid (aalog/digital) solutios [3]-[1]. They overcome the limitatios of aalog-oly solutios, ad digital solutios i particular provide a programmable sigle calibratio circuit that is likely to eable a software-defied radio receiver for the implemetatio of a MMMB sigle chip. More specifically, digital I/Q mismatch compesatio techiques have bee developed ot oly by data-aided (DA) estimatio usig o-lie pilot sigals or off-lie test toes [3]- [5] but also by o-data-aided (NDA) (blid) estimatio usig 1 Sua Kim et al. 014 ETRI Joural, Volume 36, Number 1, February 014
statistical attributes [6]-[11]. Although DA estimatio methods are usually fast ad show desirable performace, blid estimatio methods are preferred due to their lower levels of applicatio depedecy ad complexity. Amog the studies of a blid image-rejectio techique, Lerstaveesi ad Sog [10] reported the best image-rejectio ratio (IRR) of 65 db alog with simply implemeted hardware eabled by a sig detectio-oly method. The drawbacks of their techique are its relatively log adaptatio time of 6.7 secods as well as the sigificat degradatio of the level of accuracy that occurs uder a coditio of DC offset. To overcome the DC offset issue, other digital I/Q mismatch compesatio techiques, icludig DC offset cacellatio, have bee ivestigated, but they have resulted i icreased hardware complexity [4]. This paper reports a ew digital image-rejectio circuit usig a blid I/Q mismatch compesatio techique alog with a DC offset cacellatio scheme. The proposed image-rejectio techique shows very precise accuracy, a sigificatly shorter adaptatio time, ad relatively simple hardware compared to previously reported works. A aalysis of the image problem caused by the I/Q mismatches i a DCR is provided i sectio II. The proposed image-rejectio techique, which ivolves the use of a I/Q mismatch compesator ad a precedig DC offset compesator, is described i sectio III. Sectio IV presets the desig cosideratios of the proposed imagerejectio techique for optimum performace i terms of accuracy, speed, ad hardware simplicity. Sectio V shows the measuremet results of the proposed image-rejectio circuit. II. Image Problem i Direct Coversio Receivers The block diagram of a typical direct-coversio receiver (DCR) is show i Fig. 1. I this figure, each mixer of the I ad Q paths multiplies the RF sigal with local carriers with respective phase shifts of 0º ad 90º. This mixig process is equivalet to the multiplicatio of the RF sigal by a complex jωt local carrier, expressed by e = cos( ωt) + jsi( ωt). However, due to the asymmetry betwee the I ad Q paths of the aalog circuits, the complex local carrier is modified as follows: α θ α θ s () t = 1+ cos( ωt ) j 1 si( ωt ), + + (1) α j e j θ θ α (1 + ) + (1 ) e = α j (1 + ) e (1 ) e + ω α jθ e + e θ θ α j t jω t j e e, jω t jω t () RF LNA cos( ω t) 0 / 90 si( ω t) ADC ADC Fig. 1. Block diagram of typical DCR. Wated sigal DC Iterferer f f DSP RF sigal Image of wated sigal Fig.. Effects of mismatched local carrier o received IF sigal spectra. where gai mismatch α ad phase mismatch θ betwee the I ad Q paths are reflected symmetrically, ad the values of α ad θ are assumed to be very small. Assumig that the gai ad phase mismatches are static over the frequecy (f ) of iterest, the mismatches i the amplitude ad phase geerate uwated leakage of the complex local carrier at the egative frequecy j t e ω, as idicated i (). The effects of the mixig process of the received RF sigal ad the mismatched local carrier o the received IF sigal spectra are also ivestigated, as plotted i Fig.. The top portio of Fig. shows the sigal spectra of the RF sigal ad the iterferer located at ± f RF. The middle portio of Fig. shows the sigal spectra of the sigal located at ± f ; the sigal at f is the leakage sigal of the complex local carrier geerated by the mismatches. The bottom portio of Fig. shows the sigal spectra of the dowcoverted RF sigal ad iterferer by the sigal; the uwated image sigals of the RF sigal ad iterferer are also dow-coverted to ± f IF due to the leakage. We defie the received RF sigal as follows: srf() t = Asig cos( ωsigt) + Ait cos( ωitt) Asig jωsigt jωsigt Ait jωitt jωitt = ( e + e ) + ( e + e ), (3) where A sig (A it ) ad ω sig (ω it ) are the amplitude ad the frequecy of the wated RF sigal (iterferer), respectively. The, the received IF sigal dow-coverted by the mismatched complex local carrier is obtaied via ETRI Joural, Volume 36, Number 1, February 014 Sua Kim et al. 13
sif () t = srf () t s () t Asig A α jθ = e + e A A it α jθ + e + e jωift it jωift jω sig IFt jωift where ω IF = ω RF ω. We also assume that the high frequecy compoets geerated from the mixig process are elimiated by low-pass filters. As show i (4) ad Fig., the quality of the wated sigal that is dow-coverted by the mismatched complex local carrier is degraded by the image sigal of the iterferer. The degree of degradatio ca be expressed by a IRR, which is the ratio of the wated sigal power versus the image sigal power, as give by IRR db Psig Asig / = 10log = 10log P A / ( α jθ)/ img sig 4 10 log. α + θ To obtai a IRR of db, which is the typical requiremet of curret wireless commuicatio systems, oly a gai mismatch of 0.1% ad a phase mismatch of 0.1º are allowed. Thus, extremely precise I/Q mismatch compesatio ca remove this image sigal of the iterferer from the sigal bad of iterest, evetually icreasig the sigal-to-oise ratio (SNR)., (4) (5) III. Image Rejectio Techique I this sectio, we describe a image-rejectio techique that resolves the problem metioed i the previous sectio. As show i Fig. 3, the proposed image-rejectio circuit cosists of a DC offset compesator ad a I/Q mismatch compesator. The I/Q mismatch compesator utilizes the sig-sig least mea squares (LMS) algorithm, ad the DC offset compesator precedes the I/Q mismatch compesator for a more accurate mismatch estimatio. The details of the proposed image-rejectio circuit show i Fig. 3 will be explaied i the followig subsectios. 1. Mismatch Estimatio Based o Sig LMS Algorithm A perfectly matched DCR is desiged to receive both I ad Q sigals with the same gai but at 90º out of phase. Assumig that the two sigals are wide-sese statioary, the magitude of each sigal ca be obtaied from its autocorrelatio; hece, the differece betwee the two autocorrelatios idicates the gai mismatch betwee them, as follows: uα = E{ I Q } α θ α θ = E 1+ cos ( t ) 1 si ( t ) ω + ω 1 α 1 α = 1 1 α, (6) + = I/Q Mismatch compesator DC Offset compesator 1 α'/ Image rejecter I I' θ'/ Q Q' 1+α'/ Average Average Z Z α' α' [k] α' [k ] θ' θ' [k] θ' [k ] µ' α µ' α µ' θ µ' θ E{sg(I Q )} Accum. MSB µ α r E{sg(IQ)} Accum. MSB µ θ r sg(i Q) sg(i+q) sg(i) MSB sg(q) MSB Mismatch estimator Fig. 3. Block diagram of proposed image-rejectio circuit. 14 Sua Kim et al. ETRI Joural, Volume 36, Number 1, February 014
Gai error (eα) 0.05 0.04 0.03 0.0 Error covergece characteristic estimated, leadig to a greater amout of IRR. However, more accurate values of α ad θ require smaller values of μ α ad μ θ, which results i a loger adaptatio time for covergece. Therefore, the IRR ad the adaptatio time of the sig LMS algorithm exist i a tradeoff relatioship, which ca explai the relatively log adaptatio time for the high IRR i a imagerejectio circuit i earlier work [10]. 0.01 0.00 5 10 15 0 Number of loops (k) 5 30 Fig. 4. Error covergece characteristics of sig LMS algorithm. where E{ } is a expectatio fuctio, ad sigals I ad Q are borrowed from (1). I a similar maer, because sigals I ad Q are orthogoal ad ucorrelated with each other, the crosscorrelatio of the two sigals idicates the amout of the phase mismatch betwee them, as follows: uθ = E{ I Q} α θ α θ = E 1+ cos( ωt ) 1 si( ωt ) + α cosθ θ = 1 4. (7) Based o this priciple, the gai ad phase mismatches of the I ad Q sigals ca be estimated usig the sig LMS algorithm. These are respectively give by ad α [ k+ 1] = α [ k] + μ α sg( u α ) (8) θ [ k+ 1] = θ [ k] + μ θ sg( u θ ), (9) where α [k] ad θ [k] represet the estimated gai ad phase mismatches at the k-th loop, respectively, ad μ α ad μ θ represet the step size of the LMS algorithm for the gai ad phase mismatch estimatios, respectively. The expectatio values, u α ad u θ, will produce zero if the I ad Q sigals have the same magitude alog with beig 90º out of phase. Defiig the gai error as the differece betwee the actual ad the estimated gai mismatches (that is, e α [k] = α[k] α [k]) ad the phase error as the differece betwee the actual ad the estimated phase mismatches (that is, e θ [k] = θ[k] θ [k]), the sig LMS adaptatio process coverges whe e α [k] ad e θ [k] come withi ± μ α ad ± μ θ, respectively. Figure 4 shows the error covergece characteristics for a example of a gai mismatch of 5% ad a step size of 0.44%. The smaller the values of e α ad e θ are, the more accurately α ad θ ca be. Proposed I/Q mismatch Compesator The mismatch estimatio process usig the sig LMS adaptatio method show i (8) ad (9) coverges whe e α [k] ad e θ [k] come withi ± μα ad ± μ θ, respectively. Cosequetly, as show i Fig. 4, the mismatch estimator displays a uique characteristic i that the errors coverge to zero, at which poit they oscillate betwee two differet values oce the errors are reduced withi ± μ. I this work, as show i Fig. 3, alog with the covergece characteristics, the adoptio of the proposed μ r resolves the tradeoff relatioship betwee the IRR ad the adaptatio time of the sig LMS algorithm. The proposed μ r produces a adaptive step size of μ whe the error coverges, that is, e[k] = e[k ]. The adaptatio process starts with a large iitial step size to speed up the etire adaptatio process; whe the covergece characteristics are detected, the μ r reduces the step size ad cotiues the adaptatio process util the ext covergece is detected. The proposed mismatch estimator adopts a biary searchig algorithm for a simple ad fast estimatio such that the μ r reduces the step size by half at every covergece. The μ process is repeated util the step size μ becomes small eough to satisfy the required IRR such that a high IRR ad fast adaptatio speed ca be achieved simultaeously. I Fig. 5, the process of error Gai error (eα) Step size (µ'α) 0.05 0.04 0.03 0.0 0.01 0.00 0.01 0.030 0.05 0.00 0.015 0.010 0.005 0.000 5 10 15 0 5 5 10 15 0 5 Number of loops (k) Fig. 5. Covergece characteristics of gai error ad step size s. ETRI Joural, Volume 36, Number 1, February 014 Sua Kim et al. 15
covergece i accordace with the step size of the proposed mismatch estimator is demostrated for a example of a gai mismatch of 5%. I the figure, the step size μ α is iitially set to 0.0315(= 5 ) ad is reduced by half whe the error covergece characteristics are detected i e α. The iitial step size ca be optimally determied by the process described i sectio IV. By virtue of the proposed μ r, the gai error is appreciably reduced withi oly a few loops. The proposed mismatch estimator icludig the μ r, which is show i Fig. 3, is ow give by α [ k+ 1] = α [ k] + μ α [ k] sg [ E{sg( I + Q) sg( I Q)}] (10) ad θ [ k+ 1] = θ [ k] + μ θ [ k] sg [ E{sg( I) sg( Q)}], (11) where μ α ad μ θ are the adaptive step sizes produced by the μ r. The expectatio values i (10) ad (11) are implemeted by a simple accumulatio circuit, ad the μ is performed by a shift right operatio. As show i Fig. 3 ad i (10) ad (11), for a simple hardware implemetatio, the gai mismatch estimator is required to detect oly the respective sigs of I+Q ad I Q, istead of takig the etire magitude of I Q. I the same maer, the phase mismatch estimator is required to detect oly the respective sigs of I ad Q, referred to as the sig-sig LMS algorithm. As the error covergece characteristics of the sig-sig LMS algorithm are idetical to those of the sig LMS algorithm, the proposed μ r is also feasible for use with the sig-sig LMS algorithm. As show i Fig. 3, usig the estimated gai ad phase mismatches (α ad θ ) from the proposed mismatch estimator, the image rejector compesates for the received sigal agaist the image sigal caused by the mismatches. The image rejector is implemeted with just four multipliers ad two adders because the compesated sigals (I, Q ) ca be obtaied by a liear combiatio of the mismatched sigals (I, Q) [10]. Give that the proposed I/Q mismatch compesator adopts a blid estimatio method that depeds oly o the statistical properties ad the repeated error covergece characteristics, it has the advatage of applicatio-idepedece. 3. DC Offset Compesator The sig-sig LMS algorithm used i the proposed I/Q mismatch compesator accumulates errors at the DC [10]. As a result, the accuracy of the mismatch estimatio is strogly affected by ay possible sigals or offset compoets at the DC. For a demostratio, the proposed I/Q mismatch compesator, which icludes the proposed mismatch estimator expressed i (10) ad (11), is simulated for a sigal with a itetioally Image-rejectio ratio (db) 70 50 30 0 0 0.05 0.01 0.5 Normalized DC offset (V) Fig. 6. IRR of proposed I/Q mismatch compesator as fuctio of ormalized DC offset. added DC offset. Figure 6 shows the average amout of IRR through 10,000 trials for the proposed I/Q mismatch compesator as a fuctio of the ormalized DC offset to the sigal amplitude. The result demostrates that the IRR is degraded severely with the DC offset. To resolve this problem, the proposed image-rejectio circuit adopts a simple DC offset compesator [13] before the I/Q mismatch compesator, as show i Fig. 3. The DC offset compesator cosists of a offset estimator ad a subtractor for each I/Q path. The offset estimator estimates the offset by averagig a certai period of the received sigals based o the assumptio that the trasmitted sigals are zero-mea stochastic sigals, ad the subtractor the removes the estimated DC offset from the received sigals. IV. Desig Cosideratios The proposed I/Q mismatch compesator, which adopts the sig-sig LMS algorithm with a step size r, improves the speed of the compesatio process while keepig its accuracy itact. However, i some wireless trasceiver systems that operate with low carrier frequecies, a low samplig rate is uavoidable such that the data accumulatio time to obtai the expectatios i (10) ad (11) becomes loger. Whe such a usatisfactory performace is predicted, it is better to use the magitude detectio method to implemet a simple hardware setup, as show i (8) ad (9), so that a smaller amout of data is used for mismatch detectio, tha to use the sig detectio method, as show i (10) ad (11). As a result of the simulatio, the amout of IRR is plotted as a fuctio of the amout of data for accumulatio for a compariso of the magitude detectio ad sig detectio processes, as show i Fig. 7. 10-bit 64-QAM I/Q sigals with gai ad phase mismatches of 5% ad 3º, respectively, are used, ad the IRR results are 16 Sua Kim et al. ETRI Joural, Volume 36, Number 1, February 014
70 50 70 10-bit IRR (db) 30 0 10 Magitude detectio Sig detectio IRR (db) 50 30 1-bit 1 5 10 15 0 Number of data for accumulatio Fig. 7. Plot of IRR as fuctio of umber of data for accumulatio for magitude ad sig detectios. 6 8 10 1 14 16 18 0 Number of data for accumulatio Fig. 9. IRR as fuctio of umber of data for accumulatio for approximated resolutios of sigals (from 10-bit to 1-bit). α' θ' α' µ α r θ' µ θ r µ' α µ' θ Accum. Accum. Magitude detectio I Q Covergece time (Loops) 100 80 0 0 α = 10% α = 7% α = 4% α = 1% Opt.@α = 10% Opt.@α = 7% Opt.@α = 4% Opt.@α = 1% Fig. 8. Block diagram of mismatch estimator with magitude detectio. averaged through 10,000 trials. The magitude detectio, that is, the sig LMS algorithm, ca provide a IRR of db for a small amout of data accumulatio, 6, while the sig detectio method requires cosiderably more data accumulatio, 0, to obtai the same IRR. However, whereas a oe-bit (sig) multiplicatio fuctio ca be implemeted by a simple XNOR gate, as show i Fig. 3, the magitude detectio fuctio requires bulky multibit multipliers, as show i Fig. 8. It is ot easy to justify a higher speed while guarateeig higher accuracy at the expese of a bulky chip size. This coflict ca be mitigated by sacrificig the sigal resolutio for the accumulatio time. To retai the accuracy, the approximatio of the sigal with a few most sigificat bits (MSBs) ca shrik the chip size of the multiplier i the squared ratio, but at the cost of icreasig the amout of data for accumulatio. Figure 9 shows the average IRR through 100 trials as a fuctio of the amout of data for accumulatio for approximated resolutios of the sigal (from 10 bits to 1 bit). This simulatio is performed with a sigal eviromet idetical to that show i Fig. 7; hece, the 0 4 6 8 10 Iitial step size Fig. 10. Covergece time as fuctio of iitial step size for various gai mismatches. results from the approximated resolutio of 10 bits ad 1 bit correspod to the magitude detectio ad the sig detectio methods, respectively. It should be oted that the sigal approximatio process clearly iduces aother DC offset, which degrades the image-rejectio performace. Therefore, a additioal DC offset compesator eeds to be added before the accumulatio (expectatio) process to obtai more accurate results. The iitial step size for the μ r i the proposed I/Q mismatch compesator is also importat to cosider. A large iitial step size icreases the adaptatio speed by tracig mismatches with a large step i the begiig. However, if the actual mismatch is smaller tha the iitial step size, adaptatio time is wasted util the step size is reduced to its miimum value by repeatig the covergece cycles. Figure 10 shows the covergece time (umber of loops) as a fuctio of the iitial step size for various gai mismatches of 10%, 7%, 4%, ad 1% whe the phase mismatch is set to zero. The same ETRI Joural, Volume 36, Number 1, February 014 Sua Kim et al. 17
10-bit 64-QAM I/Q sigals as those used i the previous simulatios are used agai, ad the resultig values are the averages of the data collected through 100 trials. The optimum poits marked i Fig. 10 demostrate that the largest iitial step size does ot always result i the shortest adaptatio time. Therefore, to esure a optimum level of performace, the proposed image-rejectio techique should be applied with a proper iitial step size based o the roughly estimated mismatches. RF 0 +θ/ Phase shifter 90 θ/ Phase shifter 1+α/ VGA 1 α/ VGA (a) Block diagram ADC ADC FPGA V. Measuremet Results Figures 11(a) ad 11(b) respectively show a block diagram ad a image of the measuremet setup used to test the proposed image-rejectio circuit. As show i Fig. 11(a), a sigal of 457 MHz is geerated from a sigal geerator (Agilet 83630B), ad it goes through two phase shifters (JSPHS-661+ from Mii-Circuits), which produce a phase differece of (90º + θ) betwee the two paths. After these phase shifts, two variable gai amplifiers (VGAs) (VG05 from WJ Commuicatios) produce a gai differece of α% betwee the two paths. The 56-QAM sigal, modulated with a symbol rate of 0 ksps, is carried by a RF sigal of 4 MHz geerated from a vector sigal geerator (Agilet E4438C), after which it is dow-coverted to 3 MHz as a low- IF sigal by two mixers (HMC585MS8G from Hittite) with a mismatched complex sigal. The 56-QAM sigal is chose cosiderig the susceptibility of the high-level modulatio sigals to the image sigals. The low-pass filtered (PLP-10.7-75 from Mii-Circuits) IF sigals are coverted ito a discrete form by two 14-bit I/Q ADCs (ADS6P49 from Texas Istrumets) with a samplig clock of 3 MHz. The proposed image-rejectio circuit is implemeted ito a FPGA (XC6SLX150T from Xilix), ad the measured FPGA output is the evaluated usig MATLAB. Figure 1 shows the magitude spectra of the complex 56-QAM before ad after image rejectio from the measuremet. As show i the figure, the IRR of 35 db before the image-rejectio process is improved to 65 db after this process, which is oted to be the highest degree amog the reported measuremet results usig the modulated sigal as the iput. Also, the DC offset before the image rejectio early disappears after the image-rejectio process. The DC offset cacellatio loop is d at every 14 -th istace of data. Because the DC offset compesator precedes the I/Q mismatch compesator, the proposed image-rejectio system ca also be applied to zero-if receivers for self-image rejectio. I Fig. 13(a), the measured covergece times for the gai mismatch estimatio of the proposed ad sig-sig LMS [10] image-rejectio circuits are compared. While the sig-sig Magitude spectrum (db) Magitude spectrum (db) RF/Aalog ADC FPGA (b) Image of measuremet setup Fig. 11. Testig proposed image-rejectio circuits. 80 0 0 6 4 0 4 6 Frequecy (MHz) (a) Before image rejectio 80 0 0 IRR ~35 db IRR ~65 db 6 4 0 4 6 Frequecy (MHz) (b) After image rejectio Fig. 1. Magitude spectra of measured 56-QAM before ad after image rejectio. LMS method takes.8 secods to coverge with a fixed step size of 0.044%, the proposed method takes 0.7 secods to coverge with a adaptive step size from the iitial value of1.56% to the fial value of 0.044%, which is four times 18 Sua Kim et al. ETRI Joural, Volume 36, Number 1, February 014
Estimated gai mismatch Estimated gai mismatch 0.03 0.0 0.01 0.00 0.03 0.04 0.016 0.008 0.000 0.5 1.0 1.5.0.5 3.0 Covergece time (s) (a) 0.016 0.01 0.008 0.004 0.000 0. 0.4 0.6 0.8 Covergece time (s) (b) Proposed Sig-sig LMS [10] Adaptive step size Estimated phase mismatch Estimated phase mismatch 0.08 0.06 0.04 0.0 0.00 0.08 0.06 0.04 0.0 0.00 0.016 0.01 0.008 0.004 0.000 0. 0.4 0.6 0.8 Covergece time (s) (b) Proposed Sig-sig LMS [10] 4 6 8 Covergece time (s) (a) Adaptive step size Fig 13. Gai mismatch adaptatio: (a) compariso of covergece times ad (b) adaptatio process alog with adaptive step size. Fig 14. Phase mismatch adaptatio: (a) compariso of covergece times ad (b) adaptatio process alog with adaptive step size. shorter. Both of the image-rejectio circuits utilize data accumulatio of 0 for oe loop with the same samplig clock of 3 MHz. Figure 13(b) shows the adaptatio process of the gai mismatch estimatio alog with its adaptive step size i the proposed image-rejectio circuit. As iteded, the estimated gai mismatches approach rapidly toward covergece with a large step size i the begiig, while the fial covergece gives more precisely estimated gai mismatches with a fie step size. Figure 14(a) shows a compariso of the measured covergece times for the phase mismatch estimatio of both the proposed ad sig-sig LMS [10] image-rejectio circuits. I Fig. 14(a), while the sig-sig LMS method i earlier work [10] takes 9 secods to coverge with a fixed step size of 0.044%, the proposed method takes oly 0.9 secods to coverge with a adaptive step size from the iitial value of 1.56% to the fial value of 0.044%, which is te times shorter. Both of the image-rejectio circuits use the same umber of data accumulatio istaces ad the same samplig clock as those used i the gai mismatch estimatio. Figure 14(b) shows the adaptatio process of the phase mismatch estimatio alog with the adaptive step size i the proposed imagerejectio circuit. Similar to the gai mismatch estimatio, the phase mismatch estimatio has show both fast ad precise adaptatios. The estimated phase mismatch i Fig. 14 (6.7% i radia, Table 1. Performace compariso betwee this work ad other works. This work [10] [9] [8] [1] [3] IRR 65 db (digital) 65 db (digital) db (digital) 57 db (hybrid) 55 db (digital) 63 db (hybrid) Adaptatio time (mismatch) 0.9 s (6.7%) 6.7 s (6.5%) - 5 ms ( ± 0.0 V) 5 ms (4.4%) - Samplig frequecy 3 MHz MHz 7 MHz 5 MHz 480 MHz -500 MHz 1.05 MHz Modulatio 56-QAM 56-QAM NTSC CW CW+GSM FM Estimatio method NDA NDA NDA NDA DA+NDA DA Commets Best IRR high speed Best IRR low speed Good IRR High speed w/cw calibratio High speed w/cw factory calibratio Good IRR ETRI Joural, Volume 36, Number 1, February 014 Sua Kim et al. 19
3.8º i degree) is 3.4 times larger tha the estimated gai mismatch i Fig. 13 (%). Whereas the covergece time of the phase mismatch estimatio process is oly 1.3 times loger tha that of the gai mismatch estimatio process i the proposed method, the covergece time i the sig-sig LMS method is directly proportioal to the amout of mismatch. Therefore, the proposed image-rejectio circuit is more advatageous, especially i cases with a high degree of mismatch. Lastly, the performace of this work is compared with the performaces of previously reported image-rejectio circuits, as summarized i Table 1. Overall, compared to the results i the other studies, this work shows the best performace i terms of the IRR, owig to the precise mismatch estimatio. It also shows a high adaptatio speed cosiderig its modulatio level. These outstadig results are attributed to the proposed adaptive step size scheme. VI. Coclusio I this paper, we proposed a ew digital blid I/Q mismatch compesatio techique for image rejectio i a DCR. The proposed image-rejectio circuit combies DC offset cacellatio ad a adaptive step size sig-sig LMS algorithm for fast ad precise I/Q mismatch compesatio. I additio to the eed for a DC offset cacellatio block prior to the I/Q mismatch compesatio block, both the I/Q mismatch compesatio ad the step size techiques were explaied i detail. Moreover, the several desig cosideratios to optimize the performaces of the proposed image-rejectio circuit were discussed i terms of its accuracy, speed, ad hardware simplicity. Fially, the implemetatio of the proposed techique i a low-if receiver system showed a desirable IRR of 65 db alog with a sigificat reductio i the adaptatio time compared to the results i earlier studies. Thus, the proposed techique appears to be a promisig solutio for image rejectio issues i that it icreases both the speed ad the accuracy of the output by adoptig a uique step size r. Moreover, it is feasible for use with a simple hardware cofiguratio via a sig detectio-oly method. [3] L.J. Breems, E.C. Dijkmas, ad J.H. Huijsig, A Quadrature Data-Depedet DEM Algorithm to Improve Image Rejectio of a Complex Modulator, IEEE J. Solid-State Circuits, vol. 36, o. 1, Dec. 001, pp. 1879-1886. [4] G.-T. Gil et al., Joit ML Estimatio of Carrier Frequecy, Chael, I/Q Mismatch, ad DC Offset i Commuicatio Receivers, IEEE Tras. Veh. Techol., vol. 54, o. 1, Ja. 005, pp. 338-349. [5] K. Haddadi et al., Four-Port Commuicatio Receiver with Digital IQ-Regeeratio, IEEE Microw. Wireless Compo. Lett., vol. 0, o. 1, Ja. 010, pp. 58-. [6] L. Yu ad W.M. Selgrove, A Novel Adaptive Mismatch Cacellatio System for Quadrature IF Radio Receivers, IEEE Tras. Circuits Syst. II, Aalog Digit. Sigal Process., vol. 46, o. 6, Jue 1999, pp. 789-801. [7] C.C. Che ad C.-C. Huag, O the Architecture ad Performace of a Hybrid Image Rejectio Receiver, IEEE J. Sel. Areas Commu., vol. 19, o. 6, Jue 001, pp. 109-10. [8] L. Der ad B. Razavi, A -GHz CMOS Image-Reject Receiver with LMS Calibratio, IEEE J. Solid-State Circuits, vol. 38, o., Feb. 003, pp. 167-175. [9] C.-H. Heg et al., A CMOS TV Tuer/Demodulator IC with Digital Image Rejectio, IEEE J. Solid-State Circuits, vol., o. 1, Dec. 005, pp. 55-535. [10] S. Lerstaveesi ad B.-S. Sog, A Complex Image Rejectio Circuit with Sig Detectio Oly, IEEE J. Solid-State Circuits, vol. 41, o. 1, Dec. 006, pp. 693-70. [11] G.-T. Gil, Y.-D. Kim, ad Y.H. Lee, No-Data-Aided Approach to I/Q Mismatch Compesatio i Low-IF Receivers, IEEE Tras. Sigal Process., vol. 55, o. 7, July 007, pp. 33-3365. [1] I. Elahi, K. Muhammad, ad P.T. Balsara, I/Q Mismatch Compesatio Usig Adaptive Decorrelatio i a Low-IF Receiver i 90-m CMOS Process, IEEE J. Solid-State Circuits, vol. 41, o., Feb. 006, pp. 395-4. [13] H. Yoshida, H. Tsurumi, ad Y. Suzuki, DC Offset Caceller i a Direct Coversio Receiver for QPSK Sigal Receptio, IEEE It. Symp. Persoal, Idoor, Mobile Radio Commu., Bosto, MA, USA, Sept. 8-11, 1998, vol. 3, pp. 1314-1318. Refereces [1] B. Razavi, Desig Cosideratios for Direct-Coversio Receivers, IEEE Tras. Circuits Syst. II, Aalog Dig. Sigal Process, vol. 44, o. 6, Jue 1997, pp. 48-435. [] Y. Cheg, The Ifluece ad Modelig of Process Variatio ad Device Mismatch for Aalog/RF Circuit Desig, (ivited) 4th IEEE It. Caracas Cof. Devices, Circuits, Syst., Orajestad, Aruba, Apr. 17-19, 00, pp. D046:1-D046:8. 0 Sua Kim et al. ETRI Joural, Volume 36, Number 1, February 014
Sua Kim received her BS ad MS degrees i electrical egieerig from the Korea Advaced Istitute of Sciece ad Techology (KAIST), Daejeo, Rep. of Korea, i 006 ad 009, respectively. She is curretly workig toward her PhD degree i electrical egieerig at KAIST. Her research iterests iclude RF itegrated circuit desigs ad further digital calibratio circuit desigs for wireless trasceivers. Recetly, her research iterests exteded to extremely high-frequecy (THz) device ad circuit desigs based o CMOS techology. Dae-Youg Yoo received his BS degree i electroics egieerig from Soog-Sil Uiversity, Seoul, Rep. of Korea, i 005 ad his MS ad PhD degrees i iformatio ad commuicatio egieerig at the Korea Advaced Istitute of Sciece ad Techology (KAIST), Daejeo, Rep. of Korea, i 007 ad is curretly workig toward his Ph.D. degree i electrical egieerig at KAIST. His curret research iterests iclude CMOS-based RF ad aalog IC desigs, such as LNAs, mixers, ad evelope detectors for various radio trasceiver applicatios. Curretly, his research iterests regard ultra-low power receiver ad digital calibratio circuits based o CMOS techology. Hyug Chul Park received his BS, MS, ad PhD degrees i electrical egieerig from the Korea Advaced Istitute of Sciece ad Techology (KAIST), Daejeo, Rep. of Korea, i 1996, 1998, ad 003, respectively. From 003 to 005, he was a SoC desig egieer with Hyix Semicoductor, Seoul, Rep. of Korea. From 005 to 010, he was a assistat professor at Habat Natioal Uiversity, Daejeo, Rep. of Korea. I 010, he joied the faculty of the Departmet of Electroic ad IT Media Egieerig, Seoul Natioal Uiversity of Sciece ad Techology, Seoul, Rep. of Korea, where he is curretly a assistat professor. His curret research iterests iclude wireless modulatio/demodulatio algorithms, system desig/implemetatio, ad iterface study betwee RF/IF stages ad digital sigal processig. Giwa Yoo was bor i Pohag, Rep. of Korea, i 1959. He received his BS degree from Seoul Natioal Uiversity (SNU), Seoul, Rep. of Korea, i 1983 ad his MS degree from KAIST, Daejeo, Rep. of Korea, i 1985. Also, he received his PhD degree from the Uiversity of Texas at Austi, Austi, TX, USA, i 1994. From 1985 to 1990, he was with the LG Group, Rep. of Korea. From 1994 to 1997, he was with the Digital Equipmet Corporatio, USA. From 1997 to 009, he was a professor of the School of Egieerig, Iformatio & Commuicatios Uiversity (ICU), Rep. of Korea. Curretly, he is a professor i the Departmet of Electrical Egieerig, KAIST. His research areas of iterest iclude solid-state ao devices ad itelliget algorithms ad their applicatios for RF ad wireless systems. Dr. Yoo is a member of IEEE ad KIICE, Rep. of Korea. Sag-Gug Lee received his BS degree i electroics egieerig from Kyugpook Natioal Uiversity, Rep. of Korea, i 1981 ad his MS ad PhD degrees i electrical egieerig from the Uiversity of Florida, Gaiesville, FL, USA, i 1989 ad 199, respectively. I 199, he joied Harris Semicoductor, Melboure, FL, USA, where he was egaged i silico-based RFIC desigs. From 1995 to 1998, he was with Hadog Uiversity, Pohag, Rep. of Korea, as a assistat professor i the School of Computer ad Electrical Egieerig. From 1998 to 009, he was with the Iformatio ad Commuicatios Uiversity, Daejeo, Rep. of Korea, ad became a full professor. Sice 009, he has bee with the Korea Advaced Istitute of Sciece ad Techology (KAIST), Daejeo, Rep. of Korea, i the Departmet of Electrical Egieerig as a professor. His research iterests iclude CMOS-based RF, aalog, ad mixed mode IC desigs for various radio trasceivers, especially the ultra-low power applicatios. Recetly, his research iterests exteded to extreme high-frequecy (THz) circuit desigs, display semicoductors, ad eergy-harvestig IC desigs. ETRI Joural, Volume 36, Number 1, February 014 Sua Kim et al. 1