Analog IC Design Lecture 1,2: Introduction & MOS transistors Henrik.Sjoland@eit.lth.se
Part 1: Introduction
Analogue IC Design (7.5hp, lp2) CMOS Technology Analog building blocks in CMOS Single- and multiple stage Analysis and design Simulation and layout Website: www.eit.lth.se/course/etin25
Motivation Analog + the world is analog + high speed, low power IC + compact + low cost in mass production CMOS + dominating digital technology => low cost + system on chip + rapid development
Analog IC-project (7.5hp, vt1-2) Design your own chip in 65nm CMOS technology! Fabrication of real ICs Project groups with 3 or 4 students Large integrated system Analog and digital
Analog IC-project Examples of chips designed recent years: Fully integrated FM transmitter Class-D audio amplifiers DC/DC converters Wireless meat thermometer Continuous time delta-sigma ADC for mobile phones DNA sequencing Power amplifiers for NB IoT Several papers at conferences (mainly NorCAS)
Analog IC Verification (7.5hp, ht1-2) Measure the fabricated chips from IC-project
Integrated Radio Electronics (7.5hp, vt1) Given every 2 years, 2017, 2019 Required knowledge: Analog IC Design Recommended: Radio RF CMOS Close to research GHz frequencies Building blocks: LNA,VCO, Mixer, PA... Applications: Cell phones, WLAN, GPS, 60GHz wireless, Car radar,
Course information Course literature: Gray, Hurst, Lewis and Meyer: Analysis and design of Analog Integrated Circuits, 5 th ed. On-line: Laboratory manual Technology data sheet Old exams Laboratories registration
Contact information Course website: www.eit.lth.se > Education > Courses > Per scholar year > Analogue IC design (ETIN25) Direct link: http://www.eit.lth.se/course/etin25 Email: Henrik.Sjoland@eit.lth.se Phone: 046 222 95 13 Room: E:2345
Course information Prerequisite: Analogue Design/ Analog Elektronik ESS020 (or ETI 011, ETI240/0101, ESSF01) Compulsory for: Integrated Radio Electronics IC Project & Verification (Analog and Mixed Signal) Course elements: 11 lectures 7 exercises 3 laboratories To pass the course: Pass the exam Pass the laboratories (lab reports)
Course information Lectures: Exercises: Babak Mohammadi Labs: Jonas Lindstrand Stefan Andric
Course content The most important parts of the course: 1) the interface between design and manufacturing of integrated circuits 2) the analog behaviour of the MOS-transistor 3) the effect of parasitics, mainly capacitive 4) basic analog building blocks in CMOS
Course content Detailed topics: 1. The MOSFET 2. Technology, layout and passive components 3. Transistor amplifier stages Single transistor Multiple transistor 4. Current mirrors and active loads 5. Output stages and frequency response 6. CAD tools 7. Operational amplifiers and frequency compensation 8. Noise 9. Fully differential opamps
Course schedule
Course schedule
Course schedule
Exam Date and time: Monday January 8, 08.00-13.00 Place: MA10 Allowed at the exam: The book Analysis and design of Analog Integrated Circuits Calculator
Lecture slides Available at the webpage, under Course Material Restricted access: User Name: Student Password: CurrentMirr#r
Part 2: MOS transistors
Contents The MOSFET Introduction Basic physics PN junctions MOSFET device structure and characteristics Regions of operation Small-signal model Non-idealities Parasitic capacitances Velocity saturation
Introduction From 1959 to now, and continuing What makes the technology so interesting? Many devices on a single chip Combine digital and analog building blocks High yield, suitable for mass production But Source: ieee.org The process is complicated not cheap The analog performance is not always the best
Introduction Transistors are key elements Provide signal gain Models needed - Simulations -> Accuracy - Hand calculations -> Simplicity - Derived from physics -> Understanding Nonlinear - Interesting behaviour - Complicated mathematics - Often linearized
Basic Physics Periodic Table Source: ptable.com
The PN junction Lecture about transistors, but we start with diodes. Why? Reason: There are undesired (= parasitic) diodes in transistors
The PN junction
The PN junction Junction capacitance: C j = dq/dv R = C j0 / (1- V D / ψ 0 ) (Eq. 1.21)
The PN junction Group discussion: How to manufacture a diode with abrupt dopant profile?
The PN junction What happens for a graded doping profile instead of an abrupt profile? C j = C j0 / 3 (1- V D / ψ 0 )
The PN junction The reverse voltage cannot be increased indefinitely: The junction will break down if a critical maximum electrical field is built up, E crit.
The MOS transistor An now the core of the topic: The MOS transistor
The MOS transistor CMOS = Complementary Metal Oxide Semiconductor CMOS inverter
Device structure & characteristics The MOSFET is: A symmetrical device A lateral device Off state: Two back-to-back PN junctions The gate and substrate, with gate oxide as isolator, act as a capacitor
Device structure & characteristics What happens if V S = V D? For V GS > V t an inversion layer is created, and thus a channel exists The channel is symmetrical w r t source and drain The depletion region underneath the channel is symmetrical as well V t is dependent on substrate doping density, source- and bulk voltage, gate oxide capacitance, etc. (Eq. 1.140)
Device structure & characteristics What happens if V S V D? Or more specifically, if V D > V S? The channel loses its symmetry and is eventually pinched-off at the drain for V DS = V GS - V t
Device structure & characteristics I D vs. V DS I D vs. V GS
Device structure & characteristics In pinch-off, the effective channel length is less than the drawn length L L eff = L Xd where X d is the depletion-layer width L eff is a function of V DS Large-signal drain current I D : I D = 0.5k (W/L)(V GS -V t ) 2 (1+λV DS ) (Eq. 1.165) The channel length modulation coefficient λ = (1/L eff ) dx d /dv DS (Eq. 1.163 and 1.164)
Device structure & characteristics Regions of operation of the MOSFET:
Device structure & characteristics MOSFET is a 4 terminal device - Body effect (back gate) V t depends on V SB 110831 39
Device structure & characteristics MOSFET in saturation, large-signal: V ov = V GS V t = (2I D /k (W/L)) (Eq. 1.166), (ignoring channel length modulation λ) This overdrive voltage occurs frequently in transistor equations 110831 40
Small-signal model Difficult to use large signal equations (non-linear) Linearization => small signal model To find linear performance: - Gain - Bandwidth - Input & output impedance - The small-signal model contains only linear elements like: - R, C, (L), g m
Small-signal model Assume the biasing is fixed, with a certain V GS and V DS resulting in a certain I D (DC, large-signal) Then small (AC) changes will not impact the bigger picture and we can consider the impact of AC signals separately. Source: Connexions, cnx.org
Small-signal model In saturation: Transconductance g m = I D / V GS = k (W/L)(V GS -V t )(1+λV DS ) k (W/L)(V GS -V t ) = (2k (W/L) I D ) = 2I D /V ov (Eq. 1.180) In saturation: intrinsic gate-source capacitance C gs = (2/3)WLC ox (Eq. 1.191) In saturation: output resistance r o = V DS / I D = 1/λI D (Eq. 1.194) (in saturation: C gd =0)
Small-signal model Parasitic capacitances
Small-signal model Model including: - parasitic capacitances - body effect
Small-signal model Performance measure: transition frequency f T Where the magnitude of the common-source (CS) current gain is 1. f T = (1/2π)ω T = (1/2π)(g m /(C gs + C gb + C gd ) (1.5µ/2πL 2 )(V GS V t ) (Eq. 1.208)
Non-idealities Short-channel effects: non-idealities due to shrinking length L Velocity saturation Mobility degradation V d =µ n E Velocity saturation impacts g m, f T, V DS(act).
Non-idealities Velocity saturation causes deviation from the square-law characteristic. For large-signal I D, this can be modeled by a series source resistance R SX : R SX = 1/E c µ n C ox W (Eq. 1.232)
Non-idealities Substrate current flow: Due to impact ionization, causing holes to flow from the drain away to the substrate The current depends on V DS
Weak inversion (sub threshold) V GS < V t A depletion region is present The nmosfet works as an npn (bipolar) device
Weak inversion I D = I t W/L exp((v GS -V T )/nv T ) x (1- exp(-v DS /V T )) g m = (I D /V T )(C ox /(C js + C ox ) (Eq. 1.253)
Weak inversion Compare g m /I D for weak inversion and saturation: