Politecnico di Torino ICT School Amplifiers Telecommunication Electronics A2 Transistor amplifiers» Bias point and circuits,» Small signal models» Gain and bandwidth» Limits of linear analysis Op Amp amplifiers Previous courses Transistor amplifiers (lesson A2 and A3) Reference circuit and design procedures Linear model Nonlinear model» Distortion, harmonics, gain compression Lab 1: small signal analysis (linear model) Lab 2: large signal behaviour (nonlinear model) References: Transistor circuits 1.1, 1.2 06/09/2007-1 TLCE - A2-2007 DDC 06/09/2007-2 TLCE - A2-2007 DDC Amplifiers in positioning radio receiver GPS radio IC LNA: Low Noise Amplifier Wide dynamic range, low distorsion LNA: Low Noise Amplifier IF tuned amplifiers VGA: Variable Gain Amplifier VGA: Variable Gain Amplifier 06/09/2007-3 TLCE - A2-2007 DDC 06/09/2007-4 TLCE - A2-2007 DDC Amplifiers in radio structure OpAmp based Amplifers: where? IF channel LNA (low noise amplifier) RX input amplifiers - Low noise, wide dynamic IF channel amplifiers Amplifiers and filters for A/D converters PA (power amplifier) TX output amplifiers - High efficiency, low distorsion 06/09/2007-5 TLCE - A2-2007 DDC Audio interface (mike and earphones) 06/09/2007-6 TLCE - A2-2007 DDC Page 1 2007 DDC 1
Fully differential OpAmp Transistor-based amplifiers: where? Differential input AND differential output Double feedback loop Better balance LNA (low noise amplifier) RX input amplifiers: - Low noise -Widedynamicrange PA (power amplifier) TX output amplifier: - High efficiency - Low harmonic contents 06/09/2007-7 TLCE - A2-2007 DDC 06/09/2007-8 TLCE - A2-2007 DDC What matters in an amplifier Gain Bandwidth Linearity (no distorsion) Noise (low) There is always some nonlinearity Reduce, counteract» Negative feedback, tuned circuits, Used to build» VGA/dynamic compressor»mixers» oscillators Amplifiers or. Types of amplifiers Transistor amplifiers Basic circuit Linear transistor model Biasing Small signal analysis Frequency response Design of amplifiers Specifications Design sequence Lab experiment Lesson A2: Amplifiers 06/09/2007-9 TLCE - A2-2007 DDC 06/09/2007-10 TLCE - A2-2007 DDC Small signal BJT,MOS,MOS-FET Same linear model (gm or hybrid) Transistor models Large signal: same method, different models BJT: exponential large signal model (rather simple) MOS: lin/log/quad large signal model (complex!) analytic model for BJT euristic models for MOS Similar effects and countermeasures Common Emitter circuit BJT reference circuit R E1 R E2 06/09/2007-11 TLCE - A2-2007 DDC 06/09/2007-12 TLCE - A2-2007 DDC Page 2 2007 DDC 2
Amplifier features and analysis Analysis of BJT circuit: step 2 AC amplifier: BJT Common Emitter circuit Input and output AC coupling: C1, C4 Emitter feedback DC: stabilize the bias point AC control the gain Analysis or design: Bias point AC passband gain (linear model) Cutoff frequency Nonlinear model analysis CE amplifier with bipolar transistor (BJT) Find bias point: (I C, V CE ) The bias point must be in the active region: V CE > 0,2 V V CE 06/09/2007-13 TLCE - A2-2007 DDC 06/09/2007-14 TLCE - A2-2007 DDC Analysis of BJT circuit: step 3 BJT (simplified) models CE amplifier with bipolar transistor (BJT) Find bias point: (I C, V CE ) Simplified model for bias point analysis (active area) B I B β I B C The bias point must be in the active region: V CE > 0,2 V Compute small signal parametares: hie, hfe Simplified model for small signal analysis, CE configuration. Parameters h fe i B or g m v BE B E g m v BE C hie, hfe, gm... h ie = V T * h fe /I C g m = I C /V T v BE E 06/09/2007-15 TLCE - A2-2007 DDC 06/09/2007-16 TLCE - A2-2007 DDC Bias point analysis BE net DC bias point Small signal parameters depend on I C and (to a lesser extent) on V CE solve bias point first I C I E is fixed by Base-Emitter mesh V CE is related with Collector-Emitter mesh Step 1: compute I C Equation on BE mesh First approximation: I B = 0 (h FE ) Step 2: check V CE value; Equation on CE mesh if > 0,2 V active area Ic depends from these devices Ic depends only from Base-Emitter mesh, R1, R2 are mapped to a unique mesh, with equivalent Thevenin parameters V BB, R B 06/09/2007-17 TLCE - A2-2007 DDC 06/09/2007-18 TLCE - A2-2007 DDC Page 3 2007 DDC 3
BE mesh CE net BE equivalent circuit V BB Vce depends from devices in the CE mesh Vce depends from Ic and devices at the Collector node Vce= -Ic-IeRe Vce 06/09/2007-19 TLCE - A2-2007 DDC 06/09/2007-20 TLCE - A2-2007 DDC Design choices Example: bias point, SS parameters If h fe is large, I B = (V BB V BE )/R B Design variables (for a given Ic) V BB, R B /V B Large V BB Good stability vs V BE (mainly due to temperature) Reduced output dynamic range (V CE ) Small R B Good stability vs β (mainly due to parameters spreading) High power consumption (R B = R 1 //R 2 ) R1 120 kω R2 82 kω 330 Ω Re2 12 kω 10 kω 12 V hfe 100 Vbb = 12 * 82 / 202 = 4,9 V Rb = 48,7 kω Ie = 4,3 / (12,33 + 48,7/100) = 0,335 ma Vce = 4,35 V hie = 7,76 kω gm = 12,88 ma/v C1 R1 R2 I1 Re2 Ie Q1 C3 C2 06/09/2007-21 TLCE - A2-2007 DDC 06/09/2007-22 TLCE - A2-2007 DDC MOS reference circuit Lesson A2: Amplifiers Common Source G S D R E1 Types of amplifiers Transistor amplifiers Basic circuit Linear transistor model Biasing Small signal analysis Frequency response R E2 Design of amplifiers Specifications Design sequence Lab experiment 06/09/2007-23 TLCE - A2-2007 DDC 06/09/2007-24 TLCE - A2-2007 DDC Page 4 2007 DDC 4
BJT circuit: small signal analysis Gain analysis equivalent circuit Parts related with in-band gain (C3 open, C1, C2, C4 shorted) Compute the gain using the linear model I B hfe I B Reminders In signal analysis = 0 R1//R2 h ie Z E Z C R1, R2 are connected as parallel resistances to v O = i C Z C ; i C = i B h fe ; v i = i B h ie + i B (1+h fe ) Z E 06/09/2007-25 TLCE - A2-2007 DDC 06/09/2007-26 TLCE - A2-2007 DDC Results with linear model Example: gain with linear model 1 Gain with linear model If hfe >> 1 hie becomes negligible with respect to Z E (hfe+1) (h fe +1) hie = 8,96k hfe = 100 g m = 12,9 ma/v 12 kω 330 Ω 10 kω R1//R2 Ib hie hfe Ib Total load on the Collector: // Av = - (12k//10k)*100 / (8,96k + 330*100) = -13 06/09/2007-27 TLCE - A2-2007 DDC 06/09/2007-28 TLCE - A2-2007 DDC Example: gain with linear model 2 Example: Ri and Ro hie = 8,96k hfe = 100 g m = 12,9 ma/v 12 kω 330 Ω 10 kω Vbe R1//R2 hie g m Vbe hie = 8,96k hfe = 100 g m = 12,9 ma/v 12 kω 330 Ω 10 kω R1//R2 Ib hie hfe Ib Total load on the Collector: // Av = Ri =? Ro =? 06/09/2007-29 TLCE - A2-2007 DDC 06/09/2007-30 TLCE - A2-2007 DDC Page 5 2007 DDC 5
Frequency response Wideband AC amplifier Wideband AC amplifier Emitter/source feedback» stabilize DC bias point and in-band AC gain A V Z C /Z E Lower band limit: interstage series coupling capacitance Z E frequency behaviour transformer coupling (if any) Higher band limit parallel capacitors towards ground» designed capacitors» wiring parasitic» active device parasitic V u /V i (db) Band pass 1 10 100 Low cutoff frequency (C1, C2, Ce) f (Hz) High cutoff frequency (C3, Cp1, Cp2) 06/09/2007-31 TLCE - A2-2007 DDC 06/09/2007-32 TLCE - A2-2007 DDC High Frequency: L and C parasitics Parasitic capacitances Output Capacitance (load) insert isolation stage (Common Collector/Drain) PCB parasitic L and C Use SMD devices Careful PCB design Active device parasitic (C BC ) multiplied by Miller effect use HF devices with low C BC (GaAs, SiGe,..) proper circuit configuration (Common Base, cascode) C1 R1 R2 Cp1 Re2 C3 Q1 Ie C2 C4 Cp2 Cp1: Base-Collector parasitic (Cbc) C3: designed to set high cutoff frequency 06/09/2007-33 TLCE - A2-2007 DDC 06/09/2007-34 TLCE - A2-2007 DDC Miller effect Other circuit configurations: CC Parasitic Base-Collector capacitance (C BC ) is connected between to nodes with inverting gain A Corrent I cond flowing in C BC : I cond = jωc BC (V B V C ) = jωc BC (V B +AV B ) = jωc BC (A+1) V B (multiplied by Miller effect) Admittance multiplied by (gain +1) Common Collector / Common Drain high Zi low Zo No Miller effect (Av 1) Current gain Va Actual equivalent capacitance at Base node: C actual = C BC * (A+1) This capacitance limits the high frequency response Need for Miller free circuit configurations Good for Load separation Increasing Zi Lowering Zo Re Q1 06/09/2007-35 TLCE - A2-2007 DDC 06/09/2007-36 TLCE - A2-2007 DDC Page 6 2007 DDC 6
Other circuit configurations: CB Cascode amplifier Common Base / Common Gate low Zi, high Zu C BC connected to GND: No Miller effect Low Zi Low Zo ltage gain Q2 Only basic circuit, no bias network Va Q1: CE stage, Low Zc low V gain Good current gain -Low Vce - Low Miller effect Common Base Va Q2 Q1 Vu combined with CE in the cascode stage Va Vu Q2: CB stage Good voltage gain - No Miller effect Common Emitter 06/09/2007-37 TLCE - A2-2007 DDC 06/09/2007-38 TLCE - A2-2007 DDC Cascode amplifier Lesson A2: Amplifiers Common Base stage (CB) C BC parasitic towards ground no Miller effect (C multiplier) provides voltage gain Common Emitter output to low-z load small voltage dynamic provides current gain minimum effect of C BC parasitic capacitance Overall result higher gain at high frequency Types of amplifiers Transistor amplifiers Basic circuit Linear transistor model Biasing Small signal analysis Frequency response Design of amplifiers Specifications Design sequence Lab experiment 06/09/2007-39 TLCE - A2-2007 DDC 06/09/2007-40 TLCE - A2-2007 DDC Lab 1 and lab 2 Amplifier design specs Design an amplifier from the provided specs A real design:» Multiple solutions» Some specs are implicit» Devices have poorly defined parameters Simulate, build, measure Homework: design, simulation In the lab: build, measure, debug Compare specs/simulation/measurements Linear model lab 1 Nonlinear model lab 2 Single-Transistor Amplifier with: ltage gain Vu/ = 13 (nominal) Bandwidth -3 db from 200 Hz to 20 khz (minimum) Output dynamic at least 3 Vpp on 10 kω load (or higher) Supply voltage 12 V (nominal) 2N2222A Transistor All feature within +/-10%, at ambient temperature Gain and output dynamic at band center References: Text: design procedure: Cap 1, 1.P1 Lab procedures: Cap 1, 1.L1 web guides: lab 1 06/09/2007-41 TLCE - A2-2007 DDC 06/09/2007-42 TLCE - A2-2007 DDC Page 7 2007 DDC 7
Design sequence Select the circuit: CE with Ze, bias network Vb/Re Choose a no-load dynamic, or Ve, or Stabilty/power/dynamic tradeoff Compute, or no-load dynamic, or Ve Compute Ic Design bias network to get Ic: R1, R2, +Re2 Computer from gain specs Get C1, C2, C3, C4 from frequency behaviour specs. Passive devices (R and C) available in normalized values Know what they are (E12, E24, ) Only E12 values available in the lab From computed to normalized values Checks and measurements The transfer function is modified Component tolerances expand the Bode plot (a line) to a somewhat wide band Specs must lie within the strip Compare measurements with allowed variations of Bode plot 06/09/2007-43 TLCE - A2-2007 DDC 06/09/2007-44 TLCE - A2-2007 DDC Theory and practice Lesson A2: final questions V u /V i (db) Measured values (with errors) Which different types of amplifiers can be found in a radio system? Write an approximate expression for the voltage gain of a CE amplifier. Which elements limit the bandwidth of amplifiers? Design specification 1 10 100 1k Design band, taking into account device parameters tolerances f (Hz) Which are the best configurations for high bandwidth amplifiers? List the specifications for an amplifier (what you must know to selct an amplifier from a catalogue) Define the design procedure for a single transistor amplifier Describe the lab procedures to measure the frequency response on an amplifier. 06/09/2007-45 TLCE - A2-2007 DDC 06/09/2007-46 TLCE - A2-2007 DDC Next lesson (A3) How to evaluate the effects of nonlinearity How to reduce the nonlinearity effects Feedback Tuned circuits How to exploit nonlinearity Exploit harmonics Exploit gain changes Lab 2: Large signal behaviour (nonlinear) Text reference: Narrowband and tuned amplifiers: 1.2.3 06/09/2007-47 TLCE - A2-2007 DDC Page 8 2007 DDC 8