Design for MOSIS Educational Program (Research) Testing Report for Project Number 89742 Prepared By: Kossi Sessou (Graduate Student) and Nathan Neihart (Assistant Professor) Bin Huang (Graduate Student) and Degang Chen (Professor) Chongli Cai (Graduate Student) and Degang Chen (Professor) Institution: Department of Electrical and Computer Engineering, Iowa State University Date of Submission: April 14, 2014
DESIGN 1 FULLY INTEGRATED WIDE BANDWIDTH CLASS F POWER AMPLIFIER WITH RECONFIGURABLE HARMONIC TERMINATION Prepared By: Kossi Sessou (Grad Student) and Nathan Neihart (Assistant Professor) Institution: Department of Electrical and Computer Engineering, Iowa State University INTRODUCTION With the type of enriched and enhance mobile phone features available to the end user, the population of power amplifiers (PAs) and their requirements at the antenna interface is growing. For an efficient next generation wireless communication systems, frequency agile PAs are an absolute must to allow game changing innovations. To that extent, many are independently developing reconfigurable CMOS PAs that can withstand past, present, and future modulation schemes and frequency bands. There are several common approaches to increasing the versatility of PAs: using parallel PAs with switches (current industry s solution), single power cell combined with multiple, parallel matching networks and switches, using tunable matching networks, and using wide-band power amplifiers that simultaneously cover all bands of interest. Using a single power cell with multiple matching networks is not much more efficient than using multiple, parallel, power amplifiers and the power cell can be quite large. Also, the passive elements in a typical matching network are large and don t scale with technology. Another, potentially more serious problem with switchable matching networks is the loss introduced by the switches which directly reduces efficiency and the switch power handling capability. The overall area can be reduced by using a tunable matching network. By using tunable elements, most notably varactors, in the signal path can result in serious non-linear distortion. An alternative is to use broadband power amplifiers in order to cover multiple bands simultaneously. One popular method to obtain broadband operation is through the use of a distributed architecture. Distributed PAs, however, suffer from large area and relatively low efficiencies. Another approach is to use a broadband output matching network, synthesized with high order prototype filter but these are not compatible with some high-efficiency fully integrated PA architectures, namely class-f. In this project, a fully integrated CMOS power amplifier (PA) with reconfigurable harmonic termination that operates from 700 MHz to 1200 MHz is demonstrated. Magnetic tuning is used for the harmonic control and reconfigurability without introducing switches in the signal path. I-CIRCUIT DESIGN At the heart of the proposed reconfigurable class-f PA is a reconfigurable output matching network that allows the user to control the frequency at which the network presents a shortcircuit (for 2nd-harmonic termination) and an open-circuit (for 3rd-harmonic termination) over a wide range of frequencies. This is accomplished through the use of two high-order transformerbased resonators, as seen in Fig. 1. The input impedance of the 3f0 network shown in Fig. 1 can be expressed as: Z IN = sl 1 s2 M 2 sl 2 +1 sc 2 + Z LOAD (1)
C2 RFC k2 L2 f0,3f0 DC BLOCK Vb3 M4 C2f0 L1 Vb2 M3 k1 C1 RL Vb1 M2 L1f0 L2f0 CT2 RFIN Widband Input MN M1 2f0 Bias where M = k L 1 L 2 is the mutual inductance between inductors L 1 and L 2 with coupling coefficient k. Assuming that the load impedance is purely capacitive and Z LOAD = 1 sc 1, the input impedance is now: Z IN = s4 (L 1 C 1 C 2 k 2 C 1 C 2 L 1 2 )+s 2 (C 1 +C 2 )L 1 +1 sc 1 (s 2 L 2 C 2 +1) which has a pole at DC and a pair of complex conjugate poles located at: f p1 = 0 ; f p2,3 = ± j 2π 1 L 2 C 2 (3) and two real zeroes located at: f z1 = f 1 2 +f 2 2 f 4 1 +f 4 2 +f 2 1 f 2 2 (4k 2 2) 2(1 k 2 ) f z2 = f 1 2 +f 2 2 + f 4 1 +f 4 2 +f 2 1 f 2 2 (4k 2 2) 2(1 k 2 ) where f 1 = 1 2π L 1 C 1 and f 2 = 1 2π L 2 C 2. Fig. 1: Proposed Reconfigurable PA In the context of class-f PAs, and treating the network of Fig. 1 as an equivalent series resonator, the first zero, z1, should be placed at the fundamental frequency thereby allowing it to pass through to the load. The pair of complex conjugate poles can then be placed at the 3rd harmonic to present an open-circuit at that frequency. The remaining zero, z2, can be shown to be located at high frequencies, outside of the band of interest. As the value of C 2 is changed, the location of the pair of complex conjugate poles can be varied to accommodate a shift in the 3rd harmonic and track the fundamental at different frequencies. The control of the second harmonic is done using the 2f0 resonator with similar procedure as above to place a zero at the 2 nd harmonic at each fundamental frequency by tuning C 2. At the fundamental, this network should present an open circuit. A plot of the different poles and zeroes as a function of f 1 and f 2 at our desired fundamental and harmonics results in contours that can be used to find the component values. As seen in Fig. 1, a series voltage combining approach is used for the active device to allow higher supply while maintaining process allowed drop across each device terminals. (2) (4) (5)
II-TEST PLAN The proposed PA was fabricated in 130 nm CMOS process and occupies 1.5 mm x 1.5 mm as seen in Fig. 2. In order to verify the performance of the proposed, the fabricated die was first packaged in a 20-lead QFN package and mounted to a two metal layers FR4 printed circuit board (PCB). All measurements are referred to the package pins with 4.8 V power supply voltage setting. A measurement bench is built as shown in Fig. 3 to evaluate our PA. A more detailed semi block diagram shown in Fig. 4 was used in large signal characterization. The E4418B power meter can measure power level from -70 dbm to +20 dbm. Our designed PA however will generate power above +20 dbm. Hence the use of a 20 db attenuator between the DUT (device Under Test) output port and the power sensor. It was de-embedded with any cable loss from our results. As far as small signal test bench is concerned, the Agilent E5071C Network analyzer was use with dc power supplies as shown in Fig. 4. A 10 db attenuator was used to protect the network analyzer and operate below maximum operation range. III-MEASUREMENT RESULTS The small signal and large signal measurement results are shown in Fig. 6 and Fig. 7 respectively for the PA configured to operate at 700 MHz, 900 MHz and 1200 MHz. In Fig. 6 the 1.5 mm 1.5 mm Fig.2: Die photo Fig. 3: Measurement bench setup Matlab Instrument Control GPIB Cables Matlab Instrument Control GPIB Cables E4438C VSG GPIB Cable DC Supplies & Digital Multi- Meters E4418B Power Meter E5071C Network analyzer DC Supplies & Digital Multi- Meters Packaged PA Die 20 db Attenuator Packaged PA Die Evaluation Board 10 db Attenuator Evaluation Board Fig. 4: Simplified setup for large signal Fig. 5 Simplified bench setup for small signal
Magnitude (db) 20 10 0-10 -20 f0 @ 700 MHz f0 @ 900 MHz f0 @ 1200 MHz 2f0 @ 700 MHz 2f0 @ 900 MHz 3f0 @ 700 MHz 2f0 @ 1200 MHz S 21 700 MHz S 21 900 MHz S 21 1200 MHz Magnitude (db) 0-5 -10 S 11 700 MHz S 11 900 MHz S 11 1200 MHz -30 3f0 @ 900 MHz 3f0 @ 1200 MHz 0 1 2 3 4 5 Frequency (GHz) -15 0 1 2 3 4 5 Frequency (GHz) Fig. 6: Measured small signal performance gain S21 and return loss S11 Fig. 7: Measured large signal performance Gain and PAE at 700 MHz, 900 MHz and 1200 MHz measure small signal gain show the reconfigurability of the harmonics fairly well with input return loss of -10 db or better across the entire tuning range. A maximum peak PAE of 48.3/43/30%, a saturated output power of 24.6/24/20 dbm and an overall power gain of 16.5/16/14.5 db were measured at 700/900/1200 MHz respectively as seen in Fig. 7. We saw a slight shift at 1200 MHz in the small signal performance which impacted large signal gain and efficiency. This was investigated and we determined that the magnitude of the tuning capacitance at 1200 MHz is comparable to its parasitic and cause a shift in the location of the second and third harmonic. In addition to this, a package capacitance to ground at the output also contributed to the deviation seen. SUMMARY A transformer-based 700 1200 MHz class-f PA with reconfigurable harmonic termination is proposed and fabricated in standard 0.13µm CMOS. We have shown that the proposed harmonic tunable output matching network provides a means for realizing high output power and efficiency over a wide bandwidth. The measured results agree fairly well with the simulation result at 700 MHz and 900 MHz with slight shift at 1200 MHz.
DESIGN 2 A POWER EFFICIENT, PVT ROBUST CONDUCTANCE CANCELLATION METHOD FOR GAIN ENHANCEMENT Prepared By: Bin Huang (Grad Student) and Degang Chen (Professor) Institution: Department of Electrical and Computer Engineering, Iowa State University Project Description: In a deep submicron process, due to the fact that transistors intrinsic gain is typically about 20-30dB, the DC gain of the cascode version, ranging between 40-60dB, is insufficient for many high precision applications such as sigma-delta convertors. In order to achieve a high DC gain, various techniques have been proposed including cascading of multiple gain stages, gain-boosting and gds cancellation. However, cascading of multiple stages seriously degrades an amplifier s frequency response due to complex compensation, while gain-boosting usually introduces pole-zero doublets and affects an amplifier s settling performance, especially for high accurate settling. In order to achieve high DC gain without having above issues, this work proposes a power efficient, process voltage and temperature (PVT) robust conductance (gds) cancellation method. Compared with traditional gds cancellation method, the new method offers several advantages. First, the new method involves only a single side, the PMOS or NMOS side, of the cascode structure. Therefore, the method can be implemented for both the PMOS and NMOS sides simultaneously and independently so as to achieve gds cancellation for both sides and then a large DC gain boost. Second, on each side, a negative conductance rather than a negative transconductance is generated to cancel a positive conductance. The generated negative conductance can effectively track and cancel the positive conductance to be cancelled under wide temperature variation. As a result, the proposed method doesn t need a calibration or tuning circuit and thus can decrease the design complexity, power consumption overhead and human interference for the calibration work. Third, the method senses signals from cascode nodes which inherently have very small voltage swing instead of from output nodes. Consequently, the DC gain enhancement provided by the method can be predicted accurately by small-signal model and is scarcely affected by amplifiers output voltage swing. The target of this method is to obtain at least 25dB DC gain enhancement with less than 4% power consumption overhead. A design example of a two-stage single ended amplifier with the proposed method is shown in Fig. 1. The chip of the design example is shown in Fig. 2.
Vdd M9 M8 8 M7 V b1 V b2 Vcmfb M0 V in- M1 M2 4 G M3 M4 V in+ 1 V b3 M16 M17 3 M12 V b3 V b2 D M14 2 V o1- M15 6 M13 M18 Cc V o M21 M22 7 M23 V b3 5 NMOS -g ds generator M5 M6 Current mirror input stage M10 Vss M11 Cascode stack M19 M20 Output stage Fig. 1: Design example with the proposed method V b4 M24 PMOS -g ds generator 88µm 164µm Measurement setup and results: Fig. 2: Layout and Microphotograph of the fabricated chip In order to measure the DC gain of the proposed op amp. The measurement is set up as shown in Fig. 3. Vc is set as a constant voltage within the input common mode range of the op amp. The open loop DC gain can be obtained as (1). In order to accurately measure the DC voltage at node A, B, C and D, 6-digit voltage meters are used. A OL = ΔV D ΔV C ΔV B (1)
6-bit voltage meter A 6-bit voltage meter 6-bit voltage meter 19.1K C Vos B - + 2pF 18.9K Op-Amp D 6-bit voltage meter Fig. 3: Test setup The measured DC gain of the two-stage single-ended op amps are shown in Fig. 4. The test result shows that the amount of DC gain enhancement is more than 26 db while op amps output voltage swings from 0.1V to 1.4V under the supply voltage of 1.5V. This shows the effectiveness of the proposed DC gain enhancement. 110 DC gain vs. Output voltage 100 Proposed Conventional DC gain (db) 90 80 >26dB 70 Major Findings: 60 0 0.5 1 1.5 Output voltge (V) Fig. 4: DC gain vs. Output voltage A high gain op amp is successfully realized with the proposed conductance cancellation method. The total area of the chip is 0.0144mm 2.
DESIGN 3 ANALOG MULTIPLEXER DESIGN Prepared By: Chongli Cai (Grad Student) and Degang Chen (Professor) Institution: Department of Electrical and Computer Engineering, Iowa State University Design Description This work focuses on the design of on-chip analog multiplexer (MUX). The design emphasizes on practically reducing the number of monitoring pin of a designed Operational Amplifier (Op Amp). The designed analog MUX internally connect with the required monitoring nodes of a designed Op amp, which can achieve the target of using only 1 pin to monitor 16 different internal signal. For these Op amps without analog MUX, each required monitoring node needs one pin to connect for off-chip testing, which always consumes a vast amount of pins on monitoring internal signals. The design uses Serial Peripheral Interface (SPI) bus to pump the digital data into the on-chip shift register array, and then decode by column decoder array to produce the corresponding internal monitoring signal address. A 16-to-1 analog MUX has been designed as shown in the figure 1. The proposed MUX mainly consists of five 4-to-1 analog MUXs together as two stages, and each 4-to-1 MUX consists of four identical analog MUX single cells. The analog MUX single cell contains one D- flip-flop (DFF) and one transmission gate (TG). By fabricating a set of this 16-to-1 analog MUX, the dynamic performance of the designed on-chip analog MUX can be easily measured, and we can directly apply it for monitoring the internal signal of the proposed amplifiers as well. FPGA (SPI Master) Clock Line Data Line Serial-in-parallel-out (SIPO) Shift Register Shift Register Array (SPI Slave) Off-chip Column Decoder 4-bit Column Decoder 4-bit 4-1 Mux 4-bit 16 Internal Monitoring inputs 4-1 Mux 4-bit 4-1 Mux oscilloscope Select Signal D Q Monitoring Signal output 4-1 Mux External Clock Signal Q' Single Analog Mux Cell 4 identical single analog mux cell 4-1 Mux 4-bit Off-chip Figure 1: The Structure of Proposed Analog Mux
On the chip, there is a designed single-ended Op Amp and a 16-to-1 analog mux. The chip pins are listed as shown in the table 1. The layout view of the fabricated chip is shown in the figure 2. Figure 2: Layout of the chip Table 1: Chip Pin Assignment Pin Data clk TP16 out bn0 bn5 en_n, en_p vdd!, vss! va2, va3 Ibias1 Vin+, Vin- Vout+ Vo1- Description Pins for 16-to-1 Analog Mux 1-bit input of the SIPO shift register array Clock signal for the SIPO shift register array Last analog mux input pin (used for providing external signal) Output pin of analog mux Pin for the designed single-ended Op Amp Digital tuning pins for the op amp (fixed the connection during test) Enable pins for the designed op-amp gds cancellation structure Power supply pins Two internal biasing or external forcing points Op-amp biasing current Op amp inputs Op amp output Op amp first stage output Test Setup and Measurement Result
The test set up block diagram is shown as Fig.3. The Altera DE2 FPGA board is used to provide clock signal and data for the on chip SIPO shift register array. Since the on-chip power supply is 1.5V and the FPGA s output is at 3.3V level, it requires a voltage translation between 3.3V FPGA output and 1.5V onchip voltage level. The dual-bit Dual-Supply Bus Transceiver with Configurable Voltage Translation SN74ACC2T45 is used to translate the 3.3V FPGA output to 1.5V on-chip voltage. en_n Altera DE2 FPGA board Data clk enp Vin+ TP16 Vin- Agilent E3631A DC Voltage Source On board connection out Vdd! Vss! va2 va3 Chip Vo1- Vout+ bn0 bn1 bn2 On board connection Ch2 Ibias1 bn3 Oscilloscope Ch1 Vo1+ bn4 PCB Board Figure 3: Block diagram of test set up According to the block diagram shown in the figure 3, the test-bench is set up as shown in the figure 4. The on chip supply voltage is 1.5V provided by Agilent E3631A DC voltage source. Another DC voltage source is used to provide the external signal for pin TP16. The oscilloscope Tektronix TDS3054 is used to plot the measured output DC voltage. In order to automatically carry out the measurement, the Verilog HDL code is written in the Quartus software to control the FPGA board.
Figure 4: test-bench for measurement The deigned PCB board used to perform this measurement is shown in the figure 5. The part in the orange box is te corresponding part used for testing the analog mux. The remaining part is used for testing the op amp on the same chip. Here is the part used for testing analog Figure 5: PCB board used for testing analog mux
According to the initial design purpose, this analog mux is designed to measure a DC biasing voltage, it is not required to operate at high frequency level. In the measurement, the clock used to pump data into shift register array is set to 10kHz because in the simulation we found that the DFF used in shift register cannot hold the data well when the clock frequency is higher than 1MHz. Initially, data 1111 is sequentially pumped into shift register array through 4 clock periods and after that the clock is set to high for holding the data at each output of the register. For this set of data, the expected output signal should be the input signal at pin TP16. The TP16 input signal is an external signal provided by DC voltage source Agilent E3631A and in this case it is set to 0.8V and the measured DC voltage by oscilloscope Tekironix TDS 3054 at output pin is 725mV as shown in the figure 5. The clock is also plot on the oscilloscope. Figure 6: Test Result for data '1111' Output DC voltage The measurement results shows that for monitoring the on-chip op-amp biasing voltage, the designed analog mux can accurately achieve the measurement in terms of saving on-chip pins. According to the measurement results, one thing needed to be improved is the ability of DFF in shift register for holding the digital signal because we found that when the clock signal is lower or higher than 10kHz much, there is some chance for the analog mux output getting floating. In the future op amp design, this analog mux will be used together with another purposed analog forcing circuit. By using the analog mux on chip, it can help to reduce a large number of pins, which means to save large chip area.