SOFIST ver.2 for the ILC vertex detector

SOFIST ver.2 for the ILC vertex detector Proposal of SOI sensor for ILC: SOFIST SOI sensor for Fine measurement of Space and Time Miho Yamada (KEK) IHEP Mini Workshop at IHEP Beĳing 2016/07/15

SOFIST ver.2 ARITOP_SOFIST2 Layout Chip size: 4.45 4.45 mm 2 Active area: 1.6 1.25 mm 2 (64 50 pixels) Time Stamp pixel: 50 50 pixels Analog pixel: 16 50 pixels Submitted in June 2016

Introduction SOFIST: Vertex detector (Inner most and 2nd layer) for the International Linear Collider experiment ILC Experiment: Precise measurement of the Higgs boson and search for BSM etc. Requirements: 1) Single point resolution: better than 3 μm 2) Time resolution: single-crossing (366 ns interval) time resolution 3) Low material budget: X 0.1 0.2 % X0 / Layer corresponds to ~ 100-200 μm Si, including supports, cables and cooling low-power ASICs (~ 50 mw/cm 2 ) + gas-flow cooling 4) Radiation hardness: TID : < 1 kgy / year NIEL: < 10 11 1MeV neq / cm 2 / year Focus on 1) and 2) for design of SOFST ver.2 for 3) Sensor will be thinned to 50 μm. However power and cooling of the chip do not study yet. for 4) TID will be resolving by double-soi (Univ. Tsukuba), high dose LDD (I. Karachi) and FN tunneling (M. Yamada). Ref.: ILC TDR v4 Detector LC Vertex / Tracking R&D 2nd Nov. 2015

Introduction Necessary functions for the ILC vertex detector: Single point resolution Pixel size: less than 25 μm Calculate weighted center of charges (Charges are spread among multi pixels). Record an analog signal of a hit Timing resolution Bunch crossing occurs every 366 ns in 1-msec-long bunch trains with an interval 200 ms. Identify a collision bunch of a hit to reconstruct a event. Record a time stamp of a hit. High speed data transfer Data have to be send to backend before next bunch train injection. Reduce a data to transfer. Ono, Shun, et al. "Development of a pixel sensor with fine space-time resolution based on SOI technology for the ILC vertex detector., Nucl. Instrum. Methods. Phys. Res. A, 2016.

Implemented functions in SOFIST ver.2 SOFIST ver.2 designed by S. Ono (KEK) In a Pixel - Pre-amplifier 0.6 V voltage swing (detect ~3 MIP) - Comparator Keep the analog signal and time stamp if a signal exceeds a threshold Vth. - Shift register Latch for two buffers. - Analog signal memory Store signal charges up to two hits. - Time stamp circuit Store time stamps up to two hits. On Chip - Column ADC (currently 8 bit) Digitize analog signal and time stamp. - Zero-Suppression logic Extract hit pixels and reduce the data to transfer to backend. Pixels for the analog memories (Analog pixel) and the time stamps (Time Stamp pixel) are separated to evaluate the functions individually.

Time Stamp Pixel designed by S. Ono (KEK) - Pre-amplifier Charge Sensitive Amp. - Comparator Chopper Inverter type - Shift register D-FF 1) Input a RAMP waveform. 2) Open a store switch (ST1) when a comparator changes to High. 3) Keep the voltage of RAMP to the analog memory (DMOS) as a time stamp. 4) in the same way for 2nd hit. Outside of the chip CMOS SW + DMOS (25 ff)

Analog Pixel designed by S. Ono (KEK) - Pre-amplifier Charge Sensitive Amp. - Comparator Chopper Inverter type - Shift register D-FF 1) Input a analog signal. 2) Open a store switch (ST1) when a comparator changes to High. 3) Keep the analog signal to the analog memory (DMOS). 4) in the same way for 2nd hit. NMOS SF CMOS SW + DMOS (25 ff) Implement all the functions of Time stamp pixel / Analog pixel in 25 25 μm 2 pixel.

Pixel Layout Unitized active merge and share contact to minimize an area of circuit. Ex. Comparator (Chopper Inverter Type) CMOS SW Inverter (S-Tie type 2) CMOS SW (Floating body type) MIM-cap 50 ff Inverter Active merge of S-Tie type 2 (L=0.5, W=1.0 μm) Active merge of Floating body type (L=0.2, W=0.5 μm) INV + COMP 6.06 3.01 μm

Pixel Layout Unitized active merge and share contact to minimize an area of circuit. Ex. Comparator (Chopper Inverter Type) D-FF (Floating body type) 11 MOSFETs are included. designed by Y. Arai 6.3 3.3 μm Used for Shift Register

Layout of Analog Pixel Pixel Size: 25 25 μm Wafer: Double-SOI, p-type substrate Time stamp pixel is the same layout but no NMOS SF. Comparator D-FF ( 2) NMOS SF CDS Pre-amp Analog memories ( 2) MET2-5 are not displayed.

Layout of Analog Pixel Pixel Size: 25 25 μm Wafer: Double-SOI, p-type substrate Comparator D-FF ( 2) The contact to DSOI is effective to shield interference between an analog and digital circuit etc. Pre-amp and Comparator Pre-amp and D-FF Comparator and D-FF D-FF and Analog memories CDS Pre-amp Analog memories ( 2)

Analog Pixel Transient analysis 1 μs 55 na, 10 ns ~3700 e Signal (Simulation) correspond to 1 MIP (50 μm) Pre.-amp (focus) 0.72 V Pre.-amp 0.3 V COMP 0.42 V DFF ST1 DFF ST2 Analog signal of 1st hit Analog signal of 2nd hit

Time Stamp Pixel Transient analysis 1 μs 55 na, 10 ns ~3700 e Signal (Simulation) correspond to 1 MIP (50 μm) Pre.-amp COMP RAMP DFF ST1 DFF ST2 Time stamp of 1st hit Time stamp of 2nd hit

For SOFIST ver.3 Implement two (or more) buffers for the analog signal and time stamp in a single pixel. Optimization of the pixel size and the circuit. 1) Remove 2nd capacitance of comparator and reset. 2) BPW size (12, 14, 16 μm) for evaluation of a noise and a charge collection efficiency. TEG are implemented in SOFIST ver.2 3) CMOS SW (for a reset, store and read) NMOS 1 Tr + level shifter? (ref: boot strap circuit for DRAM) Layout of CMOS SW itself is small (2.6 x 1.8 μm), however there are two contact (gate poly) and we have to input RST and RST_X. We should decrease number of contact and global line for a small size pixel.

For SOFIST ver.3 Remove 2nd capacitance for the comparator (chopper inverter type). Currently there are three MIM-cap (50 ff, 5.77 x 5.77 μm) for the CDS and comparator. We have a possibility to remove 2nd capacitance that if the ktc nose is small. CMOS SW 2nd MIM-cap MIM-cap 1st MIM-cap Remove 2nd capacitance and reset (CMOS SW). This pixel is implemented as TEG in SOFIST ver.2 (Time stamp pixel) MIM-cap (CDS)

For SOFIST ver.3 Remove 2nd capacitance for comparator (chopper inverter type). Currently there are three MIM-cap (50 ff, 5.77 x 5.77 μm) for the CDS and comparator. We have a possibility to remove 2nd capacitor that if the ktc nose is small. CMOS SW 2nd RST CMOS SW MIM-cap 1st MIM-cap Remove 2nd capacitance and reset (CMOS SW). This pixel is implemented as TEG in SOFIST ver.2 (Time stamp pixel) MIM-cap (CDS)

For SOFIST ver.3 Variation of BPW size for evaluation of a noise and a charge collection efficiency (12, 14, 16 μm). 12 μm 14 μm 16 μm These pixels (Analog pixel) are implemented as TEG in SOFIST ver.2

For SOFIST ver.3 There are 8 CMOS SW (for a reset, store and read). CMOS SW itself is small (2.6 x 1.8 um), however there are two contact (gate poly) and we have to input RST and RST_X. We should decrease number of contact and global line for a small size pixel. RST RST_X RST and RST_X are input from outside of pixel. CMOS SW NMOS 1 Tr + level shifter? (ref: boot strap circuit for DRAM)

Summary We are developing prototype pixel detector SOFIST for the ILC experiment. SOFIST ver.2 has almost all necessary functions in a single pixel and on the chip. On simulation, the analog pixel and time stamp pixel are well working. Analog signals and time stamps are kept to DMOS respectively for store 1 and 2. Some TEGs are implemented in SOFIST ver.2 for study of a noise and charge collection efficiency. We do not study the occupancy yet. How much do we need the buffers for the analog memory? If we need multiple buffers (more than three? four?) for the analog signal and time stamp respectively, we have to consider solution e.g. 3D integration, new architecture etc.

Backup

Time Stamp Pixel

Analog Pixel

Pre-amplifier Cpara. ~0.7 ff DMOS 1 ff

Analog Memory DMOS 25 ff DMOS 25 ff

CSA Cf Pre. amp ~0.7 ff 5 ff 50 μm 1 MIP: 3667 e DMOS 4.2 ff PCell V = Q C 19 3667 1.6 10 = 5 10 15 =0.12 V Sense Node 3 MIP 0.6 V 1 MIP 0.2 V Cf = 3 ff 3 ff A-R-Tec