Data Sheet No. PD-S Features Floating channel designed for bootstrap operation Fully operational to +V Tolerant to negative transient voltage dv/dt immune Gate drive supply range from to 2V Undervoltage lockout 3.3V, V and V input logic compatible Cross-conduction prevention logic Internally set deadtime High side output in phase with input Shut down input turns off both channels Matched propagation delay for both channels Also available LEAD-FREE HALF-BRIDGE DRIVER Product Summary V OFFSET V max. I O +/- 3 ma / 2 ma V OUT - 2V t on/off (typ.) 8 & ns Deadtime (typ.) 2 ns Packages Description The IR2(S) are high voltage, high speed power MOSFET and IGBT drivers with dependent high and low side referenced output channels. Proprietary HVIC and latch immune CMOS technologies enable ruggedized monolithic construction. The logic input is compatible with standard CMOS or LSTTL output, down to 3.3V logic. The output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high side configuration which operates from to volts. Typical Connection 8 Lead SOIC IR2S up to V 8 Lead PDIP IR2 V CC V CC V B COM V S TO AD (Refer to Lead Assignment for correct pin configuration) This/These diagram(s) show electrical connections only. Please refer to our Application Notes and DesignTips for proper circuit board layout.
Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Symbol Definition Units V B High side floating absolute voltage -.3 2 V S High side floating supply offset voltage V B - 2 V B +.3 V High side floating output voltage V S -.3 V B +.3 V CC Low side and logic fixed supply voltage -.3 2 V Low side output voltage -.3 V CC +.3 V Logic input voltage ( & ) -.3 V CC +.3 dv s /dt Allowable offset supply voltage transient V/ns P D Rth JA Package power dissipation @ T A +2 C Thermal resistance, junction to ambient (8 lead PDIP) (8 lead PDIP). 2 (8 lead SOIC) (8 lead SOIC).2 W C/W T J Junction temperature T S Storage temperature - T L Lead temperature (soldering, seconds) 3 V C Recommended Operating Conditions The Input/Output logic timing diagram is shown in Figure. For proper operation the device should be used within the recommended conditions. The V S offset rating is tested with all supplies biased at V differential. Symbol Definition Units V B High side floating supply absolute voltage V S + V S + 2 V S High side floating supply offset voltage Note V High side floating output voltage V S V B V CC Low side and logic fixed supply voltage 2 V V Low side output voltage V CC V Logic input voltage ( & ) V CC T A Ambient temperature - 2 C Note : Logic operational for V S of - to +V. Logic state held for V S of -V to -V BS. (Please refer to the Design Tip DT9-3 for more details). 2
Dynamic Electrical Characteristics V BIAS (V CC, V BS ) = V, C L = pf and T A = 2 C unless otherwise specified. Symbol Definition Units Test Conditions ton Turn-on propagation delay 8 82 V S = V toff Turn-off propagation delay 22 V S = V tsd Shutdown propagation delay 22 tr Turn-on rise time tf Turn-off fall time 9 DT Deadtime, LS turn-off to HS turn-on & 2 HS turn-on to LS turn-off MT Delay matching, HS & LS turn-on/off ns Static Electrical Characteristics V BIAS (V CC, V BS ) = V and T A = 2 C unless otherwise specified. The V, V TH and I parameters are referenced to COM. The V O and I O parameters are referenced to COM and are applicable to the respective output leads: or. Symbol Definition Units Test Conditions V IH Logic () & Logic () input voltage 3 V CC = V to 2V V IL Logic () & Logic () input voltage.8 V CC = V to 2V V,TH+ input positive going threshold 3 V V CC = V to 2V V,TH- input negative going threshold.8 V CC = V to 2V V OH High level output voltage, V BIAS - V O I O = A V OL Low level output voltage, V O mv I O = A I LK Offset supply leakage current V B = V S = V I QBS Quiescent V BS supply current 3 V = V or V I QCC Quiescent V CC supply current 2 µa V = V or V I + Logic input bias current 3 V = V I - Logic input bias current V = V V CCUV+ V CC supply undervoltage positive going 8 8.9 9.8 threshold V CCUV- V CC supply undervoltage negative going. 8.2 9 V threshold I O+ Output high short circuit pulsed current 3 2 V O = V PW µs ma I O- Output low short circuit pulsed current 2 3 V O = V PW µs 3
Functional Block Diagram VB HV LEVEL SHIFT PULSE FILTER R S Q PULSE GEN VS DEAD TIME & SOT-THROUGH PREVENTION UV DETECT VCC COM Lead Definitions Symbol V B V S V CC COM Description Logic input for high and low side gate driver outputs ( and ), in phase with Logic input for shutdown High side floating supply High side gate drive output High side floating supply return Low side and logic fixed supply Low side gate drive output Low side return Lead Assignments V CC V B 8 V CC V B 8 2 2 3 V S 3 V S COM COM 8 Lead PDIP 8 Lead SOIC IR2 IR2S
() () % % ton t r toff tf 9% 9% % % Figure. Input/Output Timing Diagram Figure 2. Switching Time Waveform Definitions % % % t sd 9% 9% DT % DT 9% Figure 3. Shutdown Waveform Definitions % Figure. Deadtime Waveform Definitions () () % % % MT MT 9% Figure. Delay Matching Waveform Definitions
T u rn -O n D e lay Time (ns) 8 - -2 2 2 Figure A. Turn-On Time Turn-On Delay Time (ns) 8 2 8 2 Figure B. Turn-On Time vs Supply Voltage Turn-On Delay Time (ns) 8 2 8 2 8 2 Input Voltage (V) Turn-Off Delay Time (ns) 3 - -2 2 2 Figure C. Turn-On Time vs Input Voltage Figure A. Turn-Off Time Turn-Off Delay Time (ns) 3 Turn-Off Delay Time (ns 8 Typ 2 8 2 2 8 2 8 2 Input Voltage (V) Figure B. Turn-Off Time vs Supply Voltage Figure C. Turn-Off Time vs Input Voltage
Shutdown Delay Time (ns) 3 M ax. - -2 2 2 Shutdown Delay Time (ns) 3 2 8 2 Figure 8A. Shutdown Time Figure 8B. Shutdown Time vs Voltage Turn-On Rise Time (ns) 3 - -2 2 2 Turn-On Rise Time (ns) 3 2 8 2 Figure 9A. Turn-On Rise Time Figure 9B. Turn-On Rise Time vs Voltage Turn-Off Fall Time (ns) - -2 2 2 Turn-Off Fall Time (ns) M ax. 2 8 2 Figure A. Turn-Off Fall Time Figure B. Turn-Off Fall Time vs Voltage
Deadtime (ns) 8 Deadtime (ns) 8 M ax. - -2 2 2 2 8 2 Figure A. Deadtime Figure B. Deadtime vs Voltage 8 8 Input V olta g e (V ) 3 2 Input V oltage (V ) 3 2 - -2 2 2 2 8 2 Vcc Supply Voltage (V) Figure 2A. Logic "" () & Logic () & Inactive Input Voltage Figure 2B. Logic "" () & Logic () & Inactive Input Voltage vs Voltage 3.2 3.2 Input Voltage (V) 2...8 Input V oltage (V ) 2...8 - -2 2 2 Figure 3A. Logic "" () & Logic () & Active Input Voltage 2 8 2 Vcc Supply Voltage (V) Figure 3B. Logic "" () & Logic () & Active Input Voltage vs Voltage 8
High Level Output Voltage (V).8...2 - -2 2 2 High Level Output Voltage (V).8.. M ax..2 2 8 2 Vcc Supply Voltage (V) Figure A. High Level Output Figure B. High Level Output vs Voltage Low Level Output Voltage (V).8...2 - -2 2 2 Low Level Output Voltage (V).8...2 M ax. 2 8 2 Vcc Supply Voltage (V) Figure A. Low Level Output Figure B. Low level Output vs Voltage Offset Supply Leakage Current (µa) 3 - -2 2 2 Offset Supply Leakage Current (µa) 3 3 VB Boost Voltage (V) Figure A. Offset Supply Current Figure B. Offset Supply Current vs Voltage 9
VBS Supply Current (µa) 2 9 3 - -2 2 2 VBS Supply Current (µa) 2 9 3 2 8 2 VBS Floating Supply Voltage (V) Figure A. VBS Supply Current Figure B. VBS Supply Current vs Voltage Vcc Supply Current (µa) 3 - -2 2 2 Vcc Supply Current (µa) 3 2 8 2 Vcc Supply Voltage (V) Figure 8A. Vcc Supply Current Figure 8B. Vcc Supply Current vs Voltage 3 3 Logic Input Current (µa) 2 2 - -2 2 2 Logic Input Current (µa) 2 2 2 8 2 Vcc Supply Voltage (V) Figure 9A. Logic"" Input Current Figure 9B. Logic"" Input Current vs Voltage
Output Source Current (ma) Output Source Current (ma) Logic Input Current (µa) 3 2 - -2 2 2 Logic "" Input Current (ua) 3 2 2 8 2 VCC Supply Voltage (V) Figure 2A. Logic "" Input Current Figure 2B. Logic "" Input Current vs Voltage VCC UV Threshold +(V) 9 8 - -2 2 2 Figure 2A. Vcc Undervoltage Threshold(+) VCC UV Threshold - (V) 9 8 - -2 2 2 Figure 2B. Vcc Undervoltage Threshold(-) 3 3 - -2 2 2 Figure 22A. Output Source Current 2 8 2 Figure 22B. Output Source Current vs Voltage
Output Sink Current (ma) 3 - -2 2 2 Output Sink Current (ma) 3 2 8 2 Figure 23A. Output Sink Current Figure 23B. Output Sink Current vs Voltage Case Outlines 8 Lead PDIP - -33 (MS-AB) 2
A E X D 8 2 3 e B H.2 [.] A. [.2] 3X.2 [.] FOOTPRT 8X.2 [.28] 8X.8 [.] DIM C HES MILLIMETERS M MAX M MAX A A.32..88.98.3...2 b.3.2.33. c..98.9.2 D E.89.9.98..8 3.8.. e. BASIC.2 BASIC e.2 BASIC.3 BASIC H K L y.228.99..2.9. 8.8.2..2..2 8 e A C y K x 8X b A.2 [.] C A B. [.] 8X L 8X c NOTES:. DIMENSIONG & TOLERANCG PER ASME Y.M-99. 2. CONTROLLG DIMENSION: MILLIMETER 3. DIMENSIONS ARE SWN MILLIMETERS [CHES].. OUTLE CONFORMS TO JEDEC OUTLE MS-2AA. 8 Lead SOIC DIMENSION DOES NOT CLUDE MOLD PROTRUSIONS. MOLD PROTRUSIONS NOT TO EXCEED. [.]. DIMENSION DOES NOT CLUDE MOLD PROTRUSIONS. MOLD PROTRUSIONS NOT TO EXCEED.2 [.]. DIMENSION IS THE LENGTH OF LEAD FOR SOLDERG TO A SUBSTRATE. -2-2 (MS-2AA) 3
LEADFREE PART MARKG FORMATION Part number IRxxxxxx Date code YWW? IR logo Pin Identifier? MARKG CODE P Lead Free Released Non-Lead Free Released?XXXX Lot Code (Prod mode - digit SPN code) Assembly site code Per SCOP -2 ORDER FORMATION Basic Part (Non-Lead Free) 8-Lead PDIP IR2 order IR2 8-Lead SOIC IR2S order IR2S Leadfree Part 8-Lead PDIP IR2 order IR2PbF 8-Lead SOIC IR2S order IR2SPbF IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 92 Tel: (3) 22- This product has been qualified per industrial level Data and specifications subject to change without notice. /2/
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