Jn, B., & Yuan, X. (2017). Neutral ponts voltage balancng control of a four-level -type converter. In 2016 IEEE Energy Converson Congress and Exposton (ECCE 2016): Proceedngs of a meetng held 18-22 September 2016, Mlwaukee, Wsconsn, USA (pp. 4438-4445). Insttute of Electrcal and Electroncs Engneers (IEEE). https://do.org/10.1109/ecce.2016.7855286 Peer revewed verson Lnk to publshed verson (f avalable): 10.1109/ECCE.2016.7855286 Lnk to publcaton record n Explore Brstol Research PDF-document Ths s the author accepted manuscrpt (AAM). The fnal publshed verson (verson of record) s avalable onlne va IEEE at http://eeexplore.eee.org/document/7855286. Please refer to any applcable terms of use of the publsher. Unversty of Brstol - Explore Brstol Research General rghts Ths document s made avalable n accordance wth publsher polces. Please cte only the publshed verson usng the reference above. Full terms of use are avalable: http://www.brstol.ac.uk/pure/about/ebr-terms
Neutral Ponts Voltage Balancng Control of a Four-level π-type Converter Bosen Jn, Xbo Yuan Department of Electrcal and Electronc Engneerng The Unversty of Brstol Brstol, Unted Kngdom bosen.jn@brstol.ac.uk xbo.yuan@brstol.ac.uk Abstract In ths paper, a carrer-based modulaton method wth optmal zero-sequence sgnal njecton has been ntroduced to modulate a four-level π-type converter as well as regulate ts DC-lnk neutral ponts voltages. The two neutral ponts voltages can be well controlled wth a back-to-back confguraton even under hgh modulaton ndex and hgh power factor. A back-toback expermental system has been bult and tests under 300V have valdated ths control strategy. Keywords energy effcency and ndustral applcatons; power converters, control, and modelng I. INTRODUCTION Multlevel converters provde an effectve way to process voltages hgher than the ndvdual swtchng devce ratng through varous topologes. In ndustry, they are commonly used n medum voltage (3~33kV) hgh power applcatons. They are also recently consdered n low-voltage (200~460V) applcatons as an alternatve to the conventonal two-level converter [1]. Compared wth a two-level converter, to acheve equvalent output harmoncs, the swtchng frequency of multlevel converters can be kept low, thus reducng the swtchng losses and shrnkng the heatsnk sze. On the other hand, f operated at the same swtchng frequency, the flter sze of multlevel converters can be smaller. Ether way wll mprove the system power densty, whch s favoured n more electrc arcrafts, electrc/hybrd vehcles, solar or wnd power generaton, where converter power densty s an mportant factor. In addton, the swtchng loss of multlevel converters s generally lower than the two-level converter due to the use of lower voltage-ratng devces and lower swtchng voltage [2]. Ths means the effcency drops nsgnfcantly wth the ncrease of the swtchng frequency [3], whch provdes the possblty to further ncrease the swtchng frequency and acheve a hgher power densty system. The man concern of multlevel converters s the ncreased complexty regardng the crcut and control. Converter topologes that generate output voltages of more than three levels have been studed [4, 5]. An alternatve four-level π-type converter was ntroduced wth only sx swtchng devces per phase leg [6]. Ths topology does not need the clampng dodes or flyng capactors as requred n the dode neutral-pontclamped (NPC) converter or flyng capactor (FC) converter, whch smplfes the crcutry. The advantages of ths topologes have been detaled n [3, 6]. Smlar to other multlevel converter topologes, the four-level π-type converter also has the unbalanced neutral ponts voltages problem [7-9], and ths ssue wll cause system nstablty and affect the output harmoncs. Space vector modulaton (SVM) for normal fourlevel converters have been researched [4, 7, 10]. The advantage of SVM s t has the ablty to regulate the neutral ponts voltages through the selecton of redundant vectors. However, when SVM s used for a converter whch has more than four voltage levels, the selecton of voltage vectors, calculaton of the tme duraton of each vector and the arrangement of the sequence of each vector become very complcated and computatonally ntensve. Thus, the carrer-based modulaton can be seen as a better opton for multlevel converters. Wth the njecton of an approprate zero-sequence component nto the fundamental sgnals, the effect of the carrer-based modulaton wll not only be equvalent to SVM [11, 12] but smpler. Prevous papers regardng neutral ponts voltages balancng agree that the DC-lnk capactors voltages can only be balanced wth a back-to-back confguraton (rectfer + nverter) f the modulaton ndex and power factor s hgh [9, 10, 13, 14] for four-level or fve-level NPC converters. The neutral ponts voltage balancng control and experments based on coordnaton between rectfer and nverter swtchng angles have been presented [15, 16]. However, n a real case, the grd and load condtons can vary ndependently and t may not be practcal to set a fxed relatonshp between the rectfer and nverter, e.g. smlar modulaton ndexes at both sdes. In [9], an ndependent neutral pont voltage balancng control of the nverter and rectfer for a fve-level back-to-back converter has been proposed wthout expermental valdaton. Ths paper contnues the work n [6], and proposes a carrer-based modulaton control strategy, whch has the ablty to balance the neutral ponts voltage regardless the condtons of the rectfer or nverter, e.g. wth dfferent modulaton ndex and power factor, and smplfes the control complexty at the same tme. A back-to-back converter wth 300V DC-lnk voltage experment has valdated ths control strategy. II. CONVERTER STRUCTURE AND MODULATION Fg.1 shows the phase-leg structure of a four-level π-type converter. T1 and T6 need to wthstand the whole DC-lnk
voltage (3E). T3 and T4 are requred to hold 2/3 of the DC-lnk voltage (2E), and T2, T5 wll have to hold 1/3 of the DC-lnk voltage (E). A carrer-based modulaton scheme concept for ths topology s shown n Fg.2. The ntersecton of the modulaton wave and each carrer wave determnes the swtchng states of one par of the swtchng devces n a complementary manner. In practcal mplementaton, the comparson and modulaton can be smplfed by usng a sngle carrer wave and dvdng the modulaton wave nto three parts. perod, there re two parts relatng to the chargng process and two other parts relatng to the dschargng process for C2. In ths stuaton, the converter can automatcally balance ts neutral ponts voltages. Fg.4 shows ths phenomenon, and ndcates that the hgher the power factor, the harder the neutral ponts voltages can be balanced. C3 N 2 C 2 N1 C1 Fg.1. Four-level π-type converter phase-leg structure Fg.3. Currents flow through neutral ponts durng dfferent commutaton perods (a) N2 to nverter (b) nverter to N1 (c) nverter to N2 (d) N1 to nverter Fg.2. Carrer-based modulaton scheme for a four-level π-type converter Table I summarzes the swtchng states at dfferent voltage levels. TABLE I. SWITCHING STATES AND OUTPUT VOLTAGE LEVEL Devce Voltage level T1 T2 T3 T4 T5 T6 3E ON OFF ON OFF ON OFF 2E OFF ON ON OFF ON OFF E OFF ON OFF ON ON OFF 0 OFF ON OFF ON OFF ON (a) Power factor=1 III. NENTRAL POINTS VOLTAGES BALANCING CONTROL As a multlevel converter, the four-level π-type converter has the ssue of the neutral ponts voltage drft at ts DC-lnk sde. Fg.3 shows the condton of the currents flowng through neutral ponts durng dfferent commutaton perods. For a four-level π-type converter, the neutral ponts voltages are effected by the charge and dscharge stuaton of the mddle capactor (C2). When load power factor equals to 1, n one fundamental perod, C2 keeps dschargng. Thus, the voltage across C2 wll decrease to zero gradually and causes the converter neutral ponts voltages unbalancng. On the other hand, when load power factor equals to 0, n one fundamental (b) Power factor=0 Fg.4. Charge and dscharge condton of C2 Thus, a control method needs to be dentfed to adjust the currents flowng through the DC-lnk capactors especally the
ones flow through C2, whch can help to acheve the neutral ponts voltages balancng even at a hgh power factor condton. As the carrer-based modulaton s employed here to smplfy the modulaton process. Wth an approprate zerosequence sgnal njecton, the four-level π-type converter can be well modulated and the DC-lnk neutral ponts voltages can be balanced at the same tme. The reference voltage (modulaton sgnal) for the converter s composed of two parts: fundamental components (threephase snusodal waveforms) and a zero-sequence component as gven n (1). u t = u t + ct = abc (1) * () () (),, Where, u (t) s the reference voltage; u * (t) s the fundamental component; c(t) s the zero-sequence component. The fundamental components are obtaned from the output of the current control loop, whch are used to control the fundamental current of the converter to track the reference. The zero-sequence component can be adjusted and added to the three-phase fundamental components smultaneously to acheve neutral ponts voltages balancng. For the computatonal convenence, set the phase reference voltage normalzed wth 1/3 of the total DC-lnk voltage (e.g. E n Fg.1), then the per unt value of the phase reference voltage wth regard to the negatve DC-bus wll be n the range of 0~3. Therefore, the maxmum as well as the mnmum zerosequence component c(t) whch can be njected to the threephase fundamental sgnals can be expressed as capactor voltage. V dc s the DC-lnk voltage. C s the capactor value. Once an optmzed zero-sequence sgnal s selected, J can be mnmzed (deally reduced to zero) when the capactors voltages are regulated at the reference value of 1/3 of the total DC-lnk voltage. To smplgy control mplementaton, t s better to calculate the dervatve of (4) as shown n (5). When capactor energy s mnmzed, the value of (5) becomes negatve. dj 3 dv 3 cj = C Δ vcj = ΔvCjCj 0 (5) dt j= 1 dt j= 1 Where, Cj s the current flowng through the capactor C j as shown n Fg.1. Therefore, the control objectve can be set as n (6) and the control varable s the zero-sequence component wth the defned range n (2). 3 3 Vdc mn V = Δ vcjcj = ( vcj ) Cj j= 1 j= 1 3 * * Constrant : umn ( t) c( t) 3 umax ( t) The next step s to fnd out the relatonshp between the control objectve and zero-sequence sgnal so that each zerosequence sgnal can be evaluated aganst the control objectve. The relatonshp between capactor current Cj n (6) and the neutral pont currents N1, N2 can be derved accordng to Fg.5. (6) u () t c() t 3 u () t (2) * * mn max Where, u * max and u * mn are the maxmum and mnmum value of the three-phase fundamental components and are gven by = C2 C3 ΔV N1 * * * * umn () t = mn( ua(), t ub(), t uc()) t * * * * umax () t = max( ua(), t ub(), t uc()) t After the avalable range of zero-sequence sgnal s derved by (2), the optmzed zero-sequence sgnal can be selected from t. Although the optmzed zero-sequence sgnal for neutral ponts voltages balancng target may be derved analytcally, samplng several values wthn the gven range could be a smpler way. For example, ten values can be selected equally wthn the range n (2) and evaluated aganst the control objectve. The one whch leads to the optmzed value of the control objectve wll be selected. In order to balance the DClnk capactors voltages, the control objectve can be set to mnmze the capactor s energy as gven n (4) [9, 10, 14, 18]. (3) C1 C3 = C1 C2 ΔV (a) Currents flowng through N1 ΔV ΔV N 2 1 3 3 2 1 Vdc 2 J = C Δ vcj = C ( vcj ) (4) 2 j= 1 2 j= 1 3 Where Δv Cj s the voltage devaton of capactor C j n Fg.1 from 1/3 of the total DC-lnk voltage. v Cj s the ndvdual (b) Current flowng through N2 Fg.5. Transents durng currents flowng through neutral ponts For the transent state n Fg.5 (a), when the current flows through N1, assume the voltage change on C1 s equal to the
voltage change on C2 and C3. Whle for the transent state n Fg.5 (b), when the current flows through N2, assume the voltage change on C3 s equal to the voltage change on C1 and C2. Therefore, the relatonshp can be derved as 1 2 = 3 3 1 1 nverter = + 3 3 2 1 = + 3 3 C1 N2 N1 C2 N2 N1 C3 N2 N1 1 2 C1 = N2 + N1 3 3 1 1 rectfer C2 = N2 N1 3 3 2 1 = 3 3 C3 N2 N1 Snce the reference voltage has been normalzed wthn the range of 0~3, the nteger part of the voltage reference (u ) represents the voltage level and the fractonal part determnes the duty cycle. Ths sgnfcantly smplfes the calculaton to fnd out the relatonshp between neutral ponts currents, modulaton sgnal and phase current. For example, f the reference voltage s 1.2, t means the voltage level s 1 and duty cycle s 0.2. Therefore, the output voltage wll swtch between E and 2E. Specfcally, the output voltage wll be E for 80% of the swtchng perod wth swtches T4 and T5 ON, where the phase output current flows through N1. The output voltage wll be 2E for 20% of the swtchng perod wth swtches T2 and T3 ON, where the phase current flows through N2. Therefore, the neutral currents ( N1, N2 ) can be determned by the reference voltage level (nteger part of the reference voltage) and the duty cycle (fractonal part of the reference voltage). The llustraton of the voltage level and duty cycle wth regards to the nteger and fractonal part of the reference voltage s shown n Fg.6. Fg.6. Illustraton of the reference voltage level and duty cycle The reference voltage u can be adjusted by the zerosequence component, whch gves the reason the zero-sequence component can affect the neutral paths currents, the correspondng capactor currents and the control objectve n (6). The relatonshp between the neutral pont current and the reference voltage (ncludng zero-sequence voltage) can be formulated as n (8) [12, 19, 20]. (7) [(nt( ) 0) frac( ) (nt( ) 1) (1 frac( ))] (8) [(nt( ) 1) frac( ) (nt( ) 2) (1 frac( ))] = u == u + u == u = u == u + u == u N1 = abc,, N2 = a, b, c Where, nt(u ) represents the nteger part (voltage level) of the reference voltage and frac(u ) represents the fractonal part (duty cycle) of the reference voltage. a, b, c are the converter phase currents. nt(u )==0 s used to check whether the reference voltage level s 0 or not. If t s zero, then (nt(u )==0) equals to 1, otherwse 0. It can be seen that only when the voltage level s 0 or 1, the phase current may flow through N1. When the voltage level s 1 or 2, the phase current may flow through N2. And the amount of current flows through the neutral ponts wll be determned by duty cycle. Wth (1)-(8), the relatonshp between the control objectve and the zero-sequence sgnal can be establshed. In summary, the modulaton and neutral ponts voltages balancng algorthm can be mplemented as follows. Frst, the threephase fundamental components are obtaned from the current control loop. Second, usng (2), the range of zero-sequence component can be derved. Thrd, equally sample several values wthn the range of the zero-sequence component, and add to the fundamental component to obtan the reference voltage. Fourth, usng (8), (7) to check whch zero-sequence component leads to the mnmum value of the objectve functon n (6). That zero-sequence component wll be selected to form the fnal reference voltage. After the reference voltage s obtaned, t wll be compared wth three trangle carrer-sgnals to generate the approprate PWM sgnals to the devces gate drvers. The algorthm flow chart n Fg.7 s able to present ths control strategy ntutvely. Current Control Loop Sample from the specfc range * * u () t c() t 3 u () t mn Fundamental Component u t * () Modulaton Sgnal * u () t = u () t + c() t PWM max N = abc,, N Zero-sequence Component ct () Relatonshp between neutral pont current and modulaton sgnal = frac( u ) Relatonshp between capactors currents and neutral ponts currents = a + b Cj j N2 j N1 Cj 3 Vdc ( vcj ) Cj < 0 j= 1 3 YES Fnal Modulaton Sgnal ut () Fg.7. Neutral ponts voltages balancng algorthm It should be noted that although the above algorthm attempts balance the voltage on each DC-lnk capactor, the neutral ponts voltages balancng can only be achevable f the modulaton ndex s lmted to about 0.6 wth the load power factor s lmted to 0.8 [8]. From the pont of vew of SVM, the NO
best DC-lnk capactors voltages balancng qualty can be acheved when there s no restrcton for the selecton of the redundant vectors. When the modulaton ndces are of hgh values, fewer redundant swtchng vectors are avalable for the neutral ponts voltages balancng actvtes [7, 10]. Meanwhle, from the carrer based modulaton pont of vew, hgher modulaton ndces sgnfes a smaller range of the zerosequence components can be selected. If the hgh modulaton ndex and hgh power factor are requred, a back-to-back confguraton should be establshed as n Fg.8. Wth a back-toback confguraton, the unbalance tendences of both sdes have a potental to compensate each other because of the symmetry of the system. Wth proper control strategy, the net current flowng nto each neutral pont durng each fundamental perod can be controlled as closed to zero as possble, the current and power flowng through the neutral ponts (N1 and N2) can be coordnated, therefore acheve the neutral ponts voltages balancng [8]. Lne voltage (V) Phase voltage (V) Lne voltage (V) 500 0-500 0 0.02 0.04 0.06 0.08 0.1 600 400 200 0 0 0.02 0.04 0.06 0.08 0.1 Tme (s) (a) Rectfer output lne and phase voltage 500 0-500 Fg.8. Schematc of a back-to-back four-level π-type converter IV. SIMULATION RESULTS A smulaton system has been establshed n MATLAB/Smulnk accordng to the confguraton n Fg.8. In order to present the capactors voltages balancng ablty of ths control strategy, the dfferent modulaton ndces stuaton has been presented here. The nput grd sde RMS lne voltage s 342V. The DC-lnk voltage s controlled to be 650V. Ths gves modulaton ndex of 0.9 at the rectfer sde. The load sde RMS lne voltage s 187V, whch means the nverter sde modulaton ndex s 0.55. The rectfer sde choke set s R=0.1Ω, L=5mH, and the nverter sde load s R=25Ω, L=1mH, whch means the power factors on both sdes are close to 1. The swtchng frequency s 10 khz. Fg.9 (a) shows the rectfer AC-sde lne voltage and phase voltage. The lne voltage has seven levels and phase voltage has four levels as expected. There are some dstnct pulses appearng n the phase voltage, whch s due to the njecton of the optmzed zero-sequence sgnals for the DClnk neutral ponts voltages balancng. These pulses do not affect the lne voltage as they can cancel out between phases. Fg.9 (b) shows the nverter output lne voltage and phase voltage. The lne voltage has fve levels and phase voltage has three levels as expected. Fg.9 (c) shows the voltage dstrbutons of the three DC-lnk capactors. They have been well regulated around 216V whch s a thrd of the total DClnk voltage of 650V. Phase voltage (V) Dc-lnk capactor voltages (V) 600 400 200 217 216 215 214 213 212 211 210 0 0 0.02 0.04 0.06 0.08 0.1 Tme (s) (b) Inverter output lne and phase voltage Upper capactor Mddle capactor Lower capactor 209 0 0.02 0.04 0.06 0.08 0.1 Tme (s) (c) Three DC-lnk capactors voltages Fg.9. Smulaton results wth a back-to-back four π-type converter V. EXPERIMENTAL RESULTS The devces n Table II are used to establsh the prototype for the test as shown n Fg.10. The converter prototype s desgned for an output of 5kW maxmum and allows the swtchng frequency to be set n a range from 5 khz to 50 khz wth a maxmum 900V DC-lnk voltage. It has been tested wth a 600V DC-lnk voltage and 3kW output power from 10 khz to 50 khz swtchng frequency for an nverter open loop test n [3]. For a back-to-back closed-loop neutral ponts voltages balancng test, two converter boards are requred and stacked. They are both controlled by a XC3S400 FPGA wth TMS320F28335 DSP control board.
TABLE II. SELECTED IGBT FOR THE CONVERTER PROTOTYPE Inverter Swtch Devce T1, T6 FGW15N120VD T2, T3, T4, T5 IKW30N60H3 Rectfer Fg.10. Expermental setup Control board Sensor boards Gate drver supply The test setup also ncluded a three phase 5mH nductve choke (equvalent resstance 0.2Ω) at the nput of the rectfer, a three-phase star-connected resstance-nductance load (R=44Ω, L=6.32mH) for the output of the nverter sde. Ths means the power factor on both sdes s close to 1. The DC-lnk voltage s set as 300V. Each DC-lnk capactor C=1000μF, thus the total equvalent DC-lnk capactance s 1333.33μF. The fundamental frequences and swtchng frequences on both sdes are 50 Hz and 10 khz, respectvely. Due to the rectfer sde s grd-connected, a Proportonal-Integral (PI) control based DC-lnk voltage loop and current loop are appled to the rectfer sde. An open loop voltage control s appled to the nverter sde. The proposed DC-lnk neutral ponts voltage balancng control s employed on both sdes. Set the modulaton ndex of rectfer m rec =0.9, and the modulaton ndex of nverter s m nv =0.9 as well. Usng an AD5725 DAC chp, the nternal varables n the code can be montored. The modulaton waveforms as well as the njected zero-sequence sgnal waveforms on both sdes can be montored through DAC and are shown n Fg.11 (a) (b). In order to get rd of the nose, the acquston mode used here s hgh resoluton mode. The yellow waveforms represent the fundamental components whch are snusodal. The blue waveforms are the selected the zero-sequence components through the method n Secton III, and ther frequences are trple of the ones of the fundamental components. The green waveforms are the fnal modulaton sgnals by addng prevous two waveforms together. Gven the complexty of the control algorthm, the control program processng s not nstant and requres the tme consumpton. To execute the code for one tme the actual perod s evaluated as 140μs. It has been shown n Fg.11 (c) by zoomng n the waveform n Fg.11 (a). Ths perod s stll larger than the actual swtchng perod whch s 100μs. Ths tme dfference wll reduce the rectfer sde voltage loop and current loop control bandwdth, and cause the control delay as t s grd connected. Ths wll cause the rectfer sde currents dstorton to some extent. Fg.11 (d) shows the rectfer output phase voltage as well as lne voltage. The phase voltage has four levels and the lne voltage has seven levels as expected. The nverter voltage waveforms n Fg.11 (f) have the same features as the rectfer sde ones have. Fg.11 (e) shows the three-phase rectfer AC sde currents. Because of the delay problem mentoned before, there s a bt low frequency dstorton n the rectfer currents waveforms. Fg. 11 (g) presents the nverter AC sde three phase snusodal currents. Fg.11 (h) shows the grd sde phase voltage as well as the grd sde current. As the rectfer power factor s close to 1, thus these two waveforms are n phase wth each other. Fg.11 () shows three DC-lnk capactors voltages. They are well balanced through ths control method. Due to the three voltage probes used are three dfferent types, the nose on the waveforms are dfferent. Fg.11 (j) presents these three DC-lnk capactors voltages more clearly by settng the offset n dfferent values. (a) Rectfer modulaton and zero-sequence sgnals (b) Inverter modulaton and zero-sequence sgnals
140µs (c) Actual tme perod of each AD samplng nterrupt (g) Inverter AC sde three-phase currents Vr_phase Vr_lne (d) Rectfer output phase and lne voltages Ir Vgrd (h) Grd voltage and current Ir_a Ir_b Ir_c (e) Rectfer AC sde three-phase currents () Three DC-lnk capactors voltages (f) Inverter output phase and lne voltages (j) Three DC-lnk capactors voltages when offset values are dfferent Fg.11. Expermental results of the equal modulaton ndces on both sdes
The condton of the dfferent modulaton ndces on each sde has been tested as well. Set the modulaton ndex of rectfer m rec =0.9, and modulaton ndex of nverter s m nv =0.6. In ths case, the rectfer sde lne voltage has seven levels whle the nverter sde lne voltage only has fve levels as shown n Fg.12 (a). Due to the nverter sde modulaton ndex s low, t can be deemed as a load sheddng condton. Therefore the total power s reduced. The power transfer on both sdes s equal, however the rectfer sde voltage s hgher than the nverter sde voltage, thus the rectfer current s lower than the nverter current n ths stuaton. Fg.12 (b) shows the three DC-lnk capactors voltages. They are also well regulated at 1/3 of the total DC-lnk voltage when the modulaton ndces on both sdes are dfferent. I Ir Vr_lne V_lne (a) Lne voltage and current waveforms on both sdes (b) DC-lnk capactors voltages Fg.12. Expermental results of the dfferent modulaton ndces on both sdes VI. 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