BITSPREADER - 2: A SOFTWARE CONFIGURABLE SPREAD SPECTRUM TRANSCEIVER Henrique C. Miranda,VictorM.G.Alves,Tânia C. S. Pinto and Sílvio A. Abrantes INESC Porto, Largo Mompilher, 22-45 Porto (Portugal) Tel.: +351 2 294243, Fax: +315 2 284172 E-mail: hmiranda@inescn.pt FEUP - Faculdade de Engenharia da Universidade do Porto Rua dos Bragas - 45 Porto, Portugal. Tel.: +351 2 28783, Fax: +351 2 287829 ABSTRACT A low-cost, software configurable, direct sequence spread spectrum transceiver based on a digital radio architecture is described and its implementation approach is addressed. The software definable parameters of the transceiver are presented, as well as several experimental results, namely, spectrum plots and error performance curves. Practical applications for this system are also foreseen. 1. INTRODUCTION Communication systems employing spread spectrum (SS) modulation are becoming very popular, mainly in the field of mobile telephony and wireless data communications (WLAN). With this modulation, multiple access techniques like CDMA (Code Division Multiple Access) become feasible and under certain conditions can lead to a more efficient use of the ever scarce radio-electric spectrum. Several air-interface standards have already been defined, being IS-95 and UMTS/IMT-2 (Universal Mobile Telecommunications Systems / International Mobile Telecommunications Systems - 2) the most important ones. In order to reduce the hardware investments to a minimum, the implementation of these communication systems should use very flexible radio hardware architectures that can be easily adapted to existing or forthcoming standards simply by changing its embedded software. These radio systems are generally termed software radios [1][2][3]. Recent advances in digital signal processors (DSPs) and Analog-to-Digital/Digital-to-Analog (ADC/DAC) converter technologies, including specialized VLSI circuits (e.g. digital downconverters and numerically controlled oscillators) have paved the way for the development of software radio systems using digitalization at the IF (Intermediate Frequency) or even at the RF (Radio Frequency) stages. The ultimate goal for a digital radio receiver is to directly digitize the RF signal at the antenna output and therefore implement all receiver functions in either digital hardware or software, although this later goal seems to be very difficult to attain for the time being. This is mainly due both to the lack of affordable very-high speed ADCs with adequate effective number of bits [4] and DSPs with enough computational power. This kind of radio architecture possesses important advantages when compared to its analog counterparts. The most relevant are: substantially better repeatability and stability (component aging and matching are no longer factors of performance limitation); implementation of signal processing functions that are unrealizable with analog hardware (for instance, FIR filters); hardware tweaking replaced by software tuning; design of cost-effective multifunction radios supporting different modulation types and bandwidths; potential reduction in product cost and development time. 2. SPREAD SPECTRUM TRANSCEIVER The system to be presented (henceforth called BitSpreader-2) is basically a low-cost, microprocessor controlled, Direct Sequence Spread Spectrum (DSSS)
Figure 1: BitSpreader-2 physical implementation. transmitter-receiver with software configurable parameters. The BitSpreader-2 is based on a digital radio architecture with digitalization at the IF stage, thus retaining the advantages stated above for this architecture. This transceiver was implemented in a two-layer printed circuit board and its image is shown in Figure 1. Its block diagram is depicted in Figure 2. Those building blocks are described and analyzed in the following subsections. 2.1. SPREAD SPECTRUM PROCESSOR A highly integrated SS processor - the Stanford Telecom s STEL-2A [5] - forms the main building block of this system. This device integrates functions of a differential BPSK/QPSK encoder, PN modulator (spreader), BPSK/QPSK modulator, digital downconverter (DDC), PN matched filter, differential PSK/QPSK demodulator and a complex numerically controlled oscillator (NCO) which is used as the local oscillator for the modulator and DDC. The receiver input is the analog-to-digital converted I.F. signal provided by an high speed ADC (AD9225 from Analog Devices [6]) and the transmitter output is a sampled, digitally modulated signal ready for external digital-to-analog conversion, feeding the AD978 DAC (from the Analog Devices TxDAC family [7]). The receiver clock rate must be at least four times the receiver PN spreading rate and is limited to a maximum speed of 2 MHz (for the version of the SS processor used). As a result, the maximum supported PN chip rate is 5 Mchip/s. Since PN modulation is symbol-synchronous in the STEL-2A (the PN code is aligned with the symbol transitions and repeats once per symbol), the data rate is defined by the PN chip rate and length of the PN code (N). Hence, for BPSK 5 modulation, the maximum data rate is N Mbit/s whereas for QPSK modulation the maximum data rate is 1 N Mbit/s. The STEL-2A receiver circuitry employs an NCO and complex multiplier referenced to the receiver clock rate to perform frequency downconversion, where the input I.F. sampling rate and the receiver clock rate must be identical. The input I.F. frequency is not limited by the capabilities of the STEL-2A. To avoid destructive aliasing, the NCO should not be programmed above 5% of the I.F. sampling rate. Higher I.F. frequencies, however, can be supported by programming the NCO to operate on in-band aliases as generated by the sampling process. An example regarding the utilization of these images will be presented in the next subsection. 2.2. SYNTHESIZED SAMPLING CLOCK GENERATOR A synthesized clock generator drives the SS processor and converters sampling clock inputs. This clock generator is based on a complete direct digital synthesizer, the AD985 [8] which is capable of generating clock signals of frequencies up to about 6 MHz. For this application, the usable range is 27 MHz, varied in steps of.2 Hz. This flexibility in the sampling frequency setting enables the transceiver to be configured for a wide range of IF frequencies, symbol rates and chip rates. The transmitter/receiver IFs can be programmed in the range of zero to approximately half of the sampling clock or in any of the other Nyquist regions 1 (by image filtering) as discussed in the following example. Assume that the transceiver is to be configured with the following set of parameters: symbol rate: R b = 192 baud; PN code sequence length: N = 64 chip/symbol; center IF frequency: f IF = 7. MHz. It is clear that the sampling frequency should be the highest possible (without overranging the maximum frequency specification of the SS processor - 2 MHz) in order for the intended image to be located in a low Nyquist region. Ideally, f IF should be placed in the center of a region in order to minimize the aliasing distortion. Moreover, the sampling frequency must be an integer multiple of the chip rate (1.288 Mchip/s in this example). Taking all the previous conditions into 1 ( The nth Nyquist region is defined as: n 2) ( 3 fs < f < n 2) 1 fs
PC or RS232 link text terminal In-system programmable microcontroller (89C51) Spread spectrum processor (STEL-2A) D/A A/D Tx IF filter Rx IF Filter RF subsystem SRAM memory (32 KByte) FEC processor (STEL-24) DDS clock generator (AD985) Figure 2: BitSpreader-2 block diagram. power spectrum density output image 3.728 14.724 18.432 55.296 59.24 7. 73.728 77.456 f (MHz) 22.16 which reduce the coding overhead at the expense of coding gain loss. It also incorporates a BER monitor, a programmable scrambler, supports up to 256 kbit/s data rates and presents a typical coding gain of 3.2 db @ BER= 1 5,rate 1 2, hard-decision decoding. 2R c Figure 3: IF output spectrum example. account, the best sampling frequency is 18.432 MHz, yielding the spectrum presented in Figure 3. One should note that the 7. MHz image will have itsspectruminvertedasitislayingonanevennyquist region (the 8th one). Although irrelevant for BPSK, the effect for QPSK will be the exchange of the inphase and quadrature channels (these can be reversed within the SS processor, thus eliminating this effect). The above discussion applies equally to the receiver IF frequency spectrum. 2.3. FORWARD ERROR CORRECTION CIRCUITRY In addition, forward error correction (FEC) is employed in order to enhance the Bit Error Rate (BER) performance of the system. The FEC chip utilized - the STEL-24 [9] - acts as a coprocessor, encoding the data frames to be processed by the STEL-2A and decoding the received ones, under the supervision of the system controller. The STEL-24 includes a convolutional encoder with a constraint length of 7 and a Viterbi decoder with three bit soft-decision capability (though not exploited because the SS processor demodulator only provides a hard-decision output). Apart from the 1 2 and 1 3 code rates, the 2 3 and 3 4 punctured rates are also supported 2.4. TRANSCEIVER SYSTEM CONTROLLER All the system parameters are configured by the embedded software running on the 89C51 microcontroller [1]. This microcontroller is of the in-system programmable type (ISP), making software upgrades a very easy task. This software also processes data frames that are received from and sent to the personal computer (PC). The communication between the user and the configuration software is made through an RS-232 link, using a simple text terminal or a serial communications program. The most relevant parameters that one can control are presented below: transmitter section: modulation type (BPSK or QPSK), data scrambler (for spectrum whitening), chip rate, symbol rate, PN code sequence (can be any sequence up to 64 chip); receiver section: modulation type, chip rate, symbol rate, PN code sequence, acquisition threshold, data descrambler; system clock section: sampling clock frequency and transmitter/receiver intermediate frequencies. There are more than thirty commands available to the user in configuration mode of the BitSpreader-2. These commands define or report the status of each parameter.
All the software was developed in ANSI C with some language extensions to support the architecture of this microcontroller. 2.5. TEST PORTS Additionally, there is a test port from which one can monitor the signal behavior (by the use of a logic analyzer, for example) at various stages of the transmitter and receiver signal processing chains. Examples of observable signals are the unspreaded symbols, the PN code sequence, the matched filter input and outputs and the NCO output. These are software selectable, too. A BER tester port is also included, providing the transmitter and receiver data lines and respective clock signals. An auxiliary sampling clock output is also present, used to monitor its frequency value. 3. EXPERIMENTAL RESULTS CENTER 5. MHz 2 KHz/div Tektronix 494P 1 2 3 4 5 6 7 8 1 db/div db RBW 1 KHz VBW 1 KHz SWP.5 s ATT 3 (a) unmodulated carrier CENTER 5. MHz 2 KHz/div Tektronix 494P 1 2 3 4 5 6 7 8 1 db/div db RBW 1 KHz VBW 1 KHz SWP 2 s ATT 3 1 2 3 4 5 6 7 CENTER 5. MHz 2 KHz/div Tektronix 494P 8 1 db/div ATT 3 db RBW 1 KHz VBW 1 KHz SWP 2 s 1 2 3 4 5 6 7 (b) PN sequence modulated CENTER 25. MHz 5 MHz/div Tektronix 494P 8 1 db/div ATT 3 db RBW 1 KHz VBW 3 Hz SWP 5 s This system has undergone several experimental tests yielding some interesting results. These tests were performed under the following transceiver settings: sampling frequency: 2. MHz intermediate frequency: f IF =5. MHz chip rate: R c = 333.3 kchip/s symbol rate: R b =1.8 kbit/s PN code sequence: 31 chip, m-sequence (generator polynomial: x 5 + x 2 +1) modulation: DPSK 3.1. SPECTRUM PLOTS The spectrum plots obtained are shown in Figure 4. As can be observed, the spectrum plots are fairly clean, with good signal-to-noise ratios (SNR>6 db). Plot (d) show the amplitude decay of the several images. Any of these images can be used as the transmitted IF signal, but the SNR will drop considerably for the higher order ones. 3.2. BIT ERROR RATE CURVES The error performance curves (presented in Figure 5) were evaluated for an AWGN channel (Additive White Gaussian Noise) and three PN code sequences were used: (c) data modulated (d) images spectrum Figure 4: Transmitter IF spectrum plots. 11-chip Barker code; 31-chip Gold Sequence; 63-chip m-sequence. Two different chip rates were settled for these tests: 333.3 kchip/s and 1.25 Mchip/s. As one could expect, the longer the length of the PN sequence (higher processing gain) the lower the bit error rate (the curves in each plot are shifted by approximately the ratio of the length of each PN sequence). For the higher chip rate test, the performance is reduced due to the fact that fewer samples per chip period are now processed by the receiver digital filters. 4. APPLICATIONS AND FURTHER WORK Several applications can be identified for this system to be used in: packet radio networks, data communications in electromagnetically harsh environments (like telemetry in industrial plants or mains data communications), as an education tool for teaching spread spectrum or applied signal processing to communications classes and wireless local area networks with multiuser access. Future developments include a full duplex communication mode, allowing TCP/IP data frames to be
Bit error rate Bit error rate 1 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 Error rate performance for 333 kcps Barker 11 Gold 31 M Sequence 63 15 12 9 6 3 3 6 9 12 Signal to noise ratio (db) (a) BER for 333 kchip/s Error rate performance for 1.25 Mcps Barker 11 Gold 31 M Sequence 63 15 12 9 6 3 3 6 9 12 Signal to noise (db) 5. REFERENCES [1] J. Mitola, The Software Radio Architecture, IEEE Communications Magazine, vol. 33, pp. 26 38, May 1995. [2] J. Mitola, Technical Challenges in the Globalization of Software Radio, IEEE Communications Magazine, vol. 37, pp. 84 89, Feb. 1999. [3] W. H. W. Tuttlebee, Software Radio Technology: A European Perspective, IEEE Communications Magazine, vol. 37, pp. 118 123, Feb. 1999. [4] R. H. Walden, Performance Trends for Analog-to- Digital Converters, IEEE Communications Magazine, vol. 37, pp. 96 11, Feb. 1999. [5] Stanford Telecommunications, Inc, STEL-2A - Digital, Fast Acquisition, Spread Spectrum Burst Processor, Nov. 1994. http://www.stelhq.com. [6] Analog Devices, Inc., AD9225 - Complete 12-Bit 25 MSPS Monolithic A/D Converter. Rev. A. http://www.analog.com. [7] Analog Devices, Inc., AD978-8-Bit, 1 MSPS+ TxDAC D/A Converter, 1996. Rev.. http://www.analog.com. [8] Analog Devices, Inc., CMOS, 125 MHz, Complete DDS Synthesizer, 1996. Rev.. http://www.analog.com. [9] Stanford Telecommunications, Inc, STEL-24 - Convolutional Encoder / Viterbi Decoder, Aug. 1993. http://www.stelhq.com. (b) BER for 1.25 Mchip/s Figure 5: Bit error rate performance for several PN sequences. transmitted and received. For that purpose the KISS protocol [11] is being implemented. Additional tests with activated forward error correction are currently undergoing. These will show the amount of coding gain offered by the system for various code rates. A suitable RF subsystem is also being designed to enable the system to be used in a real application. [1] Philips Semiconductors, 89C51RX+: In- System Programmable Microcontrollers, 1998. http://www.philips.com. [11] M. Chepponis and P. Karn, The KISS TNC: A simple Host-to-TNC communications protocol, July 199.