Buffered LABRADOR (BLAB3) Design Review Gary S. Varner 4 NOV 09
Baseline confirmation Goals for today Ice Radio Sampler (IRS) as sampling/storage array basis High rate/long latency architecture Review simulations Basic functionality Additional monitor/control features Flag action items (prior to submission) Anything missing? Target submission (26 OCT 09 delayed) [23 NOV 09]
BLAB3 Specifications 32768 samples/chan (>5us trig latency) 8 channels/blab3 ASIC 8 Trigger channels ~9 bits resolution (12[10]-bits logging) 64 samples convert window (~16ns) 4GSa/s 1 word (RAM) chan, sample readout 1+n*0.02 us to read n samples (of same 64) 30 khz sustained readout (multibuffer) Time alignment critical Synchronize sampling to accelerator RF clock >5us a must for trigger, since single photon rates high Needs Gain!
Gain Needed Amplifiers dominate board space Readout ASIC pair What gain needed? At 10 6 gain, each p.e. = 160 fc At 2x10 5 gain (better for aging), each p.e. = 32 fc In typical ~5ns pulse, Vpeak = dq/dt * R = 32uA * R = 32mV * R [kω] (6.4mV) Gain Estimate Rterm 1 p.e. peak 50 1mV 1k 20mV 20k 400mV
Starting place: IRS design 8 HS inputs 64 x 2 samples/ch 32k deep storage 64 sample select 8x64 Wilk ADC 12 output bits Random Access 10-bits Write Sel 10-bits Read Sel 3-bits channel 7-bits ADC ch 129 bonding pads 180um min pitch
BLAB3 Single Channel Sampling: 128 (2x 64) separate transfer lanes Recording in one set 64, transferring other ( ping-pong ) Storage: 64 x 512 (512 = 8 * 64) Wilkinson (32x2): 64 conv/channel
IRS Input Coupling Input Coupling versus total input Capacitance Input coupling versus frequency Analog Bandwidth [-3dB frequency] 3.5 3 2.5 2 1.5 1 0.5 0 0 C=15fF,Ron=1k R_S = 50Ohm -1 C=15fF,Ron=5k -2 C=25fF,Ron=1k -3 C=25fF,Ron=5k -4-5 -6-7 -8-9 -10 0 500 1000 1500 2000 2500 3000 0.1 1 10 100 Total input Capacitance [ff] Frequency [GHz] Input bandwidth depends on 2x terms f3db[input] = [2*π*Z*C tot ] -1 Relative amplitude [db] f3db[storage] = [2*π*R on *C store ] -1
IRS Input Coupling Input inductance impedance versus frequency Input coupling versus frequency Impedance [Ohms] 200 180 160 140 120 100 80 60 40 Bond-wire Bump-bond Relative amplitude [db] 10 8 6 4 2 0-2 -4-6 Bond-wire Bump-bond 20-8 0 0.1 1 10 100 Frequency [GHz] -10 0.1 1 10 100 Frequency [GHz] Role of inductance
Input coupling sim (35fF sample) Onto chip ~1 GHz analog bandwidth Into storage cell
Trans-Impedance Amp Basic building block have used before
3kΩ TIA Sim ~380MHz analog bandwidth
TIA timing simulation results Some overshoot a realistic current pulse?
Summary Plot ABW TIA Analog Bandwidth vs. Gain 450 400 350 Analog Bandwidth [MHz] 300 250 200 150 100 60x gain 100uA 50 0 1 10 100 TIA Gain [k-ohm]
Summary Plot ABW vs. Bias TIA Analog Bandwidth vs. Gain 500 450 400 Analog Bandwidth [MHz] 350 300 250 200 150 Saturates ~500uA 3k TIA 100 50 0 1 10 100 1000 10000 Bias Current [ua]
Simulated Noise Input noise Saturates ~500uA Output noise Noise integral from 100.00000K Hz to 1.00000G Hz Total integrated output noise voltage = 42.96911u V Total equivalent input noise voltage = 992.82668u V
Phase Response ~300MHz
Sample Cell Main element is buffer amp (OTA) Relatively low current (10 s ua) operation possible
Effect of too small a storage Cap Desire small C for better Input Coupling Cstore = 35fF
Storage Cell Diff. Pair as comparator Only power on selected block
Another Constraint: Leakage Current Need small C for Input Coupling Can Improve? (readout faster) Sample channel-channel variation ~ fa leakage typically
Sample transfer realistic capacitance <= 16ns settling 200Ω isolation resistor to reduce ringing
IRS Sampling Method Base delay
Simulated sampling speed Sampling Simulation with full parasitic Extraction 5.000 4.500 Extracted 4.000 3.500 Sampling Rate [GSa/s] 3.000 2.500 2.000 1.500 1.000 0.500 0.000 0 0.5 1 1.5 2 2.5 RCObias [V] RCObias VadjP1,2 = RCObias; VadjN1,2 = VDD-RCObias
Triggering Need 9 th channel for monitoring
Temperature Dependence Sample 6GSa/s aperature (172ps = 5.8GSa/s) 0.2%/degree C (can correct) Matches SPICE simulation
Triggering same as previous results Trigger 1-shot Width Adjust T_1_TRG Power (T_1_TRG) 100 Output Width [ns] 10 1 0 20 40 60 80 100 120 Discharge Current [ua] Monitor 9 th channel (uses Ch.1 threshold) to compensate for temperature dependence
Wilkinson ADC No missing codes Linearity as good as can make ramp Can bracket range of interest BLAB3 Digitization 12-bit ADC Run count during ramp Modified! (self-counter) [~0.7 GHz] Excellent linearity Basically as good as can make current source/comparator
Wilkinson Clock Generation Strictly only 5 channels necessary 4x antenna, 1x reference channels Could interleave for twice depth, or multiple reference channels
Wilkinson Recording Start = start 0.5-1.5GHz Clock Ripple counter (run as fast as can)
Wilkinson Clock Simulation Wilkinson Counter Rate Dependence 0.800 0.700 0.600 Wilkinson Clock [GHz] 0.500 0.400 0.300 Extracted 0.200 0.100 0.000 0 0.5 1 1.5 2 2.5 3 3.5 Vdly Control Voltage [Volts] Better than 500MHz of FPGA (and at lower power) 1GHz would be nice, but only 30% faster
Simulated transfer encoding Works as expected
Output Bus Settling Time ~8.5ns (10-90%) ~100MHz bus operation should be possible
Project# 80350 (BLAB3) Wirebonding diagram MOSIS ID NOTE: pads 33, 63, 64, 97, 98, 128 are NOT bonded Design_number: 80350 Customer name: Univ. of Hawaii Customer acct: 2105 Phone number: (808) 956-2987 Fax number: (808) 956-2930 Qty packaged: 0 Package name: LQFP128A Cavity size: 9.5mm x 9.5mm 9.5mm 7.62mm 5.82mm 9.5mm
Summary Leveraging IRS design effort ~0.4 GHz analog bandwidth All basic functionality simulates OK (with parasitics) Up to 100MHz bus readout rate (50MHz conservative) Am concerned about schedule Things will be much worse if doesn t work Could put in 128pin package Matters if will stud bond? Remaining concerns Optimal Write Address selection time Noise level on input Cost of stud bonding Others from today?
Upgraded detector -PID(π/Κ) detectors - Inside current calorimeter - Use less material and allow more tracking volume Available geometry defines form factor - Barrel PID Aerogel RICH 1.2m e - 8.0GeV 2.6m e + 3.5GeV
imaging TOP (itop) Concept: Use best of both TOP (timing) and DIRC and fit in Belle PID envelope Drawing by Marc Rosen(UH) BaBar DIRC Bars compatible (though thinner) with proposed TOP counter Use new, compact solid-state photon detectors, new high-density electronics Use simultaneous T, θc [measuredpredicted] for maximum K/π separation Keep pixel size comparable to DIRC
Proposed Common Approach for Belle2
Baseline image block Top View 2x 64-channel PMTs per fiber link 7x BLAB3 daughtercards (112x BLAB3) 896 PMT channels/module (16 itop staves) 7 data, 7 trigger fiber pairs + HV power, LVDS RF clock, Revolution marker pairs
Baseline System Components Giga-bit Fiber Photo- Sensor Photo- Sensor BLAB3 BLAB3 BLAB3 BLAB3 MCP MAIN x4 FINESSE CARD x4 COPPER FIFO BLAB3 is 8 channels, each 32k samples deep <~1us to read out 32-samples hit/blab3 Total channel numbers presented previously unchanged, partitioned slightly differently
Hit Processing reminder 8 BLAB3 ASIC Trans-Imp Amps 512 x 64 samples Per channel BLAB3 sampling Assume: 100kHz charged track hits on each bar ~32 p.e./track (1% of 100ns windows) 30kHz trigger rate Each PMT pair sees <8> hits 240k hits/s Each BLAB3 has an average occupancy <1 hit (assume 1) 400ns to convert 256 samples 16ns/sample to transfer At least 16 deep buffering (Markov overflow probability est. < 10-38 ) Fast conversion Matrix (x256) Improvements based upon Lessons learned from BLAB2 Each hit = 64samples * 8bits = 512bits ~125Mbits/s (link is 3.0 Gb/s ~ x30 margin) Plan to model in standard queuing simulator, but looks like no problem (CF have done same exercise with Jerry Va vra for 150kHz L1 of SuperB and can handle rate)
Context: BLAB2 & PD scale readout Initial Target: New f-dirc Readout System Really reached on specs Gen. 0 Prototype (LAB3)
BLAB2 Lessons RGC (Regulated Cascode) Fussy doesn t look like 50Ω for large voltage signals Not enough phase margin (oscillates) Sampling nmos/pmos does NOT work Alignment between sampling rows Overall timing alignment troublesome Better with fewer distinct samples, yet having more buffer depth
Experiment 2: 13-Mar-09 (~9 mo.) 448 channels readout at SLAC + few hundred UH [HI-TIDE] Learning about big system timing issues Experiment 3: winter (~6+ mo.) BLAB3 ASIC upgrade (lessons learned) At speed fast feature extraction
1kΩ TIA Sim ~405MHz analog bandwidth
2kΩ TIA Sim ~400MHz analog bandwidth
5kΩ TIA Sim ~350MHz analog bandwidth
10kΩ TIA Sim ~300MHz analog bandwidth
20kΩ TIA Sim ~245MHz analog bandwidth
50kΩ TIA Sim ~170MHz analog bandwidth
100kΩ TIA Sim ~130MHz analog bandwidth
3kΩ TIA, bias current sims ~130MHz analog bandwidth
3kΩ TIA, bias current sims ~200MHz analog bandwidth
3kΩ TIA, bias current sims ~300MHz analog bandwidth
3kΩ TIA, bias current sims ~370MHz analog bandwidth
3kΩ TIA, bias current sims ~420MHz analog bandwidth
3kΩ TIA, bias current sims ~450MHz analog bandwidth
3kΩ TIA, bias current sims ~450MHz analog bandwidth
3kΩ TIA, bias current sims ~450MHz analog bandwidth