Dedication To Mum and Dad
Acknowledgment
Table of Contents
List of Tables
List of Figures
A B A B 0 1 B A
List of Abbreviations
Abstract
Chapter1 1 Introduction 1.1. Motivation Figure 1. 1 The relative delay of the transistor, local, and global interconnect wires plotted versus process technology [1]
Figure 1. 2 Moore's gap; gap between the performance and the number of transistors
1.2. System in Package (SiP) Figure 1. 3 3D ICs multilayer connected TSV [7]
1.3. Parallel vs. Serial On-Chip Communication Driver Repeaters Buffers Core1 Core2 Figure 1. 4 Parallel based communication
1.4. Thesis Organization
Chapter 2 2 On-Chip SerDes Transceiver Architectures and Signaling Schemes 2.1. Introduction Driver TX Line Buffer Core1 Serializer Deserializer Core2 Figure 2. 1 Main functional blocks of SerDes transceiver; it consists of Serializer, driver at the transmitter and buffer, deserializer at the receiver
2.2. Signaling Schemes scheme 1 0 1 VDD scheme 2,DC 0 VDD/2VDD VDD/2 1 VDDVDD/2 VDD/2scheme 3 0 VDD/2 1 VDDVDD/2
CLK Data Encoded data Encoded data_bar Figure 2. 2 Scheme 1: conventional two-level signaling scheme CLK Data Encoded data Encoded data_ bar Figure 2. 3 Scheme 2: three-level DC preserving signaling scheme CLK Data Encoded data 2.3. Transmission Line Figure 2. 4 Scheme 3: three-level signaling scheme RC RLC RLC
RLC R LC Z 0 Z S Z L Figure 2. 5 Transmission line equivalent Z 0 = 1 + R L C tz (, ) = {(, ) } = 1 + = +
=, = 2 v = 1 VDD ws RLCZ 0 ws ws Figure 2. 6 Cross section of single ended transmission line Figure 2. 7 Cross section of differential ended transmission line
RC 2.3.2. Transmission Line Matching Techniques 2.3.2.1. Source Matching Technique ZsZ 0
DC DC 2.3.2.2. Resistive Termination Technique l = = + R L R L DCAC
= + DC 2.4. Proposed SerDes Transceiver Architectures 2.4.1. Scheme 1: Conventional Two-Level Code 6-8 Encoder Serializer Detector Deserializer 8-6 Decoder ADPLL (7GHz) Transmitter Receiver CDR (7GHz) Figure 2. 8 SerDes transceiver architecture scheme1
2.4.1.1. Encoder and Decoder 6 bits parallel data in 8 bits parallel data out Figure 2. 9 Proposed 6-8 encoder
2.4.1.2. Serializer Figure 2. 10 Conventional shift-register type Serializer [15]
DETFF: Double Edge Trigger Flip Flop FF: Flip Flop L: Latch M: MUX Figure 2. 11 Serializer block diagram 2.4.1.3. Deserializer FF: Flip Flop L: Latch Figure 2. 12 Deserializer block diagram
Figure 2. 13 Deserializer waveforms
2.4.1.4. Clock and Data Recovery (CDR) Figure 2. 14 Eye diagram of the data, the Y-axis is the voltage and the X-axis is the time frequency lock
F ref Data F DCO Frequency Loop Phase Loop frequency lock FL UP/DN MUX PL UP/DN VCO F DCO Figure 2. 15 Conventional charge pump based CDR
2.4.1.4.1. All Digital CDR Proposed Architecture frequency lock Data Bang-Bang PD Deserializer UP,DN UP[7:0] DN[7:0] FSM + fraction3 / 1 st Order Fine tune / 4 Fine tune / 1 DCO Fref Frequency Acquisition Binary Search Frequency Lock Z -1 Coarse tune integer Fine tune Thermometer / 5 Encoder 24 / / 4 Thermometer Encoder 15 / Figure 2. 16 Proposed CDR block diagram
UPDN UP/DN
2.4.1.4.2. Bang-Bang Phase Detector Figure 2. 17 Linear Phase Detector: Schematic and Transfer function [18] Figure 2. 18 Bang-Bang Phase Detector: Schematic and Transfer function [18]
S0 S1,S2 UPS1 S0DN S1S2 UP DN UPDN UPDN Figure 2. 19 Proposed half-rate BBPD In-phase clock Quadrature clock Clock leading Data Clock lagging Data Figure 2. 20 Data sampled by the clock at 3 states Table 2.1 Different states of clock and data are indicated by UP and DN signals UP DN State
2.4.1.4.3. Digital Controlled Oscillator (DCO) Figure 2. 21 DCO Figure 2. 22 DCO tuning curves
2.4.2. Scheme 2: Three-Level code with Constant DC DC V DD /2 Transmitter Ro Ro Differential Transmission Line Receiver Figure 2. 23 SerDes transceiver architecture for 3 level signaling preserving the DC level in scheme 2
2.4.2.1. Three-level Encoder and Driver VDD/2 VDD/2 VDD/2 FF: Flip Flop L: Latch M: MUX FF L Data XOR CLK M FF Driver FF L M FF Figure 2. 24 Scheme 2: Three-level Encoder and driver
Z s Z 0 Figure 2. 25 The encoder internal signals and the transmission line input/output signals 2.4.2.2. Transmission Line Design Z s Z 0 Z s Z 0
C H =54f C V =254f L=1.7 n R=40 Figure 2. 26 Scheme 2, source matching technique is used Figure 2. 27 cross section of differential transmission line and design parameters of scheme 2 RLC V C H CC v C H Z 0 v (1-e - ) (1-2e - )
Table 2.2 Design parameters of scheme 3 transmission line Parameter Symbol Value R L C sat Z 0 v t p 2.4.2.3. Decoder 0 AB 1 A in Low Switching Threshold A in V th in_bar V th 0 0 0 1 1 0 in_bar B A B Figure 2. 28 Low switching threshold inverters convert the three-level signals to two-level signal A and B Figure 2. 29 A and B are the output signals of the low switching threshold inverters; 0 represented by a pulse on A followed by a pulse on B, while 1 represented by a pulse on B followed by a pulse on A.
2.4.2.4. Phase Detector QAQB AQAB QBBA QAQB AB 0, BA 1 0 0 0 1 1 0 Q Q Q Volt Q Time Figure 2. 30 Phase Detector Figure 2. 31 Simple Phase detector extract the clock and recover the data
2.4.3. Scheme 3: Three-Level Code Ro Transmitter Single-ended Transmission Line Receiver Figure 2. 32 Scheme 3 SerDes transceiver architecture for 3 level signaling
2.4.3.1. Driver and Three-level Encoder VDD/2 clk Data Encoded data clk clk V dd clk Figure 2. 33 Scheme 3: Three-level Encoder and driver 2.4.3.2. Transmission Line Design Z o R L VDD/2
DC R LC V C H CC v C H C H =52.5fF C V =763.5fF L=1 nh R=18.2 Figure 2. 34 Scheme 3 transmission line termination resistance connected to VDD/2 source rather than ground Figure 2. 35 cross section of single ended transmission line Z 0 v R L
(mv) (mv) Figure 2. 36 Scheme 3, three-level code at the input and output of the transmission line Table 2.3 Design parameters of scheme 3 transmission line Parameter Symbol Value 2.4.3.3. Detector AB
SR Latch Figure 2. 37 Scheme 3 simple detector Figure 2. 38 Detector at the receiver detects the 3 level code, extract the clock and recover the data 2.5. Calibration Technique Applied to Scheme 2 and Scheme 3
Figure 2. 39 Calibrated low switching threshold inverter Figure 2. 40 Calibrated high switching threshold inverter
2.6. A Comparison between the Three Discussed Signaling Schemes Point of comparison Scheme 1 (conventional scheme) Scheme 2 (proposed scheme) Scheme 3 (proposed scheme) Signaling scheme Transmission Line Matching technique Limitation on minimum frequency Bulky building blocks Jitter effect on data reliability Detector calibration Driver size Maximum frequency of operation (GHz) Maximum data rate (GHz) Power Design complexity Area
2.7. Simulation Results 2.7.1. Scheme 2 Simulation Results (1-2e - )1-e - )=. Figure 2. 41 Eye diagram of the three-level code at the input of the transmission line Figure 2. 42 Eye diagram of the three-level code at the output of the transmission line Figure 2. 43 Eye diagram of the extracted clock from the phase detector Figure 2. 44 Eye diagram of the recovered data from the phase detector
Table 2. 4 Power Consumption of scheme 2 componnents in typical conditions prelayout Component Power (mw)
2.7.2. Scheme 3 Simulation Results Table 2. 5 Power Consumption of scheme 3 components in typical conditions Component Power (mw)
2.8. Layout Figure 2. 45 Serializer layout Figure 2. 46 Deserializer Layout
2.9. Design Comparison Table 2. 6 Design comparison of the proposed signaling techniques with other work in published literature This work Scheme 2 Scheme 3
3.1. Introduction Chapter 3 3 All Digital Phase Locked Loop V LPF = + V LPF F O V LPF K VCO
F ref V PD V LPF PD LPF VCO F out F div Divide by N Figure 3. 1 The conventional block diagram of PLL based frequency synthesizer = / = Acquisition Lock Time Acquisition Lock Range Jitter Phase noise
F Figure 3. 2 Jitter in time domain translated to phase noise in frequency domain Bandwidth Power Consumption Portability
3.2. Motivation for All Digital PLLs F ref PFD UP Dn I UP I DN Loop Filter V LF VCO F out F div Divide by N Figure 3. 3 Block diagram of charge pump based PLL
3.2.1. Analog PLL vs. Digital PLLs F ref V PD V LPF PD DLF DCO F out F div Divide by N Figure 3. 4 The block diagram of Digital PLL
3.2.2. Target Application Requirements Table 3.1 SerDes transceiver frequency synthesizer requirements Reference frequency (F ref ) Output frequency range Output frequency step Jitter Power & area
3.3. Bang-Bang ADPLL UP/DN UP/DN = F ref UP/DN BPD F div DLF D Prop bits Int bits 5 Z -1 4 DCO 1 Modulator 1 st order F out N Figure 3. 5 Block diagram of bang-bang ADPLL
3.3.1. Proposed BBADPLL Architecture frequency lock Frequency Acquisition Loop coarse bits_fl Frequency Locked Fine bits_fl5 1 4 F ref F div Phase Loop Fine bits_pl5 MUX 5 DCO F DCO N Figure 3. 6 Architecture of the proposed BBADPLL, it consists mainly of frequency acquisition loop and phase loop
3.3.2. BBADPLL Building Blocks N UP/DN UP/DN 5 D UP/DN Q 1 F div Frequency Detector Digital Loop Filter (DLF) coarse bits_fl Frequency Locked Fine bits_fl 5 Fine bits_pl 5 Fraction bits 4 1 MUX 4 5 Thermometer Encoder Modulator 1 st order coarse bits15 Fine bits Prop bits 3 bits 1 31 Digital Controlled Oscillator (DCO) F DCO N 5 Figure 3. 7 Detailed Block diagram of the proposed BBADPLL
3.3.3. Digital Controlled Oscillator (DCO)
Figure 3. 8 Block diagram of the proposed DCO Figure 3. 9 DCO cell schematic Figure 3. 10 Post-layout simulation results showing the output frequency curves for different coarse and fine words
= + + F out W Coarse W Fine K Coarse K Fine F o W Coarse 0W Fine 0 K Fine K fine 3.3.4. Frequency Acquisition Loop NFAST/SLOW
FAST/SLOW F DCO Count Counter Enable RST D Q N + - FAST/SLOW Binary Search State Machine Coarse Bits Fine Bits Frequency Locked F ref Control Signals Generation Sample_count Figure 3. 11 Block diagram of the frequency detector 3.3.4.1. Counter and Comparator
F ref Control Signals Generation Enable RST D D Q Q Enable_sync RST_sync F DCO Figure 3. 12 Frequency detector synchronizer used to resolve metastability, and reduce the period of undefined state. 3.3.4.2. Control Signals EnableRSTSample_Count EnableRST Enable 1 RST 0RST1 Enable Sample_Count F re
Table 3.2 Three states of the counter State Enable RST reset counting hold F ref Enable RST Counter status Count=0 Counting Hold Count=0 Counting Hold Sample_Count Comparator Count<N FAST/SLOW=1 Count>N FAST/SLOW=0 Figure 3. 13 Control signals of the counter; reset and enable signals, counter status and comparator output
3.3.4.3. Binary Search Finite State Machine F ref /3 S0 100010000 S1 S4S5 S9 Figure 3. 14 State machine of the binary search algorithm
3.3.5. Phase Loop 3.3.5.1. Phase Detector UP/DN UP/DN 1 D Q Figure 3. 15 (a) Single flip flop act as binary phase detector (b) Output transfer function of BPD 3.3.5.2. Frequency Divider N
D Q D Q D Q Figure 3. 16 Divide-by-five; frequency prescaler 3.3.5.3. Sigma Delta Modulator N: integer fine bits Figure 3. 17 DCO dithering by changing the fine bits at high rate
= + ( + 1) + = + + NT N NT N+1 N+1 F DCO X n CarryCarry_bit 0100 carry Z -1 Figure 3. 18 Block diagram of modulator, it consists of adder and D-FFs
¼ 01000110 Table 3.3 Example illustrates the operation of 1st order modulatorwith fractional bits =0100=1/4 n X n X n-1 carry/ _bit Table 3.4 Example illustrates the operation of 1st order modulatorwith fractional bits =0110=3/8 n X n X n-1 carry/ _bit F DCO 3.3.5.4. Digital Loop Filter (DLF)
F DIV F ref D DLF Z -1 Figure 3. 19 Block diagram of the digital loop filter UP/DN UP/DN DD
D D D 3.3.6. Proposed BBADPLL Model ref UP/DN div X prop X int r W fine Z -1 Figure 3. 20 BBADPLL Model t () = + () o
= 1 () N () = 1 () ( ) X prop X int 0 / = 0 = 1 / = 1 1 / = 0 = 1 / = 1 X prop X int TsF ref F ref () = () (1 ) () = + 1 r
() () = 2 () () () = 2. (1 ) + (1 ) [] = 2 ( [] [ 1]) + [] [ 2] + 2 [ 1] [] = [] [ 1] K fine K fine
Figure 3. 21 phase error transient response for coarse word=1 Figure 3. 22 jitter Figure 3. 23 Figure 3. 24
K fine K fine = D Figure 3. 25 The effect of changing (a) =0.25, (b) =1, (c) =2 D
D,DK Fine,D 3.4. Simulation Results
3.4.1. DCO Frequency Curves and The Equivalent Power Consumption TT, 1V, 125c SS, 0.9V, 125c FF, 1.1V, 0c Figure 3. 26 DCO output frequency curves and power consumption for different coarse and fine words across PVT
3.4.2. ADPLL Closed Loop Simulation Results s Figure 3. 27 Closed loop post layout simulations for BBADPLL,D Table 3. 5 The closed loop simulation results at 7.5 and 10GHz
3.5. Layout 3.5.1. Full Custom Blocks 3.5.1.1. Floor Plan DCO PMOS control bits Transistors Frequency Prescaler Divide by 5 Clock Buffer DCO 3 stages Ring oscillator inverter based DCO NMOS Control bits transistors Figure 3. 28 ADPLL Floorplan
3.5.1.2. DCO, Buffer and Prescaler Layout Figure 3. 29 DCO and divide-by-five full custom layout
3.5.2. Digital Blocks 3.5.2.1. Floor Plan Figure 3. 30 ADPLL digital blocks floor plan snapshot from SoC encounter
3.5.2.2. Layout Figure 3. 31 ADPLL digital blocks Layout
3.6. Design Comparison Table 3. 6 Design comparison of the proposed BBADPLL with other work in published literature This Work
4.1. Summary Chapter 4 4 Summary and Future Work
DC
VDD/2
4.2. Conclusion 4.3. Future Work
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