Panasonic DMC-GH1 12.1 Mp, 4.4 µm Pixel Size LiveMOS Image Sensor from Panasonic LUMIX DMC-GH1 Micro Four Thirds Digital Interchangeable Lens Camera Imager Process Review For comments, questions, or more information about this report, or for any additional technical needs concerning semiconductor and electronics technology, please call Sales at Chipworks. 3685 Richmond Road, Suite 500, Ottawa, ON K2H 5B7, Canada Tel: 613.829.0414 Fax: 613.829.0515 www.chipworks.com
Imager Process Review Some of the information is this report may be covered by patents, mask and/or copyright protection. This report should not be taken as an inducement to infringe on these rights. 2009 Chipworks Inc. This report is provided exclusively for the use of the purchasing organization. It can be freely copied and distributed within the purchasing organization, conditional upon the accompanying Chipworks accreditation remaining attached. Distribution of the entire report outside of the purchasing organization is strictly forbidden. The use of portions of the document for the support of the purchasing organization s corporate interest (e.g., licensing or marketing activities) is permitted, as defined by the fair use provisions of the copyright act. Accreditation to Chipworks must be attached to any portion of the reproduced information. IPR-0909-801 13865JMRK Revision 1.0 Published: October 30, 2009
Imager Process Review Table of Contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Company Profile 1.4 Introduction 1.5 Device Summary 1.6 Process Summary 2 Package and Die 2.1 Downstream Product and Package 2.2 Die 2.3 Die Features 3 Process 3.1 General Structure 3.2 Bond Pads 3.3 Dielectrics 3.4 Metals 3.5 Vias and Contacts 3.6 MOS Transistors, Poly, and Poly Capacitors 3.7 Isolation 3.8 Wells, Epi, and Substrate 4 Pixel Array Analysis 4.1 Pixel Schematic 4.2 Pixel Array Plan-View Analysis 4.3 Pixel Array Cross-Sectional Analysis 4.4 Color Filters and Microlenses 5 Critical Dimensions 5.1 Package and Die 5.2 Vertical Dimensions 5.3 Horizontal Dimensions 6 References 7 Statement of Measurement Uncertainty and Scope Variation About Chipworks
Overview 1-1 1 Overview 1.1 List of Figures 2 Package and Die 2.1.1 Panasonic DMC-GH1 DSLR Camera Body Front View 2.1.2 Panasonic DMC-GH1 DSLR Camera Body Back View 2.1.3 Panasonic DMC-GH1 DSLR Camera Body Top View 2.1.4 Panasonic DMC-GH1 DSLR Camera Body Bottom View 2.1.5 Inside Panasonic DMC-GH1 DSLR Camera 2.1.6 SSW Dust Filter Assembly 2.1.7 Camera Main Board with LiveMOS Sensor Module Removed Front Side 2.1.8 Camera Main Board with LiveMOS Sensor Module Removed Back Side 2.1.9 DMC-GH1 Image Sensor Assembly Front 2.1.10 DMC-GH1 Image Sensor Assembly Back 2.1.11 DMC-GH1 Package with Shield and IR Filter Removed Front 2.1.12 DMC-GH1 Package with Shield and IR Filter Removed Back 2.1.13 DMC-GH1 Image Sensor Package X-Ray Plan View Overview 2.1.14 DMC-GH1 Image Sensor package X-Ray Plan View Corner Detail 2.2.1 Die Photograph Organic Lenses and Filters Removed 2.2.2 Die Photograph Delayered to Poly Level 2.2.3 DMC-GH1 Annotated Metal 1 Die Photograph 2.2.4 Analysis Sites 2.3.1 Die Corner A Intact 2.3.2 Die Corner B Intact 2.3.3 Die Corner C Intact 2.3.4 Die Corner D Intact 2.3.5 Pixel Corner A Delayered to Metal 1 2.3.6 Pixel Corner D Delayered to Metal 1 Overview 2.3.7 Pixel Corner D Delayered to Metal 1 Detail 2.3.8 Minimum Pitch Bond Pads 2.3.9 NAND Cell 3 Process 3.1.1 Pixel Array General Structure 3.1.2 Peripheral General Structure 3.1.3 Die Edge Overview 3.1.4 Die Edge Detailed View 3.1.5 Die Seal Overview 3.2.1 Bond Pad Overview 3.2.2 Bond Pad Detailed View 3.2.3 Bond Pad Right Edge
Overview 1-2 3.3.1 Passivation and IMD 3 SEM 3.3.2 Passivation and IMD 3 TEM 3.3.3 ILD 2 and ILD 1 3.3.4 ILD 1 3.3.5 Transition Between Active and Active Test Pixels Passivation, IMD 3, and ILD 3.3.6 PMD in Periphery 3.3.7 PMD in Pixel Array SEM Cross Section 3.3.8 Pixel Array at Poly SEM Plan View 3.4.1 Minimum Pitch Metal 4 3.4.2 Detail of Metal 4 3.4.3 Minimum Pitch Metal 3 and Metal 1 Pixel Array 3.4.4 Minimum Pitch Metal 2 3.4.5 Minimum Pitch Metal 1 3.4.6 Detail of Metal 3 and Metal 2 3.4.7 Detail of Metal 1 3.5.1 Minimum Pitch Via 3s 3.5.2 Detail of Via 3s 3.5.3 Minimum Pitch Via 2s 3.5.4 Minimum Pitch Via 1s and Contacts to Poly and Diffusion 3.6.1 Minimum Gate Length MOS Transistor TEM 3.6.2 Logic Gate Dielectric TEM 3.6.3 Minimum Gate Length PMOS Transistor (Si Etch) 3.6.4 Logic NMOS (Si Etch) 3.6.5 Poly Capacitor 3.6.6 Contacts to Poly Capacitor 3.7.1 Minimum Width STI 3.7.2 Poly Over STI 3.8.1 SEM of Peripheral N-Well 3.8.2 N-epi and N-substrate SRP 3.8.3 Peripheral N-Well SRP 3.8.4 SCM of Peripheral Wells 3.8.5 Higher Magnification SCM of Peripheral P-Wells 3.8.6 Peripheral P-Well SRP 3.8.7 SRP in Pixel Array 4 Pixel Array Analysis 4.1.1 Active Pixel Schematic Circuit 4.1.2 Active and Dark Test Pixel Schematic Circuit A 4.1.3 Active and Dark Test Pixel Schematic Circuit B 4.2.1 Pixel Array Corner Optical 4.2.2 Pixel Array Color Filters 4.2.3 Pixel Array Corner at Metal 3 Overview 4.2.4 Pixel Array at Metal 3 Detail 4.2.5 Pixel Array Corner at Metal 2 Overview
Overview 1-3 4.2.6 Pixel at Metal 2 Detail 4.2.7 Pixel Array Corner at Metal 1 Overview 4.2.8 Pixel at Metal 1 Detail 4.2.9 Pixel at Poly 4.2.10 Pixel at Diffusion Detail 4.2.11 Pixel Array at Substrate 4.2.12 Pixel at Substrate SCM 4.3.1 Pixel at Poly Showing Cross-Sectional Planes 4.3.2 General Structure of Pixel (A) 4.3.3 Transfer Gate (T1/T2) and Pixel (B) 4.3.4 SCM of Pixel Array (B) 4.3.5 Details of Transfer Gate (T1/T2) and FD (B) 4.3.6 Detail of a Transfer Gate (B) 4.3.7 Transfer Gate Edge Over Photocathode TEM (B) 4.3.8 Transfer Gate Edge Over FD TEM (B) 4.3.9 FD Contact of Photocathode TEM (B) 4.3.10 Silicon Nitride AR Layer Stack 4.3.11 Pixel Array Gate Oxide TEM 4.3.12 Rest T3, Source Follower T4, and Row Select T5 Transistors Overview (C) 4.3.13 Rest T3 Transistor (C) 4.3.14 Source Follower T4 Transistor (C) 4.3.15 Row Select Transistor (C) 4.3.16 T3 Gate Width (D) 4.3.17 T4 Gate Width (E) 4.3.18 T5 Gate Width (F) 4.4.1 Pixel Array General Structure (Red-Green Filters) (A) 4.4.2 Pixel Array General Structure (Blue-Green Filters) (G) 4.4.3 Pixel at Array Right Edge (E) 4.4.4 Active to Active Test to Dark Test Pixels Transition Overview 4.4.5 Active to Active Test to Dark Test Pixels Transition Detail 4.4.6 Edge of Organic Spacer and Optical Pad Layers 4.4.7 Edge of Blue Filter 4.4.8 Organic Lens, Blue Color Filter, and Optical Pad Layer 4.4.9 Organic Layer Over Lens and Hemispherical Lens TEM 4.4.10 Green Color Filter 4.4.11 Red Color Filter 4.4.12 Green-Red Color Filter Interface TEM
Overview 1-4 1.2 List of Tables 1 Overview 1.4.1 Sample Markings 1.5.1 Device Summary 1.6.1 Summary of Major Findings 2 Package and Die 2.2.1 Functional Block Sizes 2.3.1 Die, Bond Pad, and Standard Cell Dimensions 3 Process 3.3.1 Dielectric Composition and Thicknesses 3.4.1 Metallization Composition and Thicknesses 3.4.2 Minimum Metal Horizontal Dimensions 3.5.1 Via and Contact Horizontal Dimensions 3.6.1 Transistor and Polysilicon Horizontal Dimensions 3.6.2 Transistor and Polysilicon Vertical Dimensions 3.7.1 Periphery and Pixel Array Isolation Critical Dimensions 3.8.1 Wells, Epi, and Die Vertical Dimensions 4 Pixel Array Analysis 4.2.1 Pixel Horizontal Dimensions 4.3.1 Pixel Vertical Dimensions 4.3.2 Transistor Dimensions in Pixel Array 4.4.1 Pixel Elemental Analysis 5 Critical Dimensions 5.1.1 Die, Bond Pad, and Standard Cell Dimensions 5.2.1 Dielectric Composition and Thicknesses 5.2.2 Metallization Composition and Thicknesses 5.2.3 Transistor and Polysilicon Vertical Dimensions 5.2.4 Wells, Epi, and Die Vertical Dimensions 5.2.5 Isolation Composition and Thicknesses 5.2.6 Pixel Vertical Dimensions 5.3.1 Minimum Metal Horizontal Dimensions 5.3.2 Via and Contact Horizontal Dimensions 5.3.3 Transistor and Polysilicon Horizontal Dimensions 5.3.4 Isolation Horizontal Dimensions 5.3.5 Pixel Horizontal Dimensions 5.3.6 Transistor Dimensions in Pixel Array