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A/D Conversion Theory Here, an example is shown for a 3-bit A/D converter. Four capacitors are used for a 3-bit A/D converter. An N-bit A/D converter is built using N+1 capacitors and an analog comparator. 2

A/D Conversion Theory (contd.) Sample Mode In this mode the bottom plates of the capacitors are connected to the unknown voltage V x and the top plates are connected to the lower reference voltage V L. 3

A/D Conversion Theory (contd.) Charge Stored During the Sample Mode The charge in all the capacitors, stored during the sample mode, can be computed as Q S = 8(V x - V L ). If we assume V L = 0, then Q S = 8V x. 4

A/D Conversion Theory (contd.) Hold Mode : In this mode the bottom plates are switched to V L. Since the charge is conserved, we still have the same amount of charge, i.e. Q S = 8(V L - V i ) = -8V i. From the previous slide we know that Q S = 8V x. Hence, V x = -V i. 5

A/D Conversion Theory (contd.) Conversion Mode : In this mode, each capacitor, beginning with the largest one, which corresponds to the most significant bit (MSB) of the digital result, is switched from V L to V H. 6

A/D Conversion Theory (contd.) Determine the MSB of Digital Output : Let s assume that, V X =3.2v, V H =5.0v and V L =0.0v. Our goal is to determine the digital output. Q S = 8V X = 8*3.2 = 25.6 If the largest capacitor is connected to V H then Q S = 4(V H - V i ) + 4(V L - V i ) = 4*5 8* V i = 25.6. Hence, V i = -0.7v. Since V i is negative, V out is logic-1, i.e. MSB = 1. 7

A/D Conversion Theory (contd.) Determine the Next Bit of Digital Output: Now the capacitor with value 2 is also switched to V H. This time, Q S = 6(V H - V i ) + 2(V L - V i ) = 6*5 8* V i = 25.6. Hence, V i = 0.55v. Since V i is positive, V out is logic-0, i.e. the next bit of digital output is a 0. 8

A/D Conversion Theory (contd.) Determine the LSB of Digital Output: Since the middle bit of digital output is a 0, the capacitor with value 2 will be switched back to V L and the capacitor with value 1 will be switched to V H. This time, Q S = 5(V H - V i ) + 3(V L - V i ) = 5*5 8* V i = 25.6. Hence, V i = -0.075v. Since V i is negative, LSB=1. Thus, DIGITAL OUTPUT = 101. 9

A/D Converter Channels Each one of Port-E line is an A/D converter channel. Thus, altogether there are 8 channels. As a result, signals from 8 analog sources can be collected by the 68HC11 microcontroller. 10

A/D Converter Channels Normally V RH and V RL are 5v and 0v lines, respectively. Different voltage signals, in the range 0v to 5v, can be connected to these pin with V RL < V RH. 11

Analog Input & Digital Output If analog input is equal to V RH, then digital output is equal to $FF. If analog input is equal to V RL, then digital output is equal to $00. The conversion curve is linear for other voltages in the range V RL to V RH. 12

Problems Problem-1: What is the value of digital output for an analog input of 3.2v (assume that V RL = 0v and V RH = 5v)? The slope of the analog to digital conversion line is 255/(V RH - V RL ) = 255/5v = 51units/volt. Hence, the digital output for an analog input of 3.2v is = 3.2v*255/5v = 163. Problem-2: If the digital output is 198, then what is the corresponding analog input (V RL = 0v, V RH = 5v)? Since the slope of the conversion line is 51units/volt, the analog input = 198/51 v = 3.88v. 13

More Problems For the following two problems assume that V RL = 1v and V RH = 4v. Problem-3: What is value of digital output for an analog input of 3.2v? The slope of the conversion line is 255/(V RH - V RL ) = 255/3v = 85 units/volt. Hence, the digital output for an analog input of 3.2v is = (3.2v - V RL )*85/v = 2.2*85 = 187. Problem-4: If the digital output is 198, then what is the corresponding analog input? Since the slope of the conversion line is 85 units/volt, the analog input = V RL + 198/85 v = 3.33v. 14

Registers of 68HC11 A/D Converter System Bit-7 of OPTION register is used to activate the charge pump of the A/D converter. Bit-6 of OPTION register is used to select the A/D converter clock. 15

Registers of 68HC11 A/D Converter System CSEL = 0 CSEL = 1 : E clock is selected for A/D the converter : An internal R/C clock is selected for the A/D converter If the frequency of E clock is less than 750 KHz, then the internal R/C clock should be used for the A/D converter. After setting the ADPU bit (Bit-7) of the OPTION register we should wait for at least 105 micro-seconds before we can ask the A/D converter to start conversion. 16

ADCTL A/D Control/Status Register The A/D conversion is started by writing a bit-pattern into ADCTL register. Modes of A/D Converter: MULT (Bit-4) = 0 : Single channel mode Only one channel is selected in this mode. MULT (Bit-4) = 1 : Multi-channel mode Four channels are selected in this mode. 17

Non-Scan and Single Channel Mode SCAN (Bit-5) = 0 and MULT (Bit-4)=0 The A/D converter collects four samples from one channel and then stops. These four samples are saved in the following registers: 18

Non-Scan and Multi-Channel Mode SCAN (Bit-5) = 0 and MULT (Bit-4)=1 The A/D converter collects four samples from four channels, one from each channel and then stops. These four samples are saved in the following registers: 19

Channel Selection 20

CCF: Conversions Complete Flag This read-only status bit (Bit-7 of ADCTL) is set when all four A/D result registers contain valid conversion results. Each time the ADCTL register is written, this bit is automatically cleared, and a new conversion sequence is started immediately. In the continuous scan modes, conversions continue in round-robin fashion, and the result registers are updated with current data even though the CCF bit remains set. 21

Programs-1: A2DPROG1.txt 22

A2DPROG1.txt (contd.) 23

A2DPROG1.txt (contd.) 24

A2DPROG1.txt (contd.) 25

Program-2: A2DPROG2.txt 26

A2DPROG2.txt (contd.) 27

A2DPROG2.txt (contd.) 28

A2DPROG2.txt (contd.) 29

A2DPROG2.txt (contd.) 30

Program-3: A2DPROG3.txt 31

A2DPROG3.txt (contd.) 32

A2DPROG3.txt (contd.) 33

A2DPROG3.txt (contd.) 34

A2DPROG3.txt (contd.) 35