I D, Drain Current (A) IR MOSFET StrongIRFET Application Brushed Motor drive applications BLDC Motor drive applications Battery powered circuits Half-bridge and full-bridge topologies Synchronous rectifier applications Resonant mode power supplies OR-ing and redundant power switches DC/DC and AC/DC converters DC/AC Inverters G D S HEXFET Power MOSFET V DSS R DS(on) typ. max I D (Silicon Limited) I D (Package Limited) D 4V.5m.65m 557A 36A Benefits Optimized for Logic Level Drive Improved Gate, Avalanche and Dynamic dv/dt Ruggedness Fully Characterized Capacitance and Avalanche SOA Enhanced body diode dv/dt and di/dt Capability Lead-Free* RoHS Compliant, Halogen-Free G S S S S S S D2PAK-7Pin G D S Gate Drain Source Standard Pack Base Part Number Package Type Orderable Part Number Form Quantity D2PAK-7Pin Tape and Reel Left 8 R DS (on), Drain-to -Source On Resistance ( m ) 5 I D = 1A 6 LIMITED BY PACKAGE 4 5 3 4 2 1 T J = 125 C 4 8 12 16 2 V GS, Gate-to-Source Voltage (V) 3 2 1 25 5 75 1 125 15 175 T C, Case Temperature ( C) Fig 1. Typical On-Resistance vs. Gate Voltage Fig 2. Maximum Drain Current vs. Case Temperature 1 217-5-12
Absolute Maximum Rating Symbol Parameter Max. Units I D @ T C = 25 C Continuous Drain Current, VGS @ 1V (Silicon Limited) 557 I D @ T C = 1 C Continuous Drain Current, V GS @ 1V (Silicon Limited) 393 I D @ T C = 25 C Continuous Drain Current, V GS @ 1V (Wire Bond Limited) 36 A I DM Pulsed Drain Current 144 P D @T C = 25 C Maximum Power Dissipation 416 W Linear Derating Factor 2.8 W/ C V GS Gate-to-Source Voltage ± 2 V T J Operating Junction and -55 to + 175 T STG Storage Temperature Range C Soldering Temperature, for 1 seconds (1.6mm from case) 3 Avalanche Characteristics E AS (Thermally limited) Single Pulse Avalanche Energy 1275 E AS (Thermally limited) Single Pulse Avalanche Energy 215 mj I AR Avalanche Current A See Fig 15, 16, 23a, 23b E AR Repetitive Avalanche Energy mj Thermal Resistance Symbol Parameter Typ. Max. Units R JC Junction-to-Case.36 R CS Case-to-Sink, Flat Greased Surface.5 C/W R JA Junction-to-Ambient 62 Static @ (unless otherwise specified) Symbol Parameter Min. Typ. Max. Units Conditions V (BR)DSS Drain-to-Source Breakdown Voltage 4 V V GS = V, I D = 25µA V (BR)DSS / T J Breakdown Voltage Temp. Coefficient.31 V/ C Reference to 25 C, I D = 5mA.5.65 V R GS = 1V, I D = 1A DS(on) Static Drain-to-Source On-Resistance m.6.9 V GS = 4.5V, I D = 5A V GS(th) Gate Threshold Voltage 1. 2.4 V V DS = V GS, I D = 25µA 1. V DS = 4 V, V GS = V I DSS Drain-to-Source Leakage Current µa 15 V DS = 4V,V GS = V,T J =125 C Gate-to-Source Forward Leakage 1 V I GSS na GS = 2V Gate-to-Source Reverse Leakage -1 V GS = -2V R G Gate Resistance 2.2 Notes: Calculated continuous current based on maximum allowable junction temperature. Bond wire current limit is 36A. Note that Current imitations arising from heating of the device leads may occur with some lead mounting arrangements. (Refer to AN-114) Repetitive rating; pulse width limited by max. junction temperature. Limited by T Jmax, starting, L =.146mH, R G = 5, I AS = 1A, V GS =1V. I SD 1A, di/dt 18A/µs, V DD V (BR)DSS, T J 175 C. Pulse width 4µs; duty cycle 2%. C oss eff. (TR) is a fixed capacitance that gives the same charging time as C oss while V DS is rising from to 8% V DSS. C oss eff. (ER) is a fixed capacitance that gives the same energy as C oss while VDS is rising from to 8% V DSS. R is measured at T J approximately 9 C. Limited by T Jmax, starting, L = 1mH, R G = 5, I AS = 65A, V GS =1V. Pulse drain current is limited to 144A by source bonding technology. When mounted on 1" square PCB (FR-4 or G-1 Material). For recommended footprint and soldering techniques refer to application note #AN-994: http://www.infineon.com/technical-info/appnotes/an-994.pdf 2 217-5-12
Dynamic Electrical Characteristics @ (unless otherwise specified) Symbol Parameter Min. Typ. Max. Units Conditions gfs Forward Transconductance 264 S V DS = 1V, I D = 1A Q g Total Gate Charge 25 37 I D = 1A Q gs Gate-to-Source Charge 57 V DS = 2V nc Q gd Gate-to-Drain Charge 14 V GS = 4.5V Q sync Total Gate Charge Sync. (Qg Qgd) 11 t d(on) Turn-On Delay Time 67 V DD = 2V t r Rise Time 21 I D = 3A ns t d(off) Turn-Off Delay Time 222 R G = 2.7 t f Fall Time 176 V GS = 4.5V C iss Input Capacitance 1968 V GS = V C oss Output Capacitance 235 V DS = 25V C rss Reverse Transfer Capacitance 1575 pf ƒ = 1.MHz, See Fig.7 C oss eff.(er) Effective Output Capacitance (Energy Related) 269 V GS = V, VDS = V to 32V C oss eff.(tr) Output Capacitance (Time Related) 339 V GS = V, VDS = V to 32V Diode Characteristics Symbol Parameter Min. Typ. Max. Units Conditions Continuous Source Current MOSFET symbol 557 (Body Diode) showing the A G Pulsed Source Current integral reverse 144 (Body Diode) p-n junction diode. I S I SM V SD Diode Forward Voltage 1.2 V,I S =1A,V GS = V dv/dt Peak Diode Recovery dv/dt 2. V/ns T J = 175 C,I S = 1A,V DS = 4V t rr Reverse Recovery Time 42 V DD = 34V ns 43 T J = 125 C I F = 1A, Q rr Reverse Recovery Charge 43 di/dt = 1A/µs nc 45 T J = 125 C I RRM Reverse Recovery Current 1.7 A D S 3 217-5-12
C, Capacitance (pf) V GS, Gate-to-Source Voltage (V) I D, Drain-to-Source Current (A) R DS(on), Drain-to-Source On Resistance (Normalized) I D, Drain-to-Source Current (A) I D, Drain-to-Source Current (A) 1 1 3.25V 3.25V 1 6µs PULSE WIDTH Tj = 25 C VGS TOP 15V 1V 6.V 5.V 4.5V 4.V 3.5V BOTTOM 3.25V 1.1 1 1 1 V DS, Drain-to-Source Voltage (V) Fig 3. Typical Output Characteristics 1 6µs PULSE WIDTH Tj = 175 C VGS TOP 15V 1V 6.V 5.V 4.5V 4.V 3.5V BOTTOM 3.25V 1.1 1 1 1 V DS, Drain-to-Source Voltage (V) Fig 4. Typical Output Characteristics 1 2.2 I D = 1A V GS = 1V 1 1.8 T J = 175 C 1 1.4 1 1..1 V DS = 1V 6µs PULSE WIDTH 1 2 3 4 5 V GS, Gate-to-Source Voltage (V).6-6 -2 2 6 1 14 18 T J, Junction Temperature ( C) Fig 5. Typical Transfer Characteristics Fig 6. Normalized On-Resistance vs. Temperature 1 1 V GS = V, f = 1 MHZ C iss = C gs + C gd, C ds SHORTED C rss = C gd C oss = C ds + C gd 14 12 1 I D = 1A V DS = 32V V DS = 2V V DS = 8V 1 C iss C oss C rss 8 6 1 4 2 1 1 1 1 V DS, Drain-to-Source Voltage (V) 5 1 15 2 25 3 35 4 45 5 Q G, Total Gate Charge (nc) Fig 7. Typical Capacitance vs. Drain-to-Source Voltage Fig 8. Typical Gate Charge vs. Gate-to-Source Voltage 4 217-5-12
V (BR)DSS, Drain-to-Source Breakdown Voltage (V) Energy (µj) I SD, Reverse Drain Current (A) I D, Drain-to-Source Current (A) 1 1 1 OPERATION IN THIS AREA LIMITED BY R DS (on) 1µsec 1 T J = 175 C 1 1 LIMITED BY PACKAGE 1msec 1 V GS = V.1.1.2.3.4.5.6.7.8.9 1. 1.1 V SD, Source-to-Drain Voltage (V) Fig 9. Typical Source-Drain Diode Forward Voltage 1msec 1 Tc = 25 C Tj = 175 C DC Single Pulse.1.1 1. 1. V DS, Drain-toSource Voltage (V) Fig 1. Maximum Safe Operating Area 52 Id = 5.mA 2. 5 1.6 48 1.2 46.8 44.4 42-6 -2 2 6 1 14 18 T J, Temperature ( C ). 1 2 3 4 V DS, Drain-to-Source Voltage (V) Fig 11. Drain-to-Source Breakdown Voltage Fig 12. Typical C oss Stored Energy R DS (on), Drain-to -Source On Resistance ( m ) 1..8.6 V GS = 3.5V V GS = 4.5V V GS = 6.V V GS = 8.V V GS = 1V.4 4 8 12 16 2 I D, Drain Current (A) Fig 13. Typical On-Resistance vs. Drain Current 5 217-5-12
E AR, Avalanche Energy (mj) 1 Thermal Response ( Z thjc ) C/W.1.1 D =.5.2.1.5.2.1.1 SINGLE PULSE Notes: ( THERMAL RESPONSE ) 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc + Tc.1 1E-6 1E-5.1.1.1.1 t 1, Rectangular Pulse Duration (sec) Fig 14. Maximum Effective Transient Thermal Impedance, Junction-to-Case 1 Allowed avalanche Current vs avalanche pulsewidth, tav, assuming Tj = 15 C and Tstart =25 C (Single Pulse) Avalanche Current (A) 1 1 Allowed avalanche Current vs avalanche pulsewidth, tav, assuming j = 25 C and Tstart = 15 C. 1 1.E-6 1.E-5 1.E-4 1.E-3 1.E-2 1.E-1 tav (sec) Fig 15. Avalanche Current vs. Pulse Width 14 12 1 8 6 4 2 TOP Single Pulse BOTTOM 1.% Duty Cycle I D = 1A 25 5 75 1 125 15 175 Starting T J, Junction Temperature ( C) Fig 16. Maximum Avalanche Energy vs. Temperature Notes on Repetitive Avalanche Curves, Figures 15, 16: (For further info, see AN-15 at www.irf.com) 1.Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of T jmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long ast jmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 23a, 23b. 4. P D (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. I av = Allowable avalanche current. 7. T = Allowable rise in junction temperature, not to exceed T jmax (assumed as 25 C in Figure 14, 15). t av = Average time in avalanche. D = Duty cycle in avalanche = tav f Z thjc (D, t av ) = Transient thermal resistance, see Figures 14) PD (ave) = 1/2 ( 1.3 BV I av ) = T/ Z thjc I av = 2 T/ [1.3 BV Z th ] E AS (AR) = P D (ave) t av 6 217-5-12
Q RR (nc) I RRM (A) Q RR (nc) V GS(th), Gate threshold Voltage (V) I RRM (A) 2.5 2. 28 24 2 I F = 6A V R = 34V T J = 125 C 1.5 1. ID = 25µA ID = 1.mA ID = 1.A 16 12 8.5 4. -75-25 25 75 125 175 T J, Temperature ( C ) 2 4 6 8 1 di F /dt (A/µs) Fig 17. Threshold Voltage vs. Temperature Fig 18. Typical Recovery Current vs. dif/dt 28 24 2 I F = 6A V R = 34V T J = 125 C 24 2 16 I F = 6A V R = 34V T J = 125 C 16 12 12 8 8 4 4 2 4 6 8 1 2 4 6 8 1 di F /dt (A/µs) di F /dt (A/µs) Fig 19. Typical Recovery Current vs. dif/dt Fig 2. Typical Stored Charge vs. dif/dt 24 2 16 I F = 1A V R = 34V T J = 125 C 12 8 4 2 4 6 8 1 di F /dt (A/µs) Fig 21. Typical Stored Charge vs. dif/dt 7 217-5-12
Fig 22. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET Power MOSFETs V (BR)DSS 15V tp V DS L DRIVER R G 2V tp D.U.T I AS.1 + - V DD A I AS Fig 23a. Unclamped Inductive Test Circuit Fig 23b. Unclamped Inductive Waveforms Fig 24a. Switching Time Test Circuit Fig 24b. Switching Time Waveforms Vds Id Vgs VDD Vgs(th) Qgs1 Qgs2 Qgd Qgodr Fig 25a. Gate Charge Test Circuit Fig 25b. Gate Charge Waveform 8 217-5-12
D 2 Pak - 7 Pin Package Outline (Dimensions are shown in millimeters (inches)) D 2 Pak - 7 Pin Part Marking Information INTERNATIONAL RECTIFIER LOGO F1324S-7P YWWP PART NUMBER ASSEMBLY LOT CODE 17 89 DATE CODE Y = YEAR W = WEEK P = LEADFREE 9 217-5-12
Qualification Information Qualification Level Moisture Sensitivity Level RoHS Compliant D2PAK-7Pin Industrial (per JEDEC JESD47F) MSL1 (per JEDEC J-STD-2D ) Yes Applicable version of JEDEC standard at the time of product release. Revision History Date Comments 5/12/217 Corrected package picture added s on pin number 4 - page 1. Published by Infineon Technologies AG 81726 München, Germany Infineon Technologies AG 215 All Rights Reserved. IMPORTANT NOTICE The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics ( Beschaffenheitsgarantie ). With respect to any examples, hints or any typical values stated herein and/or any information regarding the application of the product, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. In addition, any information given in this document is subject to customer s compliance with its obligations stated in this document and any applicable legal requirements, norms and standards concerning customer s products and any use of the product of Infineon Technologies in customer s applications. The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of customer s technical departments to evaluate the suitability of the product for the intended application and the completeness of the product information given in this document with respect to such application. For further information on the product, technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies office (www.infineon.com). WARNINGS Due to technical requirements products may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies office. Except as otherwise explicitly approved by Infineon Technologies in a written document signed by authorized representatives of Infineon Technologies, Infineon Technologies products may not be used in any applications where a failure of the product or any consequences of the use thereof can reasonably be expected to result in personal injury. 1 217-5-12