IJSRD - International Journal for Scientific Research & Development Vol. 4, Issue 03, 2016 ISSN (online): 2321-0613 Design and Analysis of Wide Swing Folded-Cascode OTA using 180nm Technology Priyanka Patel 1 Kehul Shah 2 1,2 Sankalchand Patel College of Engineering, Visnagar, India Abstract This paper deals withthe design of Wide Swing Folded-Cascode OTA. An optimum OTA topology is done in order to optimize MOS transistor sizing. Also, the design of Folded Cascode OTA, which works for frequencies that lead to a baseband circuit design for RF application, is based on transistor sizing methodology. This paper deals an effective OTA design for good PSRR, low-voltage, lowpower and wide output voltage swing operational amplifier. Trying to combine an alternative technique of voltage driven- Bulk CMOS with a folded cascade OTA design to improve PSRR and output voltage swing in that circuit by reducing its supply voltage and power consumption. The simulation of the cascode and folded cascode circuits is done using TSPICE simulation tool and the LEVEL 2, 180nm parameters are used. A complete analysis of the circuit is presented in this paper which shows how this circuit leads to a high gain and resistance at output. A comparison between the cascode and Folded-Cascode op amps is described. We have also described their simulated and calculated results comparison individually. The Wide Swing Folded-Cascode OTA is designed using 180 nm CMOS technology. Key words: Power Supply Rejection Ratio (PSRR), Common Mode Rejection Ratio (CMRR), Operational Trans Conductance Amplifier (OTA), Capacitance Load (CL) I. INTRODUCTION The operational transconductance amplifier (OTA) is used as basic building block in many switched capacitor filters OTA is basically an op-amp without an output buffer and can only drive capacitive loads. The Operational Transconductance Amplifier (OTA) is a basic element in this type of circuit whether switched capacitors technique is kept for ADC design. Our target was to design a folded cascode OTA circuit insight of Sigma Delta analog-to-digital converter design using for wide band radio applications. Wide-swing OTA means that the input CMR is close to the supply voltages. The output voltage swing of the OTA is limited by the supply voltages. The name folded-cascode comes from folding down p-channel cascode active loads of a diff-pair and changing the MOSFETs to n-channels. This OTA, like all OTAs, has good PSRR compared to the two-stage op-amp since the OTA is compensated with the load capacitance. This paper summarizes the detailed study of Wide Swing Folded-Cascode OTA with its individual blocks using Tanner Tool(S-edit, T-Spice, W-edit) in 180nm CMOS technology. The basics of Wide Swing Folded- Cascode OTA are described in Section-II. The implementation of Wide Swing Folded-Cascode OTA circuits and the calculative procedures are shown in Section- III. Section IV describes simulation results. Finally the conclusion and future scope is given in Section V. II. BASICS OF WIDE SWING FOLDED-CASCODE OTA The Operational Transconductance Amplifier (OTA) is a basic element in this type of circuit whether switched capacitors technique is kept for ADC design. Our target was to design a folded cascode OTA circuit insight of Sigma Delta analog-to-digital converter design using for wide band radio applications. Fig. 1: Block Diagram of Two Stage Folded-Cascode OTA[5] The input signal of a common-gate stage may be a current and also that in the common-source arrangement a transistor converts a voltage signal to a current signal. The cascade of a CS stage and a CG stage is called a cascode topology, which provides many useful properties. Fig.2.1 shows the basic configuration: M1 generates a small signal drain current that is proportional to V in and M2 simply routes the current to R D. We call M1 the input device and M2 the cascode device. Note that in this example, M1 and M2 carry equal currents. As we describe the attributes of the circuit in this section, many advantages of the cascode topology over a simple Common-Source stage become evident. [Razavi, design of Analog CMOS Integrated Circuits] III. WHOLE IMPLEMENTATION OF WIDE SWING FOLDED- CASCODE OTA Parameters Specifications Slew rate 10V μs Technology 180nm CL 10pf Gain bandwidth 10MHz Gain 60dB Min. and max. output voltages are ± 2.5V Table 1: Design Specifications of Wide Swing Folded- Cascode OTA A. Single Stage OTA Single stage OTA is as shown in fig 2. This single stage OTA is less complex compare to other types of OTA topology. Because of its less complex property its speed is higher compare to other topology. The drawback of this type All rights reserved by www.ijsrd.com 632
of OTA is lower gain due to the fact that output impedance of this type configuration is relatively low. Fig. 2: Block Diagram of Single Stage OTA[5] B. Two Stage OTA As shown in fig.3 that is basic circuit diagram of two stage OTA. In which M1and M2 use for differential input pair, M3 and M4 forms current mirror. The drawback of having limited gain of the single stage OTA is overcome by two stages OTA. In this type of configuration two stages are used. One of them provides high gain followed by second stage which provides high voltage swing. This modification increases the gain up to some certain extent compared to single stage OTA. But this addition of extra stage also increases complexity and the increased complexity will reduce the speed in comparison to a single stage amplifier. Transistors are stacked on top of each other. The transistors are called "cascode", and will increase the output impedance and thereby increase the gain. It provides higher speed. It has lower power consumption. D. Folded Cascode OTA The folded cascode amplifier is in a way some sort of a compromise between the two-stage amplifier and the telescopic cascode amplifier. It permits low supply voltage, still having a rather high output voltage swing and the input and output common mode levels can be designed to be equal. Its gain is lower than for the two-stage and its speed is lower than for the telescopic cascode, which makes it a good compromise between these two amplifiers. Fig. 5: Block Diagram of Folded Cascode OTA Fig. 3: Block Diagram of Two Stage OTA[5] C. Telescopic OTA The Telescopic OTA configuration is as shown in fig 4. Single Stage OTA have low gain due to fact that it has low output impedance, One way of increasing the impedance is to add some transistors at the output including using an active load. Fig. 4: Block Diagram of Telescopic OTA[5] Fig. 6: Schematic of Folded-Cascode OTA in S-edit E. Equations 1) Slew rate 2) Positive CMR Slew rate= I out V in (max)=v DD -[ I 5 β 3 ] V TO3 (max)+v T1 (max) 3) Negative CMR 4) Slew rate V in (min)=v ss +V DS5 (sat)+[ I 5 1 ] β 1 2 +V T1 (max) Slew rate= I 3 5) Bias currents I 4 = I 5 = 1.2I 3 to1.5i 3 = 125μA All rights reserved by www.ijsrd.com 633
6) Using max output voltage S 5 = 2I 5 = 80, S P V 7 = 2I 7 SD5 = 47 P V SD7 7) Using minimum output voltage V DS9 (sat)=v DS11 (sat)= V out (min)+ V SS = 0.258 2 S 11 = 2I 11 = 24, S N V 9 = 2I 9 DS11 = 24 N V DS9 Let S 10 = S 11 and S 8 = S 9 8) Self-bias current R 1 = V SD14(sat) = 2000and R I 2 = V SD8(sat) = 2000 14 I 6 9) Gain bandwidth GB = g m1 S 1 = S 2 = g2 ml K N I 3 10) Using maximum input CM S 4 = S 5 = 11) Using minimum input CM = GB2 C 2 L K N I 3 = 19.34 2I 4 K P (V DD V in (max) + V T1 ) = 10.2 S 3 = 2I 3 K N [V in(min) V SS I 3 K N S 1 ] F. Parameters Values I bias 1 20μA I bias 2 20μA CL 1pf Table 2: Parameter Values Transistor W (μm) L(μm) M1 50 1 M2 50 1 M3 7 1 M4 7 1 M5 7 1 M6 7 1 M7 12 1 M8 10 1 M9 20 1 M10 20 1 M11 9 1 M12 9 1 Table 3: Parameter Values IV. SIMULATED RESULTS 2 = 140 The output waveform and simulation results of various components of Wide Swing Folded-Cascode OTA is shown in figure 7, 8, 9, 10, 11, 12, 13, 14 and 15 and Table1 respectively. Fig. 7: Simulation Result of Gain margine Gain=62 db Fig. 8: Simulation Result of Phase margine Phase margine=45 degree Fig. 9: Simulation Result of Common mode gain CMRR(dB) = differential gain common mode gain = 62dB-(-72dB)= 134dB All rights reserved by www.ijsrd.com 634
Fig. 10: Simulation Result of PSRR PSRR = 80dB Fig. 13: Simulation Result of DC Analysis Fig. 11: Simulation Result of DC Analysis Fig. 14: Simulation Result of Power dissipation Fig. 12: Simulation Result of DC Analysis Fig. 15: Simulation Result of Noise Analysis Parameters Paper-1 Paper-2 Paper-3 Paper-4 Paper-5 Proposed Work Gain (db) 80.5dB 74.6 db 92dB 76.84 db - 62dB Gain bandwidth (GBW) 452 MHz 0.655 MHz 69 MHz 19.46 MHz 10 MHz 10 MHz Slew Rate (V/μs) 5 V/μS 1.93 V/μS 16.5 V/μS - 10 V/μS - PSRR(dB) 74.59 db 45.26 db 2 db - 60 db 80 db Power dissipation 0.126 nm (nm) - - - - 0.096nm Table 2: Comparison of Results with Specification V. CONCLUSION designed with 62 db Gain smargine, 45 degree Phase margine, 80 db PSRR and 0.096nm Power dissipation. In this paper Wide Swing Folded-Cascode OTA has been designed and simulated using 180 nm CMOS technology of tanner tool. Thus Wide Swing Folded-Cascode OTA is All rights reserved by www.ijsrd.com 635
REFERENCES [1] RaghuwarSharan Gautam1, P. K. Jain2, D. S. Ajnar3, Design of Low Voltage Folded Cascode Operational Transconductance Amplifier with Optimum Range of Gain and GBW in 0.18μm Technology International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com Vol. 2, Issue 1,Jan-Feb 2012. [2] I. Toihria and T. Tixier, Improved PSRR and Output Voltage Swing Characteristics of Folded Cascode OTA International Journal of Electronics and Electrical Engineering Vol. 3, No. 4, August 2015 Engineering and Technology Publishing doi: 10.12720/ijeee. [3] H. DaoudDammak, S. Bensalem, S. Zouari, and M. Loulou, Design of Folded Cascode OTA in Different Regions of Operation Through gm/id Methodology International Journal of Electrical and Electronics Engineering 1:3 2008. [4] Tapsi Singh1, Manjit Kaur2, Gurmohan Singh3, Design and Analysis of CMOS Folded Cascode OTA Using Gm/ID Technique International Journal of Electronics and Computer Science Engineering ISSN- 2277-1956 ISSN 2277-1956. [5] Er. Rajni, Design of High Gain Folded-Cascode Operational Amplifier Using 1.25 um CMOS Technology International Journal of Scientific & Engineering Research Volume 2, Issue 11, November- 2011. [6] SanjeevSharma, PawandeepKaur, Tapsi Singh, Design and Analysis of Gain Boosted Recycling Folded Cascode OTA International Journal of Computer Applications (0975 8887) Volume 76 No.7, August 2013. [7] P.E. Allen, D.R. Holberg, A Compact Folded-cascode Operational Amplifier with Class-AB Output Stage EEE 523 Advanced Analog Integrated Circuits Projsect Report. [8] SUDHIR M. MALLYA, MEMRER, IEEE, AND JOSEPH H. NEVIN, MEMBER, IEEE, Design Procedures for a Fully Differential Folded-Cascode CMOS Operational Amplifier IEEEJOURNAL OF SOLID-STATE CIRCUJTS, VOL. 24, NO. 6, DECEMBER1989. All rights reserved by www.ijsrd.com 636