Analysis of High-Performance Synchronous- Asynchronous Digial Conrol for dc-dc Boos Converers S. Saggini ST Microelecronics Indusrial & Power Conversion Division Cornaredo (MI)-Ialy sefano.saggini@s.com G. Garcea, M. Ghioni DEI Poliecnico of Milano Ialy [garcea, ghioni]@ele.polimi.i P. Maavelli DIEGM Universiy of Udine Ialy maavelli@uniud.i Absrac--- This paper invesigaes he applicaion of a mixed synchronous/asynchronous digial conroller o dc-dc boos converers. The digial conrol synchronously generaes curren and lage ramps by using wo low-resoluion Digial-o-Analog Converers (DACs). Swich urn-on and urn-off are deermined asynchronously by comparing converer sae variables and he digially generaed curren and lage ramps. The conrol feaures high dynamic performance, frequency modulaion during ransiens, no quanizaion effecs, and low-complexiy. In order o evaluae he dynamic performance and o compare he proposed soluion wih convenional analog peak curren-mode conrol, a small signal model of he synchronous/asynchronous modulaion is derived. Even if aimed o an inegraed digial conroller, experimenal invesigaion has been performed using discree componens, implemening he digial conrol in a Field Programmable Gae Array (FPGA) using a hardware descripion language (VHDL). Simulaion and experimenal resuls on 1 W dc-dc boos converer confirm he proposed analysis and shows ha he proposed soluion enables dynamic performance comparable o ha of analog peak curren-mode conrol. I. INTRODUCTION Inegraed digial conrollers for Swich-Mode Power Supplies (SMPS) are gaining growing ineres, since when i has been shown he feasibiliy and advanages of digial conroller ICs specifically developed for high-frequency swiching converers [1-8]. Indeed, inegraed digial conrollers for SMPS poenially offer some ineresing advanages compared o heir analog counerpars, due o heir immuniy o componen variaions, abiliy o implemen sophisicaed conrol schemes and sysem diagnosics and, from he inegraed design poin of view, faser design process, ease of inegraion wih oher digial sysems, and sraighforward scaling wih he advances in fabricaion echnologies. One of he main limiing facors for he use of IC digial conrollers in SMPS is he achievemen of performances comparable o hose of analog conrollers in presence of non-idealiies such as conrol delays and quanizaion effecs. Thus, one of he major needs in digial conrol for SMPS is he developmen of simple digial or mixed-signal conrol archiecures wih reduced silicon area requiremens, which ensure dynamic performance comparable o analog conrollers. Mos of he digial conrollers developed up o now [1-8] are based on a convenional archiecure where Analog-o- Digial Converers (ADCs) are used o digialize he converer sae variables and a digial conrol algorihm deermines he duy-cycle, which drives he Digial Pulse Widh Modulaor (DPWM). In order o limi he complexiy of he digial conroller, low resoluion ADCs and DPWM are usually needed [], which unforunaely enhance undesirable quanizaion effecs and limi cycle oscillaions. For his reason, he developmen of alernaive digial (or mixedsignal) conrol archiecures, which overcome he limiaions of convenional soluions, is a challenging fuure rend in SMPS conrol field. One effecive soluion in his direcion has been proposed in [9] for Volage Regulaion Modules (VRM). The conrol archiecure is based on DACs wih low resoluion and on a combinaion of curren programming and variable frequency operaion. However, invesigaion in [9] does no clearly address he dynamic properies especially wih converers having righ-half plane zeros in he ransfer funcion beween he duy-cycle and oupu lage, such as he boos converers. This paper proposes he invesigaion of mixed synchronous/asynchronous digial conroller [9] o dc-dc boos converers. The digial conrol synchronously generaes curren and lage ramps by using wo low-resoluion Digial-o-Analog Converers (DACs). Swich urn-on and urn-off are deermined asynchronously by he comparison beween converer sae variables and he digially generaed curren and lage ramps. An ineresing resul of his paper is he verificaion ha he combinaion of synchronous/asynchronous conrol enables high dynamic performances, pracically comparable o hose obainable wih convenional analog peak curren-mode conrol. A small signal model of he proposed modulaion has been derived and used for he analysis of he dynamic properies and for he derivaion of conroller design. Simulaion and experimenal resuls confirm he proposed analysis.
II. BASICS OF SYNCHRONOUS-ASYNCHRONOUS DIGITAL CONTROL L D i o Fig. 1 shows he basic scheme of he synchronousasynchronous digial conrol applied o dc-dc boos converers. We recall [9] haich urn-on and urn-off are deermined by he logic signal Comp V and Comp I. When inducor or swich curren exceeds he erence signal generaed by DACI, he swich is urned off similarly o peak curren-mode conrol. When he oupu lage is lower han he erence signal generaed by DACV, he swich is urned on. While he swich urn-on and urn-off is deermined asynchronously by he comparaor saus, he digially generaed ramps are synchronous wih sysem clock. Signal generaed by DACI includes a peak curren level and a curren ramp wih negaive slope (-s I ), which ensures he absence of sub-harmonic oscillaions for duy-cycle greaer ha.5. Signal generaed by DACV includes a consan erence lage, which is in pracice generaed ouside he DACV in order o opimize DAC resoluion, and a variable boom level of he lage ramp on which a lage ramp wih posiive slope ( ) is superimposed. Main conrol waveforms in seady-sae condiions are repored in Fig., where he DAC oupus are slighly filered. As any convenional digial conrol archiecure, which requires some analog componens for he ADC, he scheme of Fig. 1 includes some analog blocks (wo low-resoluion DACs and wo comparaors), which are however very simple, no accurae and require a small silicon area for is IC implemenaion. Thus, he digial conrol archiecure is very effecive from he IC poin of view. For he purpose of explanaion, curren and lage slopes are approximaed wih consan values, s I and, respecively. Moreover comparaors and swich on/off propagaion delays are here negleced. Under seady-sae condiions, he average inducor curren I L and he average oupu lage are given by: Tsw IL = I pk si D Tsw Vin D (1) L Vo Vo Vm sv Tsw () where capial leers indicae seady-sae values, T sw is he seady-sae swiching period, D is he seady-sae duy cycle and Vm = sv Tsw, being T sw he erence swiching period. Equaion () indicaes ha seady-sae oupu lage is regulaed by he swiching period T sw. Insead, (1) indicaes haiching period T sw can be conrolled by varying he peak curren I pk, since I L and D are consan for a given load condiion. In pracice, he combinaion of DACV, CompV and he digial conroller ac as an equivalen ADC ha convers he lage error ε = ( v V ) ino a swiching period error o o ε sw = ( sw Tsw ). The sampled error lage ε s is hen obained by muliplying he swiching period error by he Comp I i S ε s v in - reg T (z) G RI DACI driver Q logic s I DACV lage slope. Regulaion of he swiching period is performed by conrolling he peak curren wih a Proporional-Inegral (PI) conrol (reg T (z)) on he sampled lage error ε s. In some insances, he boom level of he lage ramp may be kep consan (swiches in posiion in Fig. 1), i.e. =V m ; his operaing mode is denoed Case A. In oher cases, is modulaed in order o rack he oupu lage variaions. This may be needed, for example, if he lage slope is very small so as o aid converer sauraion during ransien condiions. A possible soluion o conrol is o impose a deadbea regulaion on he swiching period, as depiced in Fig. 3. Once he swiching period is measured, he nex lage ramp ampliude is se so as o cancel he swiching period error in he following swiching cycle. Thus, looking a Fig. 3, a conrol algorihm is derived, based on sampled variables a insan k, so as o impose (k1)=t sw, i.e.: vm( = Vm vm( vm( k 1) = vm( sv Digial conroller G RV Comp V T clk Conroller inegraion G RI - curren ramp generaion G RV -lageramp generaion G sw - evaluaion of Fig. 1 Block diagram of conrol archiecure applied o dc-dc boos converers: when is zero, when is conrolled using (3) [ T ( ] Equaion (3) ensures ha racks oupu lage error based on a predicive conrol on he swiching period ; his S z-1 V m ε sw T sw sw sw G sw C (3) - asynchronous synchronous
operaing mode is denoed Case B. In order o undersand he effec of (3) on he closed-loop conrol, he relaion beween he sampled oupu lage error ε s = ε ( k ) and he swiching period is derived. Looking a Fig.3, we can wrie: vm ( ε ( k 1) = sv sw( () where ε ( = Vo (. By rearranging (3) and (), he swiching period can be expressed as: 1 sw( = Tsw [ ε( k 1) ε( ] (5) sv Thus, for a given consan oupu lage error ε, he swiching period error goes o zero in one sample delay, as expeced by he predicive conrol. The main drawback is ha (5) is a derivaive acion beween he oupu lage error ε and he swiching period variaion. Thus, if he inpu of regulaor reg T (z) is he swiching period error ε sw, a double inegraor is required for ensuring zero seady-sae error. In order o aid more complex regulaor srucure respec o a convenional Proporional-Inegral (PI) conrol, is used as he inpu of he regulaor reg T (z), as repored in Fig. 1 (swiches in posiion ). In fac, rearranging (3) and (), we have: vm ( = ε ( (6) and, is he sampling of he oupu lage error ε. Comp V i S -s I Comp i (k1) V o (k1) (k1) k k1 k Fig. 3 Basic waveforms of predicive conrol on III. SMALL-SIGNAL MODEL A precise small-signal model of he conrol scheme of Fig. 1 is very complex, since i includes analog and digial conrol variables, synchronous and asynchronous evens and variable frequency conrol updae. Insead of very complex models, which handle analog and digial conrol wih variable sampling frequency, a se of approximaions has been used in order o provide a simple coninuous-ime model which represens sysem dynamics well below half of he swiching frequency. More precise and complex models are beyond he scope of his paper. Linearizaion of he synchronous/asynchronous modulaor is performed using he resuls obained in peak curren-mode modeling [1]. Among differen approaches available in lieraure [1]-[1], he mehodology proposed in [1], where he geomeric derivaion of he duy-cycle has been derived using waveforms in ransien condiions, has been here adoped. Following Fig., he average inducor curren over a swiching period is hen expressed as: 1 1 ' = ipk si δ sw son δ sw soff δ sw (7) ' where δ = on sw, δ = 1 δ, son = vin L and soff = ( vin ) L. Large signal averaging (7) has been performed in he analog domain so ha is linearized version can be inerfaced wih convenional ime-averaged smallsignal model of dc-dc boos converers. Represenaion of (7) in he discree domain would require he complex discreizaion of he dc-dc converer ransfer funcions under variable sampling imes. Assuming ha each variable x is composed by a seady-sae value X and a small signal perurbaion xˆ (i.e. x = X xˆ ), linearizaion of (7) yields o he following expression: where ( iˆ pk iˆ L ) K f ˆ sw K vˆ o Kvin vˆ in ˆ δ = (8) Q driver signal 1 = (9.a) sitsw Fig. Curren and lage waveforms under seady-sae condiions
k k1 s on k on k1 s I s off (k1) (k1) Fig. Theoreical curren and lage waveforms under ransien condiions V K = in f D si L (9.b) ' D D Kvin = Tsw (9.c) L ' D K = Tsw (9.d) L The resuling small-signal model is repored in Fig.5, where boh he case when is consan, denoed case A, and he case when is conrolled using (3), denoed case B, are shown. In Fig. 5, he separaion beween coninuous-ime and discree-ime domain is based on he asynchronous and synchronous conribuions, respecively. More precisely, he asynchronous par of he modulaor, which imposes swich urn-on and urn-off based on he analog inersecions of lage and curren ramps and wih he converer sae variables, is repored in he coninuous domain. The synchronous par, insead, is repored in he discree domain, inerfaced wih he analog model using an ADC and DACs. In order o compare conroller performance and o design he coefficiens of regulaor reg T (z), he ransfer funcion G(s) beween and has been derived. For case A, G A (s) is: GA( s) = (1) 1 1 Fi1 H 1 ( K K f sv ) 1 3 GH ia where GH ia (s) is he curren loop gain and H(s) includes he sampling effec of he peak-curren mode modulaor [11]. Insead, for case B, (1) becomes GB = (11) 1 1 Fi1 H 1 ( K stswk f sv ) 1 3 GH ib where he derivaive acion (5) has been represened in he equivalen coninuous-ime domain. The validiy of (1) and (11) has been verified using imedomain simulaions, where a small-signal sinusoidal perurbaion has been imposed on he peak curren and he ampliude and phase of he resuling sinusoidal perurbaion on he oupu lage has been measured. The converer values are hose repored in he simulaion resuls secion. Fig. 6 repors he ransfer funcion beween he peak curren and he sampled oupu lage ε s for case A and B respecively (solid lines). The comparison wih he resuls compued by numerical simulaions (indicaed wih o ) shows ha he model is quie accurae, wih small discrepancies for frequencies approaching 1/ of he swiching frequency. I is worh noing ha he modulaion of (case B) has a bigger phase shif and hus a slighly less damped response is expeced. Even if approximaed, we found his model accurae enough for sabiliy analysis and design of regulaor coefficiens. For regulaor coefficien design and for he derivaion of Fig. 6, he ransfer funcion seen by regulaor reg T (i.e. he ransfer funcion beween he peak curren and he sampled oupu lage ε s ) is simply obained by sampling ransfer funcion (1) and (11), since in boh cases A and B he inpu of reg T is a sampled version of he oupu lage. In order o accoun for he sampling process, a simple phase delay of ωt sw / has been added o (1) and (11). As far as he quanizaion effecs are concerned, i worh o poin ou ha he signals and generaed by DACs are quanized. Moreover, he measured swiching period of he converer is quanized as well, being an ineger muliple of he clock period [9]. However, hanks o he use of he digial curren ramp, he average inducor curren can be coninuously varied by modulaing he delay beween he asynchronous swich-on command and he synchronous sar of. As repored in [13], his siuaion ensures ha any sae-sae load curren and lage can be heoreically supplied wihou incurring in limi cycles condiions. In order o aid also he presence of limi cycles enhanced by he digial regulaor reg T (z), he lage slope mus be properly designed. More precisely, lower value of lage slope reduces he possibiliy of limi cycle oscillaions caused by he digial regulaor, since he effecive resoluion in he A/D conversion of he error lage is increased and he digial conroller gain of is reduced. These wo condiions increase he immuniy of he sysem from limi cycles, as shown in [3] and [1].
Frequency modulaion effecs K F δδ δδ δ1 δ 1 K F m DAC ε s s v reg T (z) ADC K vin vin in H io i o /(z-1) sw boos small-signal model F v1 F v F v3 F i1 F i F i3 v m DAC 1/ resuls are repored in Fig. 8. Noe ha in his case he dynamic response is quie similar, bu he swiching period variaion is now he derivaive of he oupu lage variaion, as prediced in (5). A closer comparison beween Fig. 7 and 8 is repored in Fig. 9. Noe ha he frequency modulaion is much smaller for case B and he sysem response has a small overshoo no presen in case A. This is also consisen wih Fig. 6 due o he higher delay of case B a he crossover frequency. [V] [A] 5 8 6 R v Fig. 5 Small signal model of he synchronous/asynchronous modulaor IV. SIMULATION RESULTS Conrol algorihm has been iniially esed by simulaion ools so as o verify he performed heoreical analysis. The converer parameer are: V in = V, =8 V, L=8 µh, C=1 µf, f sw = khz, P onominal =1 W, f clk = MHz. Coefficien of lage loop regulaor reg T has been designed so as o ensure a bandwidh of 16 khz and a phase margin of 6. Fig. 7 repors he load sep variaions (R o = 5 Ω 5 Ω 5 Ω ) for case A. Noe ha he proposed sysem gives good dynamic performance wih damping and ime response which well agree wih regulaor design. Moreover, he swiching period variaion is proporional o he oupu lage error, as expeced by (). Using he same regulaor parameers, we have esed also case B and he [db] [deg] 1-1 - -5-1 -15-1 1 Magniude Frequency [Hz] Phase F sw /3 Frequency [Hz] Fig. 6 Verificaion of he proposed small-signal model (dos o indicae imedomain simulaions): case A and B, ransfer funcion beween and ε s [µs] 6 5 Time [µs] Fig. 7 Load sep changes (R o = 5 Ω 5 Ω 5 Ω ) wih he proposed scheme Case A. [V] [A] [µs] 5 8 6 6 5 R v Time [µs] Fig. 8 Load sep changes (R o = 5 Ω 5 Ω 5 Ω ) wih he proposed scheme Case B.,
[V] 8 7.5 sw 7 [A] 6 8 3 3 3 6.5 [µs] 6 sw 5.5 5.5 3.5 6 8 3 3 3 Time [µs] Fig. 9 Load sep changes (Ro = 5 Ω 5 Ω 5 Ω ) wih he proposed scheme: Case A and B V. EXPERIMENTAL RESULTS For he experimenal verificaion a boos converer has been realized wih he following parameers: Vin= V, Vo=8 V, L=8 µh, C=1 µf, fsw= khz, Ponominal=1 W, fclk=8 MHz. Two DACs has been used and he digial conrol has been implemened in an FPGA by Alera, specifically he EP1C device, a member of Cyclone family. For he experimenal invesigaion, only case A has been esed. Fig. 1 repors he dynamic behavior of he digial conrol under small sep changes (Ro = 75 Ω 5 Ω 75 Ω ). The ransien is fas and well damped, wihou limi cycle oscillaions afer he load sep changes. For comparison, we have implemened an analog conrol wih peak curren-mode conrol, having a lage-loop bandwidh of 16 khz and a swiching frequency equal o khz. Fig. 11 shows he resuls obained using he same condiions of Fig. 1. Noe ha he dynamic behavior is quie similar, showing ha he proposed digial soluion gives dynamic performance comparable o ha of he sae-of-he-ar of analog conrollers a leas under small-signal assumpions. Insead, wih large-signal sep-up load variaions we expec our soluion o have a slighly higher dynamic response hanks o he frequency modulaion. This is also eviden by looking a Figure 1 and 13, which repor a bigger load sep change (Ro = 75 Ω 5 Ω ) using he proposed digial conrol (Fig. 1) and he analog conrol (Fig. 13). Of course, he opposie properies are expeced under large-signal sep-down load variaions, here no repored due o severe DCM operaion. Finally, i is worh noing ha he proposed soluion behaves very well in spie of a significan hyseresis band in he wo comparaors and a large delay in our Mosfe driver (5 ns), as repored in Fig. 1. Fig. 1 Load sep changes (Ro = 75 Ω 5 Ω 75 Ω ) wih he proposed scheme (vo.5v/div, -1A/div,, SW -.5 µ/div) Fig. 11 Load sep changes (Ro = 75 Ω 5 Ω 75 Ω ) wih analog peak curren-mode conrol (vo.5v/div, -1A/div) sw Fig. 1 Load sep change (Ro = 75 Ω 5) wih he proposed scheme (vo /div, -A/div,, SW -1.5 µ/div)
REFERENCES Fig. 13 Load sep change (R o = 75Ω 5Ω) wih analog peak curren-mode conrol (v O V/div, -A/div) i S R v Fig. 1 (op) oupu lage and digially generaed lage ramp R v (R v,v O V /div) and (boom) swich curren i S and digially generaed curren ramp (, A/div) in seady-sae condiions [1] B.J. Paella, A. Prodic, A. Zirger, D. Maksimović, High-frequency Digial Conroller IC for dc/dc Converers, IEEE Trans. on Power Elecronics, Vol. 18, No. 1, January 3, pp. 38-6. [] J. Xiao, A.V. Peerchev, S.R. Sanders, Archiecure and IC implemenaion of a digial VRM conroller, IEEE Trans. on Power Elecronics, Vol. 18, No. 1, January 3, pp. 356-36. [3] A.V. Peerchev, S.R. Sanders, Quanizaion resoluion and limi cycling in digially conrolled PWM converers, IEEE Trans. on Power Elecronics, Vol. 18, No. 1, January 3, pp. 31-38. [] A. Prodic, D. Maksimovic, R.W. Erickson Design and implemenaion of a digial PWM conroller for a high-frequency swiching dc-dc power converer, IEEE IECON 1, 1, pp. 893-898. [5] F. Kurokawa, T. Sao, H. Masuo, H. Eo, Oupu characerisics of DC- DC converer wih DSP conrol h Annual Inernaional Telecommunicaions Energy Conference,, (INTELEC ), pp: 1-6. [6] C. Kranz, Complee Digial Conrol Mehod for PWM dc-dc Boos Converer IEEE Power Elecronics Conference 3 (PESC 3), Acapulco, Mexico, June 3. [7] J. Chen, A. Prodic, R. W. Erickson and D. Maksimovic, Predicive digial curren programmed conrol, IEEE Trans. on Power Elecronics, Vol. 18, No. 1, pp. 1-19, January 3 [8] Huliehel, F.; Ben-Yaakov, S, Low-frequency sampled-daa models of swiched mode DC-DC converers, IEEE Transacions on Power Elecronics, Vol. 6, No. 1, Jan. 1991, pp 55-61. [9] S. Saggini, M. Ghioni, A. Geraci, An innovaive digial conrol archiecure for low-lage, high-curren dc-dc converers wih igh lage regulaion IEEE Trans. on Power Elecronics, l. 19, January, pp. 1-18. [1] R. W. Erickson and D. Maksimovic, Fundamenals of Power Elecronics, nd Ediion, Kluwer Academic Publishers, 1. [11] Ridley R.B. A new coninuous-ime model for curren-mode conrol IEEE Trans. on Power Elecronics, Vol. 6, No., pp. 71-8, April 1991. [1] D. Perreaul, G.C. Verghese, Time-Varying Effecs and averaging issues in models for curren-mode conrol, IEEE Trans. on Power Elecronics, Vol. 1, No. 3, May 1997, pp. 53-61, May 1997. [13] G. Garcea, S. Saggini, C. Pora, A. Geraci, M. Ghioni An innovaive Digial Conroller for VRM Applicaion wih negligible quanizaion effecs Power Elecronics Technology Conf., Chicago, 16-18 November,. [1] Hao Peng, D Maksimovic, A. Prodic, E. Alarcon, Modeling of quanizaion effecs in digially conrolled DC-DC converers, Power Elecronics Specialiss Conference (PESC ), June -5,, pp. 31 318. VI. CONCLUSIONS This paper has invesigaed a mixed synchronous/asynchronous digial conroller applied o dc-dc boos converers. I has been shown ha he combinaion of digially conrolled lage and curren ramps and asynchronous swich urn-on and urn-off enable highdynamic performance while keeping low conrol complexiy. An approximaed small-signal model synchronous/asynchronous digial conroller has been also derived and used for dynamic performance evaluaion. Simulaion and experimenal resuls have verified he dynamic performance achievable by he proposed soluion for dc-dc boos converers, showing ha he overall conrol performance is comparable o ha obainable wih analog peak currenmode conrol.