PD -9744A IRFS37PbF IRFSL37PbF HEXFET Power MOSFET Applications l High Efficiency Synchronous Rectification in SMPS l Uninterruptible Power Supply l High Speed Power Switching l Hard Switched and High Frequency Circuits G D V DSS R DS(on) typ. max. I D (Silicon Limited) 75V 2.5m: 3.m: 23A c Benefits l Improved Gate, Avalanche and Dynamic dv/dt Ruggedness l Fully Characterized Capacitance and Avalanche SOA l Enhanced body diode dv/dt and di/dt Capability l Lead-Free D S G I D (Package Limited) D S 95A S D G D 2 Pak IRFS37PbF TO-262 IRFSL37PbF G D S Gate Drain Source Absolute Maximum Ratings Symbol Parameter Max. Units I D @ T C = 25 C Continuous Drain Current, V GS @ V (Silicon Limited) 23c I D @ T C = C Continuous Drain Current, V GS @ V (Silicon Limited) 6 I D @ T C = 25 C Continuous Drain Current, V GS @ V (Wire Bond Limited) 95 A I DM Pulsed Drain Current d 9 P D @T C = 25 C Maximum Power Dissipation 37 W Linear Derating Factor 2.5 W/ C V GS Gate-to-Source Voltage ± 2 V dv/dt Peak Diode Recovery f 4 V/ns Operating Junction and -55 to 75 T STG Storage Temperature Range Soldering Temperature, for seconds 3 C (.6mm from case) Mounting torque, 6-32 or M3 screw lbxin (.Nxm) Avalanche Characteristics E AS (Thermally limited) Single Pulse Avalanche Energy e 3 mj I AR Avalanche Currentd See Fig. 4, 5, 22a, 22b, A E AR Repetitive Avalanche Energy g mj Thermal Resistance Symbol Parameter Typ. Max. Units R θjc Junction-to-Case kl.4 R θja Junction-to-Ambient (PCB Mount) jk 4 C/W www.irf.com 5/2/
IRFS/SL37PbF Static @ = 25 C (unless otherwise specified) Symbol Parameter Min. Typ. Max. Units Conditions V (BR)DSS Drain-to-Source Breakdown Voltage 75 V V GS = V, I D = 25μA ΔV (BR)DSS /Δ Breakdown Voltage Temp. Coefficient.9 V/ C Reference to 25 C, I D = 5mAd R DS(on) Static Drain-to-Source On-Resistance 2.5 3. mω V GS = V, I D = 4A g V GS(th) Gate Threshold Voltage 2. 4. V V DS = V GS, I D = 25μA I DSS Drain-to-Source Leakage Current 2 μa V DS = 75V, V GS = V 25 V DS = 75V, V GS = V, = 25 C I GSS Gate-to-Source Forward Leakage na V GS = 2V Gate-to-Source Reverse Leakage - V GS = -2V R G Internal Gate Resistance.2 Ω Dynamic @ = 25 C (unless otherwise specified) Symbol Parameter Min. Typ. Max. Units gfs Forward Transconductance 23 S Q g Total Gate Charge 6 24 nc Q gs Gate-to-Source Charge 38 Q gd Gate-to-Drain ("Miller") Charge 54 Q sync Total Gate Charge Sync. (Q g - Q gd ) 6 t d(on) Turn-On Delay Time 9 ns t r Rise Time t d(off) Turn-Off Delay Time 99 t f Fall Time C iss Input Capacitance 937 pf C oss Output Capacitance 84 C rss Reverse Transfer Capacitance 58 C oss eff. (ER) Effective Output Capacitance (Energy Related) 3 C oss eff. (TR) Effective Output Capacitance (Time Related)h 5 Diode Characteristics Symbol Parameter Min. Typ. Max. Units I S Continuous Source Current 23c A Conditions V DS = 5V, I D = 4A I D = 4A V DS =38V V GS = V g I D = 4A, V DS =V, V GS = V V DD = 49V I D = 4A R G = 2.7Ω V GS = V g V GS = V V DS = 5V ƒ =. MHz, See Fig. 5 V GS = V, V DS = V to 6V i, See Fig. V GS = V, V DS = V to 6V h Conditions MOSFET symbol (Body Diode) showing the G I SM Pulsed Source Current 9 A integral reverse (Body Diode)d p-n junction diode. V SD Diode Forward Voltage.3 V = 25 C, I S = 4A, V GS = V g t rr Reverse Recovery Time 54 ns = 25 C V R = 64V, 6 = 25 C I F = 4A Q rr Reverse Recovery Charge 3 nc = 25 C di/dt = A/μs g 32 = 25 C I RRM Reverse Recovery Current 3.6 A = 25 C t on Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LSLD) D S Notes: Calculated continuous current based on maximum allowable junction temperature. Bond wire current limit is 95A. Note that current limitations arising from heating of the device leads may occur with some lead mounting arrangements. (Refer to AN-4) Repetitive rating; pulse width limited by max. junction temperature. ƒ Limited by max, starting = 25 C, L =.45mH R G = 25Ω, I AS = 4A, V GS =V. Part not recommended for use above this value. I SD 4A, di/dt 38A/μs, V DD V (BR)DSS, 75 C. Pulse width 4μs; duty cycle 2%. C oss eff. (TR) is a fixed capacitance that gives the same charging time as C oss while V DS is rising from to 8% V DSS. C oss eff. (ER) is a fixed capacitance that gives the same energy as C oss while V DS is rising from to 8% V DSS. ˆ When mounted on " square PCB (FR-4 or G- Material). For recom mended footprint and soldering techniques refer to application note #AN-994. R θ is measured at approximately 9 C Š R θjc value shown is at time zero. 2 www.irf.com
C, Capacitance (pf) V GS, Gate-to-Source Voltage (V) I D, Drain-to-Source Current (Α) R DS(on), Drain-to-Source On Resistance (Normalized) I D, Drain-to-Source Current (A) I D, Drain-to-Source Current (A) IRFS/SL37PbF VGS TOP 5V V 8.V 7.V 6.V 5.5V 4.8V BOTTOM 4.5V VGS TOP 5V V 8.V 7.V 6.V 5.5V 4.8V BOTTOM 4.5V 4.5V 4.5V 6μs PULSE WIDTH Tj = 25 C. V DS, Drain-to-Source Voltage (V) 6μs PULSE WIDTH Tj = 75 C. V DS, Drain-to-Source Voltage (V) Fig. Typical Output Characteristics Fig 2. Typical Output Characteristics 2.5 I D = 4A V GS = V = 75 C 2. = 25 C.5 V DS = 25V 6μs PULSE WIDTH 2. 3. 4. 5. 6. 7. V GS, Gate-to-Source Voltage (V) Fig 3. Typical Transfer Characteristics..5-6 -4-2 2 4 6 8 2 4 6 8, Junction Temperature ( C) Fig 4. Normalized On-Resistance vs. Temperature 6 2 V GS = V, f = khz C iss = C gs C gd, C ds SHORTED C rss = C gd C oss = C ds C gd 6 2 I D = 4A V DS = 6V V DS = 38V Ciss 8 8 4 Coss 4 Crss V DS, Drain-to-Source Voltage (V) 4 8 2 6 2 24 Q G Total Gate Charge (nc) Fig 5. Typical Capacitance vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage www.irf.com 3
Energy (μj) E AS, Single Pulse Avalanche Energy (mj) I D, Drain Current (A) V (BR)DSS, Drain-to-Source Breakdown Voltage I D, Drain-to-Source Current (A) IRFS/SL37PbF I SD, Reverse Drain Current (A). 25 2 = 75 C = 25 C V GS = V..5..5 2. 2.5 V SD, Source-to-Drain Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage LIMITED BY PACKAGE LIMITED BY PACKAGE Fig 8. Maximum Safe Operating Area I D = 5mA OPERATION IN THIS AREA LIMITED BY R DS (on) msec μsec msec Tc = 25 C DC Tj = 75 C Single Pulse.. V DS, Drain-toSource Voltage (V) 5 9 5 8 25 5 75 25 5 75 T C, Case Temperature ( C) Fig 9. Maximum Drain Current vs. Case Temperature 7-6 -4-2 2 4 6 8 2 4 6 8, Junction Temperature ( C) Fig. Drain-to-Source Breakdown Voltage 4. 3. 4 2 I D TOP 2A 49A BOTTOM 4A 2. 8 6. 4 2. 2 4 6 8 25 5 75 25 5 75 V DS, Drain-to-Source Voltage (V) Starting, Junction Temperature ( C) Fig. Typical C OSS Stored Energy Fig 2. Maximum Avalanche Energy Vs. DrainCurrent 4 www.irf.com
E AR, Avalanche Energy (mj) Avalanche Current (A) IRFS/SL37PbF Thermal Response ( Z thjc ) D =.5..2..5..2 R R 2 R 3 R R 2 R 3 Ri ( C/W) τι (sec) τ. J τ τ C J τ.477.7 τ τ τ 2 τ 3 τ 2 τ 3.634.88. SINGLE PULSE Ci= τi/ri Ci= τi/ri.8934.7457 ( THERMAL RESPONSE ) Notes:. Duty Factor D = t/t2 2. Peak Tj = P dm x Zthjc Tc. E-6 E-5.... t, Rectangular Pulse Duration (sec) Fig 3. Maximum Effective Transient Thermal Impedance, Junction-to-Case Duty Cycle = Single Pulse Allowed avalanche Current vs avalanche pulsewidth, tav, assuming ΔTj = 5 C and Tstart =25 C (Single Pulse)..5. 35 3 25 2 5 Allowed avalanche Current vs avalanche pulsewidth, tav, assuming ΔΤ j = 25 C and Tstart = 5 C..E-6.E-5.E-4.E-3.E-2.E- 5 TOP Single Pulse BOTTOM % Duty Cycle I D = 4A 25 5 75 25 5 75 Starting, Junction Temperature ( C) tav (sec) Fig 5. Maximum Avalanche Energy vs. Temperature Fig 4. Typical Avalanche Current vs.pulsewidth Notes on Repetitive Avalanche Curves, Figures 4, 5: (For further info, see AN-5 at www.irf.com). Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of T jmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long ast jmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 6a, 6b. 4. P D (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (.3 factor accounts for voltage increase during avalanche). 6. I av = Allowable avalanche current. 7. ΔT = Allowable rise in junction temperature, not to exceed T jmax (assumed as 25 C in Figure 4, 5). t av = Average time in avalanche. D = Duty cycle in avalanche = t av f Z thjc (D, t av ) = Transient thermal resistance, see Figures 3) P D (ave) = /2 (.3 BV I av ) = DT/ Z thjc I av = 2DT/ [.3 BV Z th ] E AS (AR) = P D (ave) t av www.irf.com 5
Q RR - (nc) I RRM - (A) Q RR - (nc) V GS (th) Gate threshold Voltage (V) I RRM - (A) IRFS/SL37PbF 4.5 4. 3.5 I D =.A I D =.ma I D = 25μA 32 24 3. 2.5 6 2..5. -75-5 -25 25 5 75 25 5 75, Temperature ( C ) Fig 6. Threshold Voltage Vs. Temperature I F = 9A 8 V R = 64V = 25 C = 25 C 2 3 4 5 6 7 8 9 di f / dt - (A / μs) Fig. 7 - Typical Recovery Current vs. di f /dt 32 8 24 6 6 4 I F = 35A 8 V R = 64V = 25 C = 25 C 2 3 4 5 6 7 8 9 di f / dt - (A / μs) Fig. 8 - Typical Recovery Current vs. di f /dt I F = 9A 2 V R = 64V = 25 C = 25 C 2 3 4 5 6 7 8 9 di f / dt - (A / μs) Fig. 9 - Typical Stored Charge vs. di f /dt 8 6 4 I 2 F = 35A V R = 64V = 25 C = 25 C 2 3 4 5 6 7 8 9 di f / dt - (A / μs) Fig. 2 - Typical Stored Charge vs. di f /dt 6 www.irf.com
IRFS/SL37PbF - D.U.T ƒ - Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer - Reverse Recovery Current Driver Gate Drive Period P.W. D.U.T. I SD Waveform Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt D = P.W. Period V GS =V V DD * R G dv/dt controlled by RG Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test V DD - Re-Applied Voltage Body Diode Inductor Curent Current Forward Drop Ripple 5% I SD * V GS = 5V for Logic Level Devices Fig 2. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET Power MOSFETs 5V tp V (BR)DSS V DS L DRIVER R G 2V V GS tp D.U.T I AS.Ω - V DD A I AS Fig 22a. Unclamped Inductive Test Circuit Fig 22b. Unclamped Inductive Waveforms V DS R D V DS V GS D.U.T. 9% R G - V DD VV GS Pulse Width µs Duty Factor. % % V GS t d(on) t r t d(off) t f Fig 23a. Switching Time Test Circuit Fig 23b. Switching Time Waveforms Current Regulator Same Type as D.U.T. Vds Id 5KΩ Vgs 2V.2μF.3μF V GS D.U.T. V - DS Vgs(th) 3mA I G I D Current Sampling Resistors Qgs Qgs2 Qgd Qgodr Fig 24a. Gate Charge Test Circuit Fig 24b. Gate Charge Waveform www.irf.com 7
IRFS/SL37PbF TO-262 Package Outline Dimensions are shown in millimeters (inches) TO-262 Part Marking Information EXAMPLE: THIS IS AN IRL33L LOT CODE 789 ASSEMBLED ON WW 9, 997 IN THE ASSEMBLY LINE "C" INTERNATIONAL RECTIFIER LOGO ASSEMBLY LOT CODE PART NUMBER DATE CODE YEAR 7 = 997 WEEK 9 LINE C OR INTERNATIONAL RECTIFIER LOGO AS S E MBLY LOT CODE PART NUMBER DATE CODE P = DESIGNATES LEAD-FREE PRODUCT (OPTIONAL) YEAR 7 = 997 WEEK 9 A = ASSEMBLY SITE CODE Note: For the most current drawing please refer to IR website at http://www.irf.com/package/ 8 www.irf.com
IRFS/SL37PbF D 2 Pak (TO-263AB) Package Outline Dimensions are shown in millimeters (inches) D 2 Pak (TO-263AB) Part Marking Information T HIS IS AN IRF53S WITH LOT CODE 824 ASSEMBLED ON WW 2, 2 IN THE ASSEMBLY LINE "L" INTERNATIONAL RECTIFIER LOGO AS S E MB LY LOT CODE F53S PART NUMBER DATE CODE YEAR = 2 WEEK 2 LINE L OR INTERNATIONAL RECTIFIER LOGO AS S E MB LY LOT CODE F53S PART NUMBER DATE CODE P = DESIGNATES LEAD - FREE PRODUCT (OPTIONAL) YEAR = 2 WEEK 2 A = AS S E MBL Y S IT E CODE Note: For the most current drawing please refer to IR website at http://www.irf.com/package/ www.irf.com 9
IRFS/SL37PbF D 2 Pak (TO-263AB) Tape & Reel Information Dimensions are shown in millimeters (inches) TRR.6 (.63).5 (.59) 4. (.6) 3.9 (.53).6 (.63).5 (.59).368 (.45).342 (.35) FEED DIRECTION TRL.85 (.73).65 (.65).6 (.457).4 (.449) 5.42 (.69) 5.22 (.6) 24.3 (.957) 23.9 (.94).9 (.429).7 (.42) 6. (.634) 5.9 (.626).75 (.69).25 (.49) 4.72 (.36) 4.52 (.78) FEED DIRECTION 3.5 (.532) 2.8 (.54) 27.4 (.79) 23.9 (.94) 4 33. (4.73) MAX. 6. (2.362) MIN. NOTES :. COMFORMS TO EIA-48. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION MEASURED @ HUB. 4. INCLUDES FLANGE DISTORTION @ OUTER EDGE. 26.4 (.39) 24.4 (.96) 3 3.4 (.97) MAX. 4 Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/ Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR s Web site. IR WORLD HEADQUARTERS: N. Sepulveda., El Segundo, California 9245, USA Tel: (3) 252-75 TAC Fax: (3) 252-793 Visit us at www.irf.com for sales contact information. www.irf.com 5/2