Device Engineering Incrprated 385 East Alam Drive handler, AZ 85225 Phne: (48) 33-822 Fax: (48) 33-824 E-mail: admin@deiaz.cm DEI 128 ltage lamping ircuit Features Prtectin fr pwer electrnics n 28D avinics r industrial pwer bus. ntrls pwer P-FET t clamp transient at 34. Small ft print (8L SOI NB). Wide input vltage range. Prgrammable Undervltage Lckut. Lgic cmpatible On/Off input. Stable ver temperature. Sft start delay. General Descriptin The DEI128 is a cntrl circuit fr a 28D pwer bus vltage clamp. It is designed fr use as the frnt end t a 28D input pwer supply t prvide transient vltage prtectin. It cntrls the gate drive f a P-hannel pwer MOSFET t linearly clamp the utput during ver vltage transients. The utput vltage is maintained belw the clamping threshld f 35 (max) which is adequate t prtect mst mmercial-off-the-shelf switching supplies, linear regulatrs, and p amps. The device prtects against a 1 spike f 1ms duratin and prvides versht prtectin. There is an Undervltage Lckut feature that shuts the Pwer MOSFET ff when the input vltage is belw a user prgrammed threshld. An pen cllectr lgic utput annunciates the under vltage status. There is als a lgic n/ff input which may be used t cntrl the pwer circuit. An external capacitr may be used t set a delay frm when input pwer is applied t when the MOSFET is turned n. Table 1: Pin Definitins Pin # Name Type / Descriptin 1 GATE 2 AP OUTPUT. ntrls the gate f the external p-channel pwer MOS- FET. IN/OUT. ntrls the sft start delay f the device. Use.22uF fr 2ms minimum sft start time. GATE AP 1 2 8 7 OUT GND 3 IN INPUT. Pwer input fr the DEI128 ltage lamp. IN 3 6 NU 4 UL INPUT. ntrls the under vltage lckut cnditin f the device. 5 NON INPUT. Lgic lw enables device. Lgic high disables device. UL 4 5 NON 6 NU OUTPUT. Open cllectr utput. Active lw when IN is belw UL threshld. DEI128 Pin Diagram 7 GND POWER. Grund 8 OUT INPUT. Feedback t gate cntrl frm drain f Pwer MOSFET. 22 Device Engineering Inc. Page 1 f 5
Table 2: Abslute Maximum Ratings Parameter Symbl Rating Units IN Pin: Relative t GND ntinuus 1 ms Transient 1 ms Transient IN t +4-5 +1 UL Pin: Relative t IN UL -6 t +.5 AP Pin: Relative t IN AP -2 t +2 GATE Pin: Relative t IN GATE -1 t +.5 NON Pin: Relative t GND NON -.5 t + 6. NU Pin: Relative t GND NU -.5 t + 2 OUT Pin: Relative t GND OUT -.5 t + 4 Operating Temperature T A -55 t +85 Strage Temperature T STG -55 t +125 Lead sldering temperature (1 sec duratin) +28 Table 3: Operating haracteristics (Ta = -55 º t 85 º) Parameter Symbl nditins Min Typ Max Units lamp utput vltage O(L1) IN = 4, 6 33 35 lamp utput vltage O(L2) IN = 1 (1) 33 35 lamp utput vltage (L3) IN = -5 (1,2) - - - Surce-Gate FET vltage (ON) SG(1) RUL = 13.6 kω, IN = 14 9 1 Surce-Gate FET vltage (OFF) SG(2) RUL = 13.6 kω, IN = 1.7 Surce-Gate FET vltage (ON) SG(1) RUL = 7 kω, IN = 25 9 1 Surce-Gate FET vltage (OFF) SG(2) RUL = 7 kω, IN = 19.5.7 Surce-Gate FET vltage (LINEAR) SG(3) 35 < IN < 1, OUT= lamp ltage (33 35v).7 9 Turn-n time t ON =.22µF; see Figures 4, 5. 2 msec Sft start delay charge current I ST IN > 1.75 3 µa Sft start delay threshld ST IN > 1 IN - 2.5 IN - 2.9 versht vltage MX See Figure 6. (1) 35 settling time t S See Figure 6. (1) 2 msec Supply urrent I IN IN = 3 5 ma Ntes: 1. Guaranteed by design and nt prductin tested. 2. Device must survive this test. Duratin f negative vltage must be limited t less than 1 ms due t heating effects. 3. MOSFET capacitance (gs) must be in the range 5 ~ 5 pf. If belw 5 pf, an external 47 pf capacitr must be cnnected between the DEI128 OUT and GATE pins. Table 4: Lgic haracteristics (Ta = -55 º t 85 º) Parameter Symbl nditins Min Typ Max Units NON input lgic 1 level IH IN = 8 t 3 2.8 NON input lgic level IL IN = 8 t 3.8 NON input lgic current I IL NON = IN = 8 t 3-3 -3 µa NU utput lgic 1 level OH R UL = 13.6 kω, IN = 14, R PU = 1 kωt 5 (See Figure 7.) NU utput lgic level OL R UL = 13.6 kω, IN = 1 I OL = 42 µa (See Figure 7.) 4.75.8 22 Device Engineering Inc. Page 2 f 5
Gate Drive The DEI128 device is designed t cntrl the gate f a P-hannel pwer MOSFET such as the IRF954. At nrmal peratin the gate utput turns the transistr ON t saturatin. Belw under vltage cnditins the MOSFET is shut ff. In clamp mde the MOSFET is driven t linear mde, keeping the utput at apprximately 34. Undervltage Lckut An Undervltage Lckut feature is prvided t prevent large currents frm flwing thrugh the MOSFET if the input vltage is t lw. The resistr is placed between the IN and UL pins. The fllwing frmula is used t determine the resistr value t set the nminal (25 º) lckut threshld vltage: (see figures 6 & 7 fr temperature characteristics) R UL = (1kΩ ) 1.45 ( UL 1.45) Sft Start Delay An external capacitr between AP and the input vltage may be used t set a turn n delay time. See figure 4. TON(mS) ss(nf) At start up, the vltage acrss the capacitr is apprximately zer, the vltage at the AP pin is apprximately the input vltage, and the MOSFET is turned ff. The 128 AP pin prvides a current sink (apprx. 2uA) t charge the capacitr. The 128 turns the MOSFET n when the vltage acrss the capacitr reaches apprximately 2.7. Table 4: Under vltage Lckut Threshld R UL TEMP SYMBOL MIN TYP MAX UNITS 13.6K 85 º IN 12. - 14. 13.6K 25 º IN 11. - 13. 13.6K -55 º IN 1. - 12. 7K 85 º IN 22. - 24. 7K 25 º IN 21. - 23. 7K -55 º IN 19.5-21.5 Figure 1: Typical Applicatin 22 Device Engineering Inc. Page 3 f 5
UL utff vs Temperature Reference ltage vs Temperature UL ltage () 3 25.41 25 22.8 24.1 2.58 2 15 13.1 13.7 12.5 11.21 1 5-1 -5 5 1 15 Temp () 13.6K 7K Reference ltage (). 1.8 1.57 1.65 1.6 1.47 1.4 1.345 1.2 1.8.6.4.2-1 -5 5 1 15 Temp () Figure 2: Typical UL cutff vltage by temperature fr Ruvl = 7K and Ruvl = 13.6K Figure 3: Typical UL Reference ltage vs. Temperature. 4 4.5 Input t ON 3 NON 25 t ON Figure 4. Turn On Time Figure 5. Lgic ntrl ( NON pin) 4 DEI128 +5 Input 25 2ms 2ms t s NU 1K NU OMX Figure 6. Oversht and Settling 1% Figure 7. Undervltage Lgic 22 Device Engineering Inc. Page 4 f 5
Package haracteristics: Figure 8: 8 Lead SOI Outline Drawing Misture Sensitivity: JEDE J-STD-2A MSL 1 Table 7: 8 LD SOI Thermal haracteristics Theta jc Junctin t ase 4 /W Theta ja Junctin t Ambient 135 /W 4 layer bard T j-max Max Junctin Temperature 125 Table 8: Ordering Infrmatin Part Number Marking Package Temp DEI128 SES DEI128 8-lead SOI -55 / +85 DEI reserves the right t make changes t any prducts r specificatins herein. DEI makes n warranty, representatin, r guarantee regarding suitability f its prducts fr any particular purpse. 22 Device Engineering Inc. Page 5 f 5