a FEATURES kb Transmission Rate ADM: Small (. F) Charge Pump Capacitors ADM3: No External Capacitors Required Single V Power Supply Meets EIA-3-E and V. Specifications Two Drivers and Two Receivers On-Board DC-DC Converters 9 V Output Swing with V Supply Low Power BiCMOS:. ma I CC 3 V Receiver Input Levels APPLICATIONS Computers Peripherals Modems Printers Instruments GENERAL DESCRIPTION The ADM/ADM3 is a two-channel line driver/ receiver pair designed to operate from a single V power supply. A highly efficient on-chip charge pump design permits levels to be developed using charge pump capacitors as small as. µf. The capacitors are internal to the package on the ADM3 so no external capacitors are required. These converters generate ± V output levels. The ADM/ADM3 meets or exceeds the EIA-3-E and V. specifications. Fast driver slew rates permit operation up to kb while high-drive currents allow for extended cable lengths. An epitaxial BiCMOS construction minimizes power consumption to mw and also guards against latch-up. Overvoltage protection is provided allowing the receiver inputs to withstand continuous voltages in excess of ± 3 V. In addition, all pins contain ESD protection to levels greater than kv. The ADM is available in 6-lead DIP and both narrow and wide SOIC packages. The ADM3 is available in a -lead DIP package. High-Speed, V,. F CMOS Driver/Receivers ADM3 6V FUNCTIONAL BLOCK DIAGRAMS C+ C T IN T T OUT R OUT R R IN +V TO +V DOUBLER +V TO V INVERTER ADM V INPUT 6V * 4k PULL-UP RESISTOR ON EACH INPUT. ** k PULL-DOWN RESISTOR ON EACH INPUT. T IN T T OUT R OUT R R IN DO NOT MAKE CONNECTIONS TO THESE PINS V POWER +V POWER C+ C V INPUT ADM3 * * * 4k PULL-UP RESISTOR ON EACH INPUT. ** k PULL-DOWN RESISTOR ON EACH INPUT. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 96, Norwood, MA 6-96, U.S.A. Tel: 7/39-47 World Wide Web Site: http://www.analog.com Fax: 7/36-73 Analog Devices, Inc.,
ADM/ADM3 SPECIFICATIONS ( = V %, (ADM C C4 =. F). All Specifications T MIN to T MAX, unless otherwise noted) Parameter Min Typ Max Unit Conditions/Comments Output Voltage Swing ± ± 9 V = V ± %, T OUT, T OUT Loaded with 3 kω to Output Voltage Swing ± ± 9 V = V ± %, T A = C, T OUT, T OUT Loaded with 3 kω to Power Supply Current. 6. ma No Load, T IN, T IN = or T IN, T IN = Input Logic Threshold Low, V INL. V T IN Input Logic Threshold High, V INH.4 V T IN Logic Pull-Up Current µa T IN = V Input Voltage Range 3 +3 V Input Threshold Low.. V Input Threshold High.6.4 V Input Hysteresis..4. V Input Resistance 3 7 kω T A = C to C Output Voltage Low, V OL.4 V I OUT =.6 ma Output Voltage High, V OH 3. V I OUT =. ma Propagation Delay.3 µs to TTL Transition Region Slew Rate V/µs R L = 3 kω, C L = pf Measured from +3 V to 3 V or 3 V to +3 V Baud Rate kb R L = 3 kω, C L = nf Output Resistance 3 Ω = = = V, V OUT = ± V Output Short Circuit Current ± ±6 ma Specifications subject to change without notice. ABSOLUTE MAXIMUM RATINGS* (T A = C unless otherwise noted).......................................... 6 V............................ (.3 V) to +4 V................................. +.3 V to 4 V Input Voltages T IN..........................3 V to ( +.3 V) R IN....................................... ± 3 V Output Voltages T OUT................... (, +.3 V) to (,.3 V) R OUT........................3 V to ( +.3 V) Short Circuit Duration T OUT................................. Continuous Power Dissipation N-6 DIP................................ 47 mw R-6N SOIC............................. 6 mw R-6W SOIC............................. mw N- DIP................................ 9 mw Thermal Impedance N-6 DIP................................ 3 C/W R-6N SOIC............................. C/W R-6W SOIC............................. C/W N- DIP................................ C/W Operating Temperature Range Commercial (J Version).................. C to 7 C Storage Temperature Range............ 6 C to + C Lead Temperature Soldering Vapor Phase (6 sec)......................... C Infrared ( sec)............................. C ESD Rating................................ > V *This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. ORDERING GUIDE Model Temperature Range Package Option ADMJN C to 7 C N-6 ADMJRN C to 7 C R-6N ADMJRW C to 7 C R-6W ADM3JN C to 7 C N-
ADM3 DIP/SOIC PIN CONFIGURATIONS DIP PIN FUNCTION DESCRIPTION Mnemonic Function Power Supply Input V ± %. Internally Generated Positive Supply (+ V nominal). Internally Generated Negative Supply ( V nominal). Ground Pin. Must be connected to V. C+ ADM External Capacitor, (+ terminal) is connected to this pin. ADM3: The capacitor is connected internally and no external capacitor is required. C ADM External Capacitor, ( terminal) is connected to this pin. ADM3: The capacitor is connected internally and no external capacitor is required. ADM External Capacitor, (+ terminal) is connected to this pin. ADM3: The capacitor is connected internally and no external capacitor is required. ADM External Capacitor, ( terminal) is connected to this pin. ADM3: The capacitor is connected internally and no external capacitor is required. T IN Transmitter (Driver) Inputs. These inputs accept levels. An internal 4 kω pull-up resistor to is connected on each input. T OUT Transmitter (Driver) Outputs. These are levels (typically ± V). R IN Receiver Inputs. These inputs accept signal levels. An internal kω pull-down resistor to is connected on each of these inputs. Receiver Outputs. These are levels. R OUT 6V C+ C T IN T T OUT R OUT R R IN C+ 6 C 3 4 ADM 4 3 T OUT R IN T OUT 6 7 TOP VIEW (Not to Scale) 9 R OUT T IN T IN +V TO +V DOUBLER +V TO V INVERTER ADM V INPUT 6V * 4k PULL-UP RESISTOR ON EACH INPUT. ** k PULL-DOWN RESISTOR ON EACH INPUT. * 3 T IN T T OUT R OUT R R IN DO NOT MAKE CONNECTIONS TO THESE PINS V POWER +V POWER Figure. Typical Operating Circuits T IN T IN R OUT R IN T OUT 3 4 ADM3 9 7 6 T OUT 6 TOP VIEW (Not to Scale) C+ 7 9 4 3 C C+ C V INPUT ADM3 * 4k PULL-UP RESISTOR ON EACH INPUT. ** k PULL-DOWN RESISTOR ON EACH INPUT. *
ADM3 Typical Performance Characteristics Tx O/P HI Tx O/P HI LOADED, V Tx O/P V SLEW RATE V/ s 3 4. LOAD CURRENT ma 3 TPC. Charge Pump, vs. Current HIGH-TO-LOW SLEW RATE LOW-TO-HIGH SLEW RATE = V R L = 3k f = khz TPC. Transmitter Slew Rate vs. Load Capacitance TPC. Transmitter Output Voltage vs. Current T T T CH.V CH.V M. s CH 6.4V LOADED SLEW RATE nf Tx O/P LO LOADED Tx O/P LO 4... V TPC 4. Transmitter Output Voltage vs. k.k k.k 3k 4 6 4 CAPACITIVE LOAD pf LOAD CURRENT ma Tx O/P V Tx O/P LO Tx O/P HI T CH.V CH.V M. s CH 6.4V UNLOADED SLEW RATE TPC 3. Transmitter Fully Loaded Slew Rate TPC 6. Transmitter Unloaded Slew Rate 4
GENERAL INFORMATION The ADM/ADM3 is an drivers/receivers designed to solve interface problems by meeting the EIA-3E specifications while using a single digital V supply. The EIA standard requires transmitters that will deliver ± V minimum on the transmission channel and receivers that can accept signal levels down to ± 3 V. The parts achieve this by integrating step up voltage converters and level shifting transmitters and receivers onto the same chip. CMOS technology is used to keep the power dissipation to an absolute minimum. The ADM3 uses internal capacitors and, therefore, no external capacitors are required. The ADM contains an internal voltage doubler and a voltage inverter which generates ± V from the V input. External. µf capacitors are required for the internal voltage converter. The ADM/ADM3 is a modification, enhancement and improvement to the AD3 AD4 family and derivatives thereof. It is essentially plug-in compatible and does not have materially different applications. CIRCUIT DESCRIPTION The internal circuitry consists of three main sections. These are: (a) A Charge Pump Voltage Converter (b) to Receivers (c) to Transmitters Charge Pump DC-DC Voltage Converter The charge pump voltage converter consists of an oscillator and a switching matrix. The converter generates a ± V supply from the input V level. This is done in two stages using a switched capacitor technique as illustrated below. First, the V input supply is doubled to V using capacitor C as the charge storage element. The V level is then inverted to generate V using C as the storage element. Capacitors C3 and C4 are used to reduce the output ripple. Their values are not critical and can be reduced if higher levels of ripple are acceptable. The charge pump capacitors C and C may also be reduced at the expense of higher output impedance on the and supplies. On the ADM3, all capacitors C to C4 are molded into the package. The and supplies may also be used to power external circuitry if the current requirements are small. S S C S3 S4 C3 = FROM DOUBLER OSCILLATOR S S C S3 S4 C4 ADM3 = () Figure 3. Charge Pump Voltage Inverter Transmitter (Driver) Section The drivers convert input levels into EIA-3-E output levels. With = + V and driving a typical EIA-3-E load, the output voltage swing is ± 9 V. Even under worst-case conditions the drivers are guaranteed to meet the ± V EIA-3-E minimum requirement. The input threshold levels are both TTL and CMOS compatible with the switching threshold set at /4. With a nominal = V the switching threshold is. V typical. Unused inputs may be left unconnected, as an internal 4 kω pull-up resistor pulls them high forcing the outputs into a low state. As required by the EIA-3-E standard the slew rate is limited to less than 3 V/µs without the need for an external slew limiting capacitor and the output impedance in the power-off state is greater than 3 Ω. Receiver Section The receivers are inverting level shifters that accept EIA-3-E input levels (± V to ± V) and translate them into V TTL/ CMOS levels. The inputs have internal kω pull-down resistors to ground and are also protected against overvoltages of up to ± 3 V. The guaranteed switching thresholds are. V minimum and.4 V maximum which are well within the ±3 V EIA-3 requirement. The low level threshold is deliberately positive as it ensures that an unconnected input will be interpreted as a low level. The receivers have Schmitt trigger input with a hysteresis level of. V. This ensures error free reception both for noisy inputs and for inputs with slow transition times. OSCILLATOR Figure. Charge Pump Voltage Doubler
ADM3 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 6-Lead Plastic DIP (N-6) PIN. (.).4 (.) 6 9.43 (.).34 (.). (.7). (.46).4 (.36).4 (.34).74 (.9) 6 9. (7.).4 (6.).3 (.) PIN.6 (.).3 (7.6). (.33). (.3).9 (4.9) MAX.. (.93). (.) (3.). (3.) MIN. (.3). (.)..7 (.77) SEATING (.4) PLANE. (.4).4 (.36).4 (.).74 (4.).497 (3.) 6-Lead Wide SOIC (R-6W).99 (7.6).94 (7.4).7 (.7).9 (.6) SEATING PLANE.49 (.6).44 (.6). (.3).7 (.) PIN 6-Lead Narrow SOIC (R-6N) 6 9.9 (.).4 (.).3937 (.).39 (9.). (.7).9 (.74) 4.9 (.).44 (6.).4 (.).6 (.7).3 (.3).96 (.) 4.99 (.).9 (.49) SEATING.99 (.). (.7).3 (.3) PLANE.7 (.9).6 (.4).4 (.). (.) -Lead Plastic DIP (N-).6 (6.9).9 (3.). (7.).4 (6.).3 (.) PIN.6 (.).3 (7.6). (.3). (.33).9 (4.9) MAX. (.93).. (.) (3.). (3.) MIN. (.3). (.)..7 (.77) SEATING PLANE. (.4).4 (.36) (.4).4 (.) C6 / (rev. A) PRINTED IN U.S.A. 6