ECEN 610 Mixed-Signal Interfaces

Spring 2014 S. Hoyos-ECEN-610 1 ECEN 610 Mixed-Signal Interfaces Sebastian Hoyos Texas A&M University Analog and Mixed Signal Group

Oversampling ADC Spring 2014 S. Hoyos-ECEN-610 2

Spring 2014 S. Hoyos-ECEN-610 3 Nyquist-rate Sampling and Over- Nyquist-rate Sampling Sampling Sampling frequency F S slightly higher than the Nyquist rate of the signal, F Nyquist = 2 f b. F S > 2 f b but F S 2 f b. Over-Sampling Sampling frequency F S much higher than the Nyquist rate of the signal, F Nyquist = 2 f b. F S >> 2 f b. The ratio M = F S /(2 f b ) is called oversampling ratio (OSR). Nyquist-rate Sampling Over-Sampling time time Definition: Oversampling Ratio (OSR) F OSR = 2 f S b

Spring 2014 S. Hoyos-ECEN-610 4 Nyquist-rate and Over-sampling Data Converters Nyquist-rate data converters Sampling frequency F S slightly higher than the Nyquist rate of the signal, F Nyquist = 2 f b. OSR is larger but close to 1 Over-sampling data converters Sampling frequency F S much higher than the Nyquist rate of the signal, F Nyquist = 2 f b OSR usually larger than 8.

Spring 2014 S. Hoyos-ECEN-610 5 Why Over-Sampling? Better SQNR Benefit of over-sampling: lower quantization noise within signal bandwidth. Assuming quantization noise is white, every time we double the sample frequency, the effective resolution increases with 3 db (0.5 bit). quan. noise that falls within frequency band of interest -Fs/2 -Fb S(f) Fs/2 The quantization noise outside of the frequency of interest could be filtered out by post digital low pass filtering. Fb quantization noise PSD 2 12 freq. * In many situations, dither is needed to make quantization white. 1 Fs

Spring 2014 S. Hoyos-ECEN-610 6 Why Over-Sampling? Better SQNR (Cont d) The higher sampling frequency, the lower inband quantization noise S(f) Signal Quantization noise Doubling sampling frequency increases equivalent resolution by 3 db. 6 bit resolution improvement means 4096 times higher clock frequency!! F S1 /2 F S2 /2 F S1 < F S2 < F S3 freq. F S3 /2 1MHz signal bandwidth needs 2 GS/s sampling for 5 extra bits?! Seems too expensive (Noise shaping is the cure )

Spring 2014 S. Hoyos-ECEN-610 7 Why Over-Sampling? Relaxed AAF Requirement Another benefit for oversampled A/D conversion is much relaxed anti-alias filter requirements. anti-alias filter for oversampled ADCs anti-alias filter for (true) Nyquist ADCs -Fs -Fs/2 -Fb Fb Fs/2 Fs Freq. For true Nyquist rate ADCs, very steep brick wall type anti-alias filters are required with large phase distortion, high power consumption, and large silicon area. In practice, Nyquist rate ADCs always have certain oversampling with practical anti-alias filters. For over-sampling ADCs, simple low order anti-alias filters could be utilized.

Spring 2014 S. Hoyos-ECEN-610 8 Anti-Alias Filter Order vs. OSR Anti-alias filter order (Butterworth type) vs. OSR maximum aliasing dynamic range F S /f b (2 OSR) [R. van de Plassche, CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters, 2 nd ed., 2003, p. 41]

Original Modulation Let s start with modulator before discussions on Σ modulator X U clock integrator Problems Output of modulation is the differentiation of signal. SNR is inversely proportional to the signal frequency. Error code during transmission causes a permanent error at the receiver output. Y integrator Spring 2014 S. Hoyos-ECEN-610 9 voltage output code Y' T S low pass filter U' X, X' U, U' Y, Y' X' time time

Spring 2014 S. Hoyos-ECEN-610 10 Modifications to the Modulation Pre-emphasis with an integrator at the input integrator clock low pass filter X integrator Y Y' integrator d dt X' Simplification of the system X integrator clock Y Y' low pass filter X' Σ modulator [Inoise et al, IRE Trans. Space Electronics and Telemetry, SET-8, Sep. 1962]

Spring 2014 S. Hoyos-ECEN-610 11 Oversampling Σ A/D Converters To obtain 14 bit resolution from an 8 bit Nyquist ADC, we need to increase the sample frequency by 4096 times! To digitize an signal with 1 MHz bandwidth, sample frequency will be 8 GHz!! The benefit of oversampling only is too limited The quantization noise is approximately white with only oversampling Could we move most of the quantization noise energy to higher frequencies and then filter out high passed quantization noise with digital low pass filter?

Spring 2014 S. Hoyos-ECEN-610 12 Oversampling Σ A/D Converters PSD useful signal quantization noise with noise-shaping quantization noise digital LPF without noise-shaping Fs/2 freq. Much lower quantization noise remains within signal of interest, thus we may get higher Signal/Quantization Noise ratio, or equivalent resolution. Sigma-delta (Σ ) modulation could shape noise energy to higher frequencies! * The terms sigma-delta (Σ ) and delta-sigma ( Σ) are both used by people, and usually are interchangable.

Spring 2014 S. Hoyos-ECEN-610 13 Σ Data Converter Summary Sigma delta modulators are based on: Oversampling Noise shaping Resolution vs. speed trade off Advantages: High Resolution, high performance possible (>20bit) Easy integration into digital CMOS processes Low precision analog circuits are needed Relaxed requirements for analog circuits Digital filters used to eliminate out-of-band quantization noise [Gabriel J. Gomez, 2000]

Spring 2014 S. Hoyos-ECEN-610 14 Oversampling Σ A/D Converters Spectrum 0 0 0 Fs 0 Fs 0 F nyst Waveform Signal Flow Action AAF Antialias Filter Σ Modulator Σ Modulator Digital Decimation LPF Decimation Filter Digital Lowpass Filter Taking 1 out of n time spectra, waveforms, and signal flow diagram of an oversampling sigma-delta ADC

Spring 2014 S. Hoyos-ECEN-610 15 Nyquist Rate A/D and D/A Converters clock analog input anti-alias filter (AAF) A/D converter digital output Nyquist-rate A/D Converter clock digital input D/A converter reconstruction filter analog output Nyquist-rate D/A Converter

Spring 2014 S. Hoyos-ECEN-610 16 Oversampling A/D and D/A Converters high speed clock M F Nyq Nyquist clock F Nyq analog input anti-alias filter (AAF) Σ modulator digital low-pass filter OSR digital output low-pass filter L th order (L+1) th order Σ A/D Converter Nyquist clock F Nyq high speed clock M F Nyq digital input OSR interpolation low-pass filter digital Σ modulator DAC analog low-pass filter analog output Σ D/A Converter L th order (L+1) th order

Spring 2014 S. Hoyos-ECEN-610 17 Oversampling Σ A/D Converters The input analog signal, with some high frequency components, is firstly filtered by the anti-alias filter. The sigma-delta modulator shapes quantization noise to higher frequencies. In signal bandwidth, noise floor is significantly suppressed. The output bit (data) stream of the sigma-delta modulator contains useful signal and high passed quantization noise. The decimation filter greatly attenuates quantization noise energy at higher frequencies, while keeps useful signal at low frequency band. In decimation filter, low pass and decimation are actually combined to efficiently utilize digital processing hardware.

Spring 2014 S. Hoyos-ECEN-610 18 Oversampling Σ A/D Converters The input analog signal, with some high frequency components, is firstly filtered by the anti-alias filter. The sigma-delta modulator shapes quantization noise to higher frequencies. In signal bandwidth, noise floor is significantly suppressed. The output bit (data) stream of the sigma-delta modulator contains useful signal and high passed quantization noise. The decimation filter greatly attenuates quantization noise energy at higher frequencies, while keeps useful signal at low frequency band. In decimation filter, low pass and decimation are actually combined to efficiently utilize digital processing hardware.

Spring 2014 S. Hoyos-ECEN-610 19 Features of Oversampling Σ A/D Converters Simple low order anti-alias filter could be utilized. Relatively simple analog circuit -- sigma-delta modulator -- is required with relaxed matching requirements. The analog circuit works at much higher clock frequency. Digital decimation filter is needed, usually implemented in hardware, not software for high throughput. 16-bit or even higher (such as 20-bit) resolution could be achieved with relatively low signal bandwidth, which is hard or even impossible to reach with Nyquist-rate ADCs. Basically, we are trading operation speed for accuracy. Large latency time due to latency time of the decimation filter.

Spring 2014 S. Hoyos-ECEN-610 20 First-Order Σ Modulator (with discrete-time integrator) analog input sampler x c (t) integrator z -1 comparator (1-bit quantizer) DAC digital output Y(n) First-order 1-bit sigma-delta modulator with discrete-time integrator

Spring 2014 S. Hoyos-ECEN-610 21 First-Order Σ Modulator (with continuous-time integrator) analog input x c (t) integrator F S /s sampler comparator (1-bit quantizer) digital output Y(n) DAC First-order 1-bit sigma-delta modulator with continuous-time integrator

Spring 2014 S. Hoyos-ECEN-610 22 Waveforms with 0 V DC Input 1.5 1 voltage 0.5 0-0.5-1 -1.5 0 5 10 15 20 25 30 35 40 45 50 feedback DAC output CT integrator output sample # The output codes oscillate between 1 and -1.

Waveforms with 1/7 V DC Input 1.5 1 voltage 0.5 0-0.5-1 -1.5 0 5 10 15 20 25 30 35 40 45 50 feedback DAC output CT integrator output sample # The output code period is 7, the sequence is [ -1, 1, -1, 1, -1, 1, 1]. Average value of the sequence is 1/7. Spring 2014 S. Hoyos-ECEN-610 23

1.5 Waveforms with 2/7 V DC Input 1 voltage 0.5 0-0.5-1 -1.5 0 5 10 15 20 25 30 35 40 45 50 feedback DAC output CT integrator output sample # The output code period is 14, the sequence is [ -1, 1, 1, -1, 1, 1, -1, 1, 1, -1, 1, 1, -1]. Average value of the sequence is 2/7. Spring 2014 S. Hoyos-ECEN-610 24

Waveforms with 3/7 V DC Input 1.5 1 voltage 0.5 0-0.5-1 -1.5 0 5 10 15 20 25 30 35 40 45 50 feedback DAC output CT integrator output sample # The output code period is 7, the sequence is [ -1, 1, 1, - 1, 1, 1, 1]. Average value of the sequence is 3/7. Spring 2014 S. Hoyos-ECEN-610 25

Waveforms with 4/7 V DC Input 1.5 1 voltage 0.5 0-0.5-1 -1.5 0 5 10 15 20 25 30 35 40 45 50 feedback DAC output CT integrator output sample # The output code period is 14, the sequence is [ -1, 1, 1, 1, -1, 1, 1, 1, 1, -1, 1, 1, 1, 1]. Average value of the sequence is 4/7. Spring 2014 S. Hoyos-ECEN-610 26

Sigma-Delta (ΣΔ) Modulator Σ z -1 V i Δ A/D D o 1 st -order ΣΔ modulator D/A Obtain noise shaping with an integrator Subtract output from the input to avoid integrator saturation Spring 2014 S. Hoyos-ECEN-610 27

Spring 2014 S. Hoyos-ECEN-610 28 Linearized Discrete-Time Model E(z) X(z) H(z) Y(z) H(z) = z 1 z 1 1 Y ( z) = H( z) [ X( z) Y( z) ] + E( z) Y Y ( z) ( ) H( z) H z = 1+ ( ) X z 1 + 1+ H z ( ) 1 1 ( z) = z X( z) + ( 1 z ) E( z) ( ) E z Signal Transfer Function : Y STF = = z 1 Delay X z NTF = ( z) ( ) Noise Transfer Function : ( z) ( ) Y E z = 1 z 1 HP Caveat: E(z) may be correlated with X(z) not white.

Spring 2014 S. Hoyos-ECEN-610 29 1 st -Order Noise Shaping PSD f m f s /2 In - band quantization noise : N e 2 2 12 π 2 3M 3 2sin π f f s 2 f N e 2 = f m 0 2 12 1 2 NTF 2 df f s = 2 f 12 1 f s 2 2sin π f 2 m df 0 f s 2 f 12 1 f s 2 m 2π f df f s 12 2f m = 2 f s 3 0 π 2 3 2 Doubling OSR (M) increases SQNR by 9 db (1.5 bit/oct).

SC Implementation C I Ф 1 C S Ф 2 V i D o Ф 2 Ф 1 +V R 1-b -V R DAC SC integrator 1-bit ADC simple, ZX detector 1-bit feedback DAC simple, inherently linear Spring 2014 S. Hoyos-ECEN-610 30

Spring 2014 S. Hoyos-ECEN-610 31 2 nd -Order ΣΔ Modulator INT1 INT2 V i z -1 z -1 A/D D o 2 D/A Signal Transfer Function : STF = z 2 Noise Transfer Function : ( ) 2 NTF = 1 z 1 In - band quantization noise : N e 2 2 12 π 4 5M 5 Doubling OSR (M) increases SQNR by 15 db (2.5 bit/oct).

Spring 2014 S. Hoyos-ECEN-610 32 2 nd -Order ΣΔ Modulator (1-Bit Quantizer) V i α z -1 β z -1 1-bit A/D D o α 1 β 1 2 1-bit D/A α + α 1 ( z) = X( z) Y + 2 2 z z ( z 1) 2 + α 1 E( z) z-plane jy Simple, stable, highly-linear Insensitive to component mismatch Less correlation b/t E(z) and X(z) (2) (2) 0 1 x

Generalization (L th -Order Noise Shaping) Modulator transfer function : ( ) L E z Y( z)= z L X( z)+ 1 z 1 ( ) π 2L ( 2L +1) M 2L +1 1 In - band quantization noise : N 2 e 2 12 π 2L ( 2L +1) M 2L +1 Doubling OSR (M) increases SQNR by (6L+3) db, or (L+0.5) bit. Potential instability for 3 rd - and higher-order singleloop ΣΔ modulators. Spring 2014 S. Hoyos-ECEN-610 33

Spring 2014 S. Hoyos-ECEN-610 34 ΣΔ vs. Nyquist ADC s ΣΔ ADC output (1-bit) Nyquist ADC output +1-1 ΣΔ ADC behaves quite differently from Nyquist converters. The digital codes only display an average impression of the input. INL, DNL, monotonicity, missing code, and etc. do not directly apply in ΣΔ converters use SNR, DR, SNDR, SFDR instead.

Spring 2014 S. Hoyos-ECEN-610 35 Tones V i = 0... T V i = 0.001... 2000*T The output spectrum corresponding to V i = 0 results in a tone at f s /2, and will get eliminated by the decimation filter. The 2 nd output not only has a tone at f s /2, but also a low-frequency tone f s /2000 that cannot be eliminated by the decimation filter.

Spring 2014 S. Hoyos-ECEN-610 36 Tones Origin the quantization error spectrum of the low-resolution ADC (1-bit in the previous example) in the ΣΔ modulator loop is NOT white, but correlated with the input signal, especially for idle (DC) inputs (R. Gray, Spectral analysis of sigma-delta quantization noise ). Approaches to whitening the error spectrum Dither add high-frequency noise in the loop to randomize the quantization error. Drawback is large dither signal consumes the input dynamic range. Multi-level quantization. Needs linear multi-level DAC. High-order single-loop ΣΔ modulator. Potentially unstable. Cascaded (MASH) ΣΔ modulator. Sensitive to mismatch.

Spring 2014 S. Hoyos-ECEN-610 37 Cascaded (MASH) ΣΔ Modulator E(z) X(z) H(z) Y(z) D/A E(z) A/D DNTF Idea: to further quantize E(z) and later subtracted in digital domain. The 2 nd quantizer can be a ΣΔ modulator as well.

Spring 2014 S. Hoyos-ECEN-610 38 2-1 Cascaded Modulator X(z) INT1 z -1 INT2 z -1 E 1 (z) Y 1 (z) z -1 Y(z) 2 D/A E 1 (z) INT3 E 2 (z) Y 2 (z) z -1 (1-z -1 ) 2 D/A DNTF

2-1 Cascaded Modulator Y 1 ( z)= z 2 X( z)+ ( 1 z 1 ) 2 E 1 ( z) z 1 Y 2 ( z)= z 1 E 1 ( z)+ ( 1 z 1 )E 2 ( z) ( 1 z 1 ) 2 Y( z)= Y 1 ( z) Y 2 ( z) ( ) 2 E 1 z = z 3 X( z)+ z 1 1 z 1 = z 3 X( z) ( 1 z 1 ) 3 E 2 ( z) ( ) 2 E 1 z ( ) z 1 1 z 1 ( ) 3 E 2 z ( ) 1 z 1 ( ) E 1 (z) completely cancelled assuming perfect matching between the modulator NTF (analog domain) and the DNTF (digital domain) A 3 rd -order noise shaping on E 2 (z) obtained No potential instability Spring 2014 S. Hoyos-ECEN-610 39

Integrator Leakage V i 1 2 H(f) e H(z) = z 1, p <1 1 1 pz jy H(f) H -1 (f) z-plane A 0 db logf 0 db 1 A logf A = 1 1 p 0 1 x Finite op-amp DC-gain introduces noise leakage into the signal band. Leakage can also result in dead zone for small input voltages. Spring 2014 S. Hoyos-ECEN-610 40

Spring 2014 S. Hoyos-ECEN-610 41 Effect of Finite Op-Amp Gain in First- Order Case NTF(z) =1 pz 1, p <1 NTF(e jω ) 2 A 2 + ω 2 The in-band noise power can be calculated from the leaky NTF and compare with the case of A =.If A>OSR, the additional noise is less than 0.2 db, which assumes a linear gain. If the gain is non-linear, the effect is much serious.

DAC Nonlinearity 2- or 3-level DAC Multi-level DAC A A D D 2-level or 3-level DAC can be made perfectly linear. Multi-bit DAC nonlinearity directly adds to the summing node, limiting the ΣΔ Modulator linearity and quantization noise performance. Multi-level DAC linearity is limited by component mismatch (10-12 bits). Spring 2014 S. Hoyos-ECEN-610 42

Spring 2014 S. Hoyos-ECEN-610 43 DAC Nonlinearity 2 nd -order ΣΔ Modulator (4-b A/D and D/A), OSR = 32, ideal SNDR 14 b [db] 0-50 -100 Ideal DAC SNDR=84.3 db [db] 0-50 -100 10-bit linear DAC SNDR=60.5 db -150 0.001 0.01 0.1 Normalized frequency 0.5-150 0.001 0.01 0.1 Normalized frequency 0.5 DAC nonlinearity causes elevated in-band noise and distortion. In general, linearity of ΣΔ Modulator is no better than that of the DAC necessary to use mismatch-shaping DAC.

Spring 2014 S. Hoyos-ECEN-610 44 Integrator Noise N 1 INT1 N 2 INT2 E 1 X(z) H(z) H(z) Y 1 (z) 2 D/A N 3 INT3 E 2 H(z) D/A Y 2 (z) INT1 dominates the overall noise Performance! Y = z 3 (X + N 1 ) + z 2 ( 1 z 1 ) N 2 z 1 ( 1 z 1 ) 2 N 3 ( 1 z 1 ) 3 E 2

Spring 2014 S. Hoyos-ECEN-610 45 DR and Power Consumption Quantization noise << thermal noise DR OSR (VDD nv kt C S dsat Small V DD ; Large OSR High DR ) 2 (Thermal noise limited) Power in SC integrator: Power = I V DD V DD V dsat 2 BW FB OSR C s FB: feedback factor CMOS scaling reduces power in later stages and decimator

Spring 2014 S. Hoyos-ECEN-610 46 Architecture Comparison Topology f s (MHz) Ideal DR(dB) Power Penalty Disadvantage 2 nd order, 1-b 128X 128 95 larger parasitic cap. high samp. Rate 2 nd 4-b, 64X 64 97 DEM, 4-b quantizer linearity 3 rd order, 1-b 64X 64 106 additional integrator stability 2-1 MASH, 1-b 64X 64 106 additional integrator mismatch

Spring 2014 S. Hoyos-ECEN-610 47 Design Highlights Low supply voltage Low power design High Linearity High dynamic range Capacitor matching sensitivity Bootstrapped switch, low voltage OTA Tapered OTAs, high g m /I D Single-bit DAC, high-gain amplifiers, linear switches, complete settling High oversampling ratio (kt/osr/c) Capacitor matching insensitive Σ architecture

Spring 2014 S. Hoyos-ECEN-610 48 MASH Σ ADC DAC f 1 f 2 X a 1 + + + + Y1 Y1 2 = z X + E Q1 (1 z -1 ) 2 + a 4 a 3 + Y2 Y2 = z -1 E Q1 + E Q2 (1 z -1 ) f 3 Quantization noise level equivalent to 3 rd order Σ Integrator coefficients scaled to limit amplifier voltage swings DAC

Spring 2014 S. Hoyos-ECEN-610 49 Operational Transconductance Amplifier 1.2V Bult, JSSC, Dec 90 Vfbp 0.95V + + 0.7V V op V on V p V n V in V ip + V i - V i + 0.25V 0V + Vcmfb Vfbn Folded-cascode with gain-boosting High gain, high speed (f u 350MHz) Wide output swing Can operate with low V DD (below 1V)

Spring 2014 S. Hoyos-ECEN-610 50 g m /I D vs f t (SPICE) 80 60 130nm 90nm f t [GHz] 40 20 180nm 0 250nm 12 16 20 24 28 g m /I D [V -1 ] Large g m /I D : low speed but power efficient Utilizing high f t in 0.13µm CMOS: g m /I D 15 20

Spring 2014 S. Hoyos-ECEN-610 51 Amplifier Gain (1 st Integrator) 100 DC gain [db] 80 60 ( 0.7V, 82dB) 0.9 0.6 0.3 0 0.3 0.6 0.9 Differential output voltage [V] V swing = (V DD 4V dsat ) 80dB DC gain at ±0.7V

Spring 2014 S. Hoyos-ECEN-610 52 Switches V DD φ 1 10 Abo, JSSC, May 99 C1 C2 C3 Switch R (Ω) 5 φ 1 φ 1 Vin Vout 0 0.1 0.65 1.1 Vin(V) (89.6µm/0.14µm) Vin φ φ Vout PMOS: 3.42µm/0.14µm NMOS: 1µm/0.14µm R (Ω) 900 700 500 0 0.6 1.2 Vin(V)

Spring 2014 S. Hoyos-ECEN-610 53 Power Distribution Comparator 1% 1% Clock Generator 3 rd Integrator 14% 26% 2 nd Integrator 58% 1 st Integrator

Spring 2014 S. Hoyos-ECEN-610 54 Σ Chip Micrograph Clk Generator Comparator Input Int 1 Int 2 Int 3 Bypass Capacitors 1.4mm X 1.8mm 0.13µm 6-Metal 1-P digital CMOS process B. Tsang, Y. Chiu, B. Nikolić, A 1.2V, 10.8mW, 500kHz Σ Modulator with 84dB SNDR and 96dB SFDR

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Spring 2014 S. Hoyos-ECEN-610 57 SNDR, SFDR and HDs f in = 200kHz, f s = 64MHz SNDR, SFDR, HD 2, HD 3 (db) 100 80 60 40 20 0 SFDR HD 2 SNDR HD 3-80 -60-40 -20 0 Input Level (dbfs)

Spring 2014 S. Hoyos-ECEN-610 58 Σ Performance Summary Sampling Frequency 64 MHz Oversampling Ratio (M) 64 Signal Bandwidth (BW) 500kHz References 1.2V/0V Maximum Input Dynamic Range Peak SNR/SNDR Peak SFDR Power 1V pp 84dB 84dB/84dB 97dB 10.8mW Supply Voltage 1.2V Process Technology 0.13µm CMOS

Spring 2014 S. Hoyos-ECEN-610 59 Performance Comparison Power FOM = 2 ENOB 2 BW FOM [pj/conv-step] 100 10 1 0.1 SC Sigma-delta with >80dB SNDR 75 85 95 105 SNDR [db] ISSCC 1996-2005 This work VLSI 1996-2005 CICC 2001-2005

Spring 2014 S. Hoyos-ECEN-610 60 FOM vs V DD FOM [pj/conv-step] 10 SC Sigma-delta with > 80dB SNDR 5 ISSCC VLSI CICC This work 0 0 1 2 3 4 5 V DD [V] ISSCC (1996-2005), VLSI (1996-2005), CICC (2001-2005) Scaling technology improves FOM

Spring 2014 S. Hoyos-ECEN-610 61 Conclusions Low-voltage, low-power Σ modulator in 0.13µm CMOS High dynamic range, high-linearity Σ modulator with 1.2V supply High-gain and low-power OTA in 0.13µm CMOS with 1.2V supply Scaling of technology improves FOM

Spring 2014 S. Hoyos-ECEN-610 62 CT Bandpass ΣΔ Modulator LC, OP-RC E(s) X(s) H(s) Y(s) T +V R -V R t D/A ( ) H s = Resonator: s 2 + ω0s ω0 s + ω Q 2 0 Integrator is replaced by a CT high-q resonator. Comparator and DAC still work in discrete time. Integration is performed over the entire clock period of DAC needs return-to-zero (RZ) coding to maintain constant pulse width.

Spring 2014 S. Hoyos-ECEN-610 63 STF and NTF ( ) H s = ( ) = X( s) Y s s 2 + ω0s ω0 s + ω Q ( ) H( s) H s 1+ ( ) + E s ω s STF = 2 2 s + ω s + ω 0 0 0 2 0 1 1+ H s BP ( ) Linear Scale 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 STF NTF 2 ω0 s + s + ω Q NTF = 2 2 s + ω s + ω 0 0 2 0 BS 0.2 0.1 10-1 10 0 ω/ω 0 10 1 QE shaped by the notch filter

Spring 2014 S. Hoyos-ECEN-610 64 Example Ref: R. Schreier et al., "A 10-300-MHz IF-digitizing IC with 90-105-dB dynamic range and 15-333-kHz bandwidth," JSSC, vol. 37, pp. 1636-1644, issue 12, 2002.

Spring 2014 S. Hoyos-ECEN-610 65 Example f s = 8-32 MHz f center = f s /8 BW = 4-333 khz DR = 90-105 db AGC range = 12 db NF = 8 db IIP3 = -1 dbm 0.35-μm BiCMOS V DD = 3 V P(A) = 50 mw P(D) = 15-25 mw

Spring 2014 S. Hoyos-ECEN-610 66 Example Multi-resonator (LC, active-rc, SC) loop-filter with offset notch frequencies maximally suppresses the in-band quantization noises.

Spring 2014 S. Hoyos-ECEN-610 67 References 1. B. E. Boser et al., JSSC, vol. 23, pp. 1298-1308, issue 6, 1988. 2. B. H. Leung et al., JSSC, vol. 23, pp. 1351-1357, issue 6, 1988. 3. B. P. Brandt et al., JSSC, vol. 26, pp. 1746-1756, issue 12, 1991. 4. F. Chen et al., JSSC, vol. 30, pp. 453-460, issue 4, 1995. 5. T. L. Brooks et al., JSSC, vol. 32, pp. 1896-1906, issue 12, 1997. 6. A. K. Ong et al., JSSC, vol. 32, pp. 1920-1934, issue 12, 1997. 7. S. A. Jantzi et al., JSSC, vol. 32, pp. 1935-1950, issue 12, 1997. 8. A. Yasuda et al., JSSC, vol. 33, pp. 1879-1886, issue 12, 1998. 9. A. R. Feldman et al., JSSC, vol. 33, pp. 1462-1469, issue 10, 1998. 10.H. Tao et al., JSSC, vol. 34, pp. 1741-1752, issue 12, 1999. 11.E. J. van der Zwan et al., JSSC, vol. 35, pp. 1810-1819, issue 12, 2000. 12.I. Fujimori et al., JSSC, vol. 35, pp. 1820-1828, issue 12, 2000. 13.Y. Geerts et al., JSSC, vol. 35, pp. 1829-1840, issue 12, 2000. 14.T. Burger et al., JSSC, vol. 36, pp. 1868-1878, issue 12, 2001. 15.K. Vleugels et al., JSSC, vol. 36, pp. 1887-1899, issue 12, 2001.

Spring 2014 S. Hoyos-ECEN-610 68 References 16.S. K. Gupta et al., JSSC, vol. 37, pp. 1653-1661, issue 12, 2002. 17.R. Schreier et al., JSSC, vol. 37, pp. 1636-1644, issue 12, 2002. 18.Y.-I. Park et al., CICC, 2003, pp. 115-118. 19.W. Xuesheng et al., CICC, 2004, pp. 523-526.

Spring 2014 S. Hoyos-ECEN-610 69 Continuous Time ΣΔ Modulators Continuous-time equivalent of the discrete-time modulators. Although the loop filter is a continuous-time filter, the modulator still discrete because the output is discrete data.

Spring 2014 S. Hoyos-ECEN-610 70 Feedback DAC In DT modulators, the feedback DAC gives sampled data to the DT loop filter. However, in CT implementations, the DAC should provide the CT loop filter with CT data. DAC should convert the DT data into CT pulses. Most commonly used DAC waveforms are rectangular DAC pulses. They can be easily generated and loop filter coefficients can be obtained in a straightforward manner.

Spring 2014 S. Hoyos-ECEN-610 71 Feedback DAC Typical DAC Rectangular Pulses

Spring 2014 S. Hoyos-ECEN-610 72 Equivalence of Continuous- Time & Discrete-Time ΣΔ The key feature of the ΣΔ modulator is the noise shaping. To achieve equivalence between a continuous-time and discretetime implementations, NTF should be the same. How can we realize the same NTF using continuous-time and discrete-time loop filters? The NTF is mainly determined by the transfer function of the loop filter and the feedback DAC!

Spring 2014 S. Hoyos-ECEN-610 73 Impulse Invariant Transformation Transformations can be easily applied by decomposing the original DT (Z-domain) loop filter into partial fractions and use S- domain equivalences for the Z-domain poles to get the CT loop filter.

Spring 2014 S. Hoyos-ECEN-610 74 CT-DT equivalents for rectangular feedback DACs

Spring 2014 S. Hoyos-ECEN-610 75 Inherent Anti-aliasing According to impulse invariant, the above two loops are equivalent, L(z) = 1 / (1 + H(z))!

Spring 2014 S. Hoyos-ECEN-610 76 Inherent Anti-aliasing For CT case

Inherent Anti-aliasing Spring 2014 S. Hoyos-ECEN-610 77

Spring 2014 S. Hoyos-ECEN-610 78 Continuous Time vs. Discrete Time Sampling Frequency Continuous Time ΣΔ Not limited by amplifiers GBW Power Consumption Lower (No high GBW required!) Higher Discrete Time ΣΔ Limited by GBW of loop filter amplifiers Anti-aliasing Inherent Needed explicitly before the ADC Sampling Errors Shaped by loop filter Appear directly at ADC output Clock Jitter Loop Delay Rise-Fall Time Asymmetry Sensitivity to Process variations Sensitive to clock jitter in feedback DAC Modify the loop filter poles and zeros Yield even order harmonics in the DAC feedback signal Absolute RC (or Gm/C) values can vary by 30 % Robust to Clock Jitter No effect No effect Capacitance ratios can be as accurate as 0.01!

Continuous-Time Sigma Delta ADCs: A Design Perspective Spring 2014 S. Hoyos-ECEN-610 79

Spring 2014 S. Hoyos-ECEN-610 80 NTF Optimization NTF can be optimized to reduce the overall noise power in the band of interest by adding local resonators. Local resonators distribute the NTF zeros over the band of interest, rendering the pure differential NTF into an inverse Chebyshev response flat over the band of interest

NTF Optimization Spring 2014 S. Hoyos-ECEN-610 81

Spring 2014 S. Hoyos-ECEN-610 82 NTF Optimization Optimized NTF can be obtained automatically using the Delta-Sigma Toolbox by Richard Schreier: H = synthesizentf(modulator Order, OSR,1) By adding the argument 1 instead of 0 to the synthesizentf command, the realized NTF, based on the given order and oversampling ratio (OSR), is optimized and its zeros are distributed over the band of F b = F s /(2 OSR). R. Schreier,.The Delta-Sigma Toolbox 5.1,. http://www.mathworks.com/, 2000.

Spring 2014 S. Hoyos-ECEN-610 83 Sensitivity to RC variations One of the main challenges in designing continuous-time ΣΔ ADCs. In today s IC technologies, variations of absolute R and C values can be as high as ±15 %. Thus, RC products can vary by ±30% As absolute RC values increase, the integrator gains decrease and hence the noise shaping becomes weaker yielding lower SNR. As absolute RC values decrease, the integrator gains increase making the noise shaping more steep and hence SNR increases. However, at certain limit, the system goes unstable and SNR falls. The most critical RC variation is in the RC time constant associated with the local feedback path(s).

Spring 2014 S. Hoyos-ECEN-610 84 Sensitivity to RC variations The effect of RC variation can be compensated by using tuning through an additional bank of capacitors. This adds extra cost to the design. Especially that fine tuning steps add more cost and area requirements on the design. Thus, the design should be inherently robust to RC variations as much as possible to minimize the requirements on the additional tuning capacitor array. The values of the local feedback factors can be optimized to obtain a flat SNR response over wider range of absolute time constant variations! This comes of course at the expense of sacrificing few dbs from the achievable SNR

Sensitivity to RC variations 100 SNDR variation vs Normalized Time Constant Acheivable SNDR Vin=-3 dbfs, db 80 60 40 20 0-20 -40-60 A 15% variation in the RC (or Gm/C) product would yield more than 10 db of performance degradation 0.8 1 1.2 1.4 1.6 1.8 2 Normalized RC Time-Constant (Nominal value = 1) Spring 2014 S. Hoyos-ECEN-610 85

Sensitivity to RC variations 100 SNDR variation vs Normalized Time Constant Acheivable SNDR Vin=-3 dbfs, db 80 60 40 20 0-20 -40-60 Flat SNR over the range of 0.9 to 1.2. At Normalized Time Constant of 1.05, ±15% variations in the RC (or Gm/C) product can be tolerated with stable performance 0.8 1 1.2 1.4 1.6 1.8 2 Normalized RC Time-Constant (Nominal value = 1) Spring 2014 S. Hoyos-ECEN-610 86

Spring 2014 S. Hoyos-ECEN-610 87 Integrator Saturation Feed-forward and feed-back coefficients can be scaled so that the full swing at the output of each integrator is utilized without clipping by saturation limits.

Spring 2014 S. Hoyos-ECEN-610 88 Integrator Saturation Steps: Initially let f 1 = f 2 = f 3 = = f n = 1. Apply an input Sinusoid that achieves the maximum SNR. Calculate the scaling coefficient f i of each stage i such that: f i = maximum output of i th integrator desired maximum output swing of i th integrator Try to keep a room of 8-10% of the output swing for other inaccuracies (e.g. RC variations) or coarse filtering before the ADC (if used in a wireless receiver).

Spring 2014 S. Hoyos-ECEN-610 89 Noise Budgeting Main Noise Sources in the ADC: Quantization noise. Thermal noise. Jitter induced errors. Nonlinearity induced distortion. Quantization errors. DAC mismatch errors. If any of these noise sources is assigned x% noise power in the total budget, the SNR w.r.t. this error can be calculated as follows: SNR = Dynamic Range (db) 10*Log (x/100).

Spring 2014 S. Hoyos-ECEN-610 90 Noise Budgeting Typical Noise budget for a 5 th order 25 MHz ADC operating at sampling frequency of 400 MHz to achieve 10-bit resolution.

Final Project Overview Spring 2014 S. Hoyos-ECEN-610 91

Motivation of the Project Spring 2014 S. Hoyos-ECEN-610 92

5th Order Feed-Back CT ΣΔ Spring 2014 S. Hoyos-ECEN-610 93

STF Inherent Blocker Filtering Spring 2014 S. Hoyos-ECEN-610 94

GSM Blocking Requirements Spring 2014 S. Hoyos-ECEN-610 95

Spring 2014 S. Hoyos-ECEN-610 96

Spring 2014 S. Hoyos-ECEN-610 97 Single Tone Test with 3 In- Band Blockers