Application TOP. Symbol Parameter Ratings Units V DS Drain to Source Voltage 20 V V GS Gate to Source Voltage ±12 V Drain Current -Continuous T

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FDZ93P P-Channel.5V Specified PowerTrench BGA MOSFET V,.6A, 6mΩ Features Max r DS(on) = 6mΩ at V GS =.5V, I D =.6A Max r DS(on) = 7mΩ at V GS =.5V, I D = 3.6A Occupies only.5 mm of PCB area. Less than 5% of the area of SSOT-6. Ultra-thin package: less than.8 mm height when mounted to PCB. Outstanding thermal transfer characteristics: times better than SSOT-6. Ultra-low Qg x r DS(on) figure-of-merit. RoHS Compliant. GATE BOTTOM General Description November 6 Combining Fairchild's advanced.5v specified PowerTrench process with state of the art BGA packaging process, the FDZ93P minimizes both PCB space and r DS(on). This BGA MOSFET embodies a breakthrough in packaging technology which enables the device to combine excellent thermal transfer characteristics, high current handing capability,ultra-low profile packaging, low gate charge, and low r DS(on). Application Battery management Load switch Battery protection TOP G S D tm MOSFET Maximum Ratings T A = 5 C unless otherwise noted Symbol Parameter Ratings Units V DS Drain to Source Voltage V V GS Gate to Source Voltage ± V Drain Current -Continuous T I A = 5 C (Note a).6 D -Pulsed A P D Power Dissipation T A = 5 C (Note a).7 W T J, T STG Operating and Storage Junction Temperature Range 55 to +5 C Thermal Characteristics R θja Thermal Resistance, Junction to Ambient (Note a) 7 C/W Package Marking and Ordering Information Device Marking Device Reel Size Tape Width Quantity E FDZ93P 7 8mm 3 units 6 Fairchild Semiconductor Corporation

Electrical Characteristics T A = 5 C unless otherwise noted Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BV DSS Drain to Source Breakdown Voltage I D = 5µA, V GS = V V BV DSS Breakdown Voltage Temperature I T J Coefficient D = 5µA, referenced to 5 C 3 mv/ C I DSS Zero Gate Voltage Drain Current V DS = 6V, V GS = V µa I GSS Gate to Source Leakage Current V GS = ±V, V DS = V ± na On Characteristics V GS(th) Gate to Source Threshold Voltage V GS = V DS, I D = 5µA.6.8.5 V V GS(th) T J r DS(on) (note ) Gate to Source Threshold Voltage Temperature Coefficient Drain to Source On Resistance I D = 5µA, referenced to 5 C 3 mv/ C V GS =.5V, I D =.6A 36 6 V GS =.5V, I D = 3.6A 58 7 V GS =.5V, I D =.6A,T J =5 C 7 65 I D(on) On to State Drain Current V GS =.5V, V DS = 5V A g FS Forward Transconductance V DS = 5V, I D =.6A 3 S Dynamic Characteristics C iss Input Capacitance 75 pf V DS = V, V GS = V, C oss Output Capacitance 67 pf f = MHz C rss Reverse Transfer Capacitance 9 pf R g Gate Resistance f = MHz 6 Ω Switching Characteristics (note ) t d(on) Turn-On Delay Time ns V DD = V, I D = A t r Rise Time ns V GS =.5V, R GEN = 6Ω t d(off) Turn-Off Delay Time 35 ns t f Fall Time 7 3 ns Q g(tot) Total Gate Charge at V V DS = V,I D =.6A 7.5 nc Q gs Gate to Source Gate Charge V GS =.5V.5 nc Q gd Gate to Drain Miller Charge. nc mω Drain-Source Diode Characteristics I S Maximum continuous Drain-Source Diode Forward Current. A V SD Source to Drain Diode Forward Voltage V GS = V, I S =.A (Note ).7. V t rr Reverse Recovery Time 7 ns I F =.6A, di/dt = A/µs Q rr Reverse Recovery Charge 5 nc Notes: : R θja is determined with the device mounted on a in pad oz copper pad on a.5 x.5 in. board of FR- material. The thermal resistance from the junction to the circuit board side of the solder ball, R θjb is defined for reference. For R θjc the thermal reference point for the case is defined as the top surface of the copper chip carrier. R θjc and R θjb are guaranteed by design while R θja is determined by the user's board design. a. 7 C/W when mounted on a in pad of oz copper,.5 X.5 X.6 thick PCB b. 57 C/W when mounted on a minimum pad of oz copper : Pulse Test: Pulse Width < 3µs, Duty cycle <.%.

Typical Characteristics T J = 5 C unless otherwise noted r DS(ON),NORMALIZED -ID, DRAIN CURRENT (A) DRAIN TO SOURCE ON-RESISTANCE 8 6 PULSE DURATION = 3µs DUTY CYCLE = %MAX..5..5 -VDS, DRAIN TO SOURCE VOLTAGE (V) Figure..6....8 I D = -.6A V GS = -.5V V GS = -3.V V GS = -3.5V V GS = -.V r DS(ON), NORMALIZED.6 6 8 -I D, DRAIN CURRENT(A) On Region Characteristics Figure. Normalized On-Resistance vs Drain Current and Gate Voltage.6-5 -5 5 5 75 5 5 T J, JUNCTION TEMPERATURE ( o C) rds(on), DRAIN TO DRAIN TO SOURCE ON-RESISTANCE SOURCE ON-RESISTANCE (mω).6..8.. 5 5 V GS = -.V T J = 5 o C I D = -.3A PULSE DURATION = 3µs DUTY CYCLE = %MAX T J = 5 o C V GS = -.5V V GS = -3.V V GS = - 3.5V PULSE DURATION = 3µs DUTY CYCLE = %MAX 3 5 -V GS, GATE TO SOURCE VOLTAGE (V) Figure 3. Normalized On Resistance vs Junction Temperature Figure. On-Resistance vs Gate to Source Voltage -I D, DRAIN CURRENT (A) 8 6 PULSE DURATION = 3µs DUTY CYCLE = %MAX T J = 5 o C T J = -55 o C T J = 5 o C V DS =-5V.5..5..5 -V GS, GATE TO SOURCE VOLTAGE (V) Figure 5. Transfer Characteristics -IS, REVERSE DRAIN CURRENT (A).. E-3 V GS = V T J = 5 o C T J = 5 o C T J = -55 o C E-....6.8.. -V SD, BODY DIODE FORWARD VOLTAGE (V) Figure 6. Source to Drain Diode Forward Voltage vs Source Current 3

Typical Characteristics T J = 5 C unless otherwise noted -VGS, GATE TO SOURCE VOLTAGE(V) -ID, DRAIN CURRENT (A) 5 3 6 8 Q g, GATE CHARGE(nC) Figure 7. 5 r DS(on) LIMIT V DD = -5V V DD = -V V DD = -5V. -V DS, DRAIN TO SOURCE VOLTAGE (V) Gate Charge Characteristics Figure 8. Capacitance vs Drain to Source Voltage. VGS = -.5V SINGLE PULSE Rthja = 57 O C/W T A = 5 O C.. -V DS, DRAIN to SOURCE VOLTAGE (V) us ms ms ms s s DC 5 CAPACITANCE (pf) P(PK), PEAK TRANSIENT POWER (W) 3 5 5 5 f = MHz V GS = V T A = 5 o C C iss C oss C rss - - 3 t, PULSE WIDTH (s) SINGLE PULSE Rthja = 57 O C/W FOR TEMPERATURES ABOVE 5 o C DERATE PEAK CURRENT AS FOLLOWS: 5 T I = I A 5 ----------------------- 5 Figure 9. Forward Bias Safe Operating Area Figure. Single Pulse Maximum Power Dissipation NORMALIZED THERMAL IMPEDANCE, Z θjc.. DUTY CYCLE-DESCENDING ORDER D =.5...5.. SINGLE PULSE P DM t t NOTES: DUTY FACTOR: D = t /t PEAK T J = P DM x Z θja x R θja + T A E-3 - -3 - - 3 t, RECTANGULAR PULSE DURATION (s) Figure. Transient Thermal Response Curve

Dimensional Pad and Layout 5

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