Datorstödd Elektronikkonstruktion

Datorstödd Elektronikkonstruktion [Computer Aided Design of Electronics] Zebo Peng, Petru Eles and Gert Jervan Embedded Systems Laboratory IDA, Linköping University http://www.ida.liu.se/~tdts80/~tdts80 Electronics Systems 1

Goals Basic principles of computer-aided design. Digital design at high levels of abstraction. Synthesis and testability techniques. The hardware description language VHDL and its use in the design/synthesis process. Course Organization Lectures (Zebo and Petru): Introduction and basic terminology. VHDL: overview and simulation semantics. Behavioral modeling with VHDL. Structural modeling with VHDL. High-level synthesis of digital systems. Testing and design for test. 2

Course Organization (Cont d) Laboratory part (Gert): One seminar on the CAD system to be used. Lab assignments with VHDL. Literature: Z. Navabi: VHDL Analysis and Modeling of Digital Systems, or J. Armstrong and F. G. Gray: Structured Logic Design with VHDL. G. de Micheli: High-Level Synthesis of Digital Circuits. Lecture notes (www.ida.liu.se/~tdts80). Lecture I Trend in microelectronics The design process and tasks Different design paradigms Basic terminology The test problems 3

The Technological Trend # of trans. 100M 75M 50M Moore s Law (# of transistors per chip would double every 1.5 years) 25M 75 80 85 90 95 00 year Intel Microprocessor Evolution Year/Month Clock =1/tc. Transistors. Micras I4004 1971/11 108 KHz. 2300 10 I8080 1974/04 2 MHz. 6000 6 I8086 1978/06 10 MHz. 29000 3 I80286 1982/02 12 MHz. 0.13 m. 1.50 I486DX 1989/04 25 MHz. 1.2 m. 1 Intel DX2 1992/03 100 MHz. 1.6 m 0.8 Pentium 1993/03 60 MHz. 3.1 m 0.8 Pentium Pro 1995/11 200 MHz. 5.5 m 0.35 Pentium II 1998/ 450 MHz 7.5 m. 0.25 Pentium III 2000/01 1000 MHz. 28 m. 0.18 P4 2000/09 1400 MHz. 42 m. 0.18 4

Intel Microprocessor Evolution 100M 10M 1M 80486 Pentium P4 Pentium II 100K 80386 80286 10K 4004 8080 75 8086 80 85 90 95 00 year Technology Directions: SIA Roadmap Year Feature size (nm) Logic: trans/cm 2 Trans/chip #pads/chip Clock (MHz) Chip size (mm 2 ) Wiring levels Power supply (V) High-perf pow (W) Battery pow (W) 2002 2005 2008 2011 2014 130 100 70 50 35 18M 44M 109M 269M 664M 67.6M190M 539M 1523M 4308M 2553 3492 4776 6532 8935 2100 3500 6000 10000 16900 430 520 620 750 900 7 7-8 8-9 9 10 1.5 1.2 0.9 0.6 0.5 130 160 170 175 183 2 2.4 2.8 3.2 3.7 5

System on Chip (SoC) Hardware Software microprocessor 200 m+ transistors ASIC 800 MHz 2 watt with 1 volt Analog circuit Embedded memory DSP 6-8 month design time Source: S3 Source: Stratus Computers Sensor Network High-speed electronics Design Requirements Technology-driven: Greater Complexity Higher Density Increased Performance Lower Power Dissipation Market-driven: Shorter Time-to-Market (TTM) 6

The Design Challenges Complexity implication: 300 gates/person-week 15 000 gates/person-year For a 12-million gate system: 800 designers for one year $120 million design cost ($150K salary) Mixed Technologies Embed in a single chip: Logic, Analog, DRAM blocks LOGIC ANALOG DRAM Embed advanced technology blocks: FPGA, Flash, RF/Microwave Beyond Electronic MEMS Optical elements DRAM FLASH FPGA LOGIC Analog SRAM RF Logic 7

What are the Solutions? Powerful design methodology and tools. Advanced architecture (modularity). Extensive design reuse. Design Paradigm Shift Capture and Simulate The detailed design is captured in a model. The model is simulated. The results are used to guide the improvement of the design. All design decisions are made by the designers. a b c d o 8

Abstraction Hierarchy Layout/silicon level The physical layout of the integrated circuits is described. Circuit level The detailed circuits of transistors, resistors, and capacitors are described. in out Logic (gate) level The design is given as gates and their interconnections. a b c d o Abstraction Hierarchy (Cont d) Register-transfer level (RTL) Operations are described as transfers of values between registers. Algorithmic level A system is described as a set of usually concurrent algorithms. System level A system is described as a set of processors and communication channels. p clk R1 R2 O For I=0 To 2 Loop Wait until clk event and clk = 1 ; If (rgb[i] < 248) Then P = rgb[i] mod 8; Q = filter(x, y) * 8; End If; 9

Behavioral domain Gajski s Y-Chart System level RT - level Structural domain Algorithms, processes Register-Transfer Spec. Boolean Eqn. Transistor functions. Logic level Circuit level CPU, Memory, Bus ALU, Reg., MUX Gate, Flip-Flop Transistor Transistor layouts Standard-Cell/Subcell Macro-Cell, chips Board, MCMs Physical/geometrical domain The Three Domains Structural domain A component is described in terms on an interconnection of more primitive components. Behavioral domain A component is described by defining its input/output response. Physical/geometrical domain A component is described in terms of its physical placement and characteristics (e.g., shape). 10

Describe and Synthesize Description of a design in terms of behavioral specification. Refinement of the design towards an implementation by adding structural details. Evaluation of the design in terms of a cost function and the design is optimized w.r.t. the cost function. o1 = (a + b) c + d c; o2 = (d +f) c; o3 = (a + b) d + d f;... a b c d o High-Level Describe and Synthesize Description of a design in terms of behavioral specification. Refinement of the design towards an implementation by adding structural details. Evaluation of the design in terms of a cost function and the design is optimized for the cost function. For I=0 To 2 Loop Wait until clk event and clk= 1 ; If (rgb[i] < 248) Then P=rgb[I] mod 8;... p clk R enable O 11

IP-Based Design Intellectual Property: pre-designed and pre- verified building blocks. Design reuse Hard v. soft IPs Interface synthesis Verification Testing Source: VSI Alliance Basic Terminology Design A series of transformations from one represen- tation to another until one exists that can be fabricated. Synthesis Transforming one representation to another at a lower abstraction level or a behavioral representation into a structural representation at the same level. Analysis Studying a representation to find out its behavior or checking for certain property of a given representation. Simulation Use of a software model to study the response of a system to input stimuli. Verification The process of determining that a system functions correctly. Optimization The change of a design representation to a new form with improved features. 12

Design Activities Behavioral Domain Synthesis Analysis Structural Domain Refinement Optimization Abstraction Generation Extraction Physical/geometrical Domain A Typical Top-Down Design Process Informal Specification Behavioral Domain Algorithms, processes 1 Register-Transfer Spec. Boolean Eqn. Transistor functions. System level RT - level Lo gic level Circuit level Transistor Structural Domain CPU, Memory, Bus AL U, Reg., MUX Gate, Flip-Flop Transistor layouts Standard-Cell/Subcell Ma cro-c ell, chips Physical D omain Board, MCMs 13

Testing and its Current Practice To meet users quality requirements. Testing aims at the detection of physical faults (production errors/defects and physical failures). Automatic Test Equipment Testing of Mixed Technologies How to test the mixed chip? Need multiple ATE for a single chip: Logic ATE, Memory ATE, Analog ATE. Need SUPER ATE w combined capabilities. LOGIC ANALOG DRAM 14

High Performance On Chip High speed ATE substantially more expensive. ATE vs chip technology discrepancy: Tester uses 5 year old technology - Chips move to next generation every 2 years. ATE accuracy degrading: Chip cycle time will crossover ATE accuracy. Time in ns, yield loss in percent 1000 100 10 1 0,1 1980 1985 1990 1995 2000 2005 2010 2015 Year Silicon speed OTA Source: SIA Roadmap High Complexity: Bandwidth # of transistors increases exponentially. # of access port remains stable. Implication: # of transistors per pin (Testing Complexity Index) increases rapidly. Testing Complexity Index - [#Tr. per Pin] 1.60E+ 5 1.40E+ 5 1.00E+ 5 8.00E+ 5 6.00E+ 4 4.00E+ 4 2.00E+ 4 0.00E+ 0 Implications of SIA Roadmap: Testing Year F. Size [µm] 1992 0.5 1995 0.35 1998 0.25 2001 018 2004 0.12 2007 0.1 Source: W. Maly, 1996 Source: SIA Roadmap 15

Built-In Self Test (BIST) Solution: Dedicated built-in hardware for embedded test functions. No need for expensive ATE. At-speed testing. Current test possible. Support O&M. Support field test. External Test Standard Digital Tester Limited Speed/ Accuracy Low Cost-per-Pin Embedded Test (Built-in) Pattern Generation Result Compression Precision Timing Diagnostics Power Management Test Control Support for Board-level Test System-Level Test Memory Logic. Mixed- Signal I/Os & Interconnects Source: LogicVision Challenges to the CAD Communities System specification with very high-level languages. Modeling techniques for heterogeneous system. Testing must be considered during the design process. Design verifications -> get the whole system right the first time! Very efficient power saving techniques. Global optimization. 16

The Electronics System Designer Low cost High perf. Low pow Good testability X- ability Conclusion Remarks Much of design of digital systems is managing complexity. What is needed: new techniques and tools to help the designers in the design process, taking into account different aspects. We need especially design tools working at the higher levels of abstraction. If the complexity of the microelectronics technology will continue to grow, the migration towards higher abstraction level will continue. 17