Ring Oscillator Using Replica Bias Circuit

2012 2013 Third International Conference on Advanced Computing & Communication Technologies Design and Analysis of High Performance Voltage Controlled Ring Oscillator Using Replica Bias Circuit Sheetal Soni Research scholar, ITM Universe Gwalior, India acronyms shantanu.soni25@gmail.com Ajay Yadav Research scholar, ITM Universe Gwalior, India ajaysy.yadav@gmail.com Shyam Akashe Associate Professor, ECED ITM University Gwalior, India shyam.akashe@yahoo.com Abstract In present paper, extremely robust design of Ring oscillator using various circuitry and differential stages of cmos inverter have been presented. In this design improvement in power consumption and several other parameters viz. slew rate, transconductance, leakage power and leakage current has been achieved by varying the input voltage. This paper describes power consumption variation of [2.811 to1.283] mw by varying input voltage from [1.8 to1.0] V at 180nm technology and improved power consumption of [190.12 to 48.40] μw by varying input voltage from [1.7 to 0.7] V at 45nm technology with the generation of rapid frequency of 2.4 GHz. In this context, we have simulated a high speed ring oscillator using cascaded differential five stage delay cells by applying DC inversion, a biasing circuit and a tuning circuit using the cadence virtuoso tool, which is exceedingly applicable in ultra high speed Wi-Fi communications. Keywords- Ring oscillator, CMOS inverter, Differential stages and biasing circuitry. I. INTRODUCTIONN In present era almost all electronic and optical system shows the oscillatory behavior and voltage controlled oscillators have become the most indispensible and inevitable component of all analog and digital communication systems. Two most commonly used VCOs are LC tank and CMOS ring oscillators [1]-[4]. Ring oscillator based on CMOS technology had no requirement of inductor on chip and exhibits wide tuning range of frequency of GHz range[5]-[6] and CMOS technology is upper hand in terms of its less power consumption and a broad tuning range of operating frequency [7]-[10]. A block diagram of five-stage single endedd ring oscillator is depicted below in figure 1: Figure 1. Single ended five stage voltage controlled ring oscillator The necessary condition to oscillate is unity voltage gain provided that phase shift of 2, which can be achieved by providing /N phase shift followed by dc inversion [11]. Assuming td is the delay of each stage the signal must go through each stage twice to achieve total period of 2N. Hence oscillation frequency may be given as: Where N is the number of stages [8], [12]. Here in this paper we have used the VCO using the differential stages because of the fact that differential output has the property to reduce noise from various sources like from the power supply and common mode noise. Which is shown in Figure 2: Figure 2. 5 stages differential voltage controlled ring oscillator Voltage controlled ring oscillator has a significant application in phase lock loop devices because of the fact that frequency of oscillation is proportionate to the tail current of the differential rings[13]-[14]. Static, dynamic and leakage power are three significant power consumption factors that contribute the overall power consumption of any VLSI circuit. Static power consumption proceeds by all DC sources and without happening of any switching activity. Dynamic power can be contributed from charging and discharging phenomenon of load capacitance and leakage power is the byproduct of leakage current from sub threshold, gate, and reverse biased junctions[9]-[10], [15]. The aim of this paper is to overcome the tradeoff between power dissipation and noise and rapid frequency of 2.4 GHz can be generated at 45 nm scale using differential stages. 978-0-7695-4941-5/12 978-0-7695-4941-5/13 $26.00 2012 2013 IEEE DOI 10.1109/ACCT.2013.44 186 182

II. CIRCUIT DISCRIPTION A. Delay cell: CMOS inverter can be used as a delay element which is cascaded throughout the circuit to provide DC inversion [16]. In this paper the delay cell is designed by the five CMOS transistors which consume the power of 48 μw. Power can be calculated by using the formula in equation (2). So we can obtain the IBIAS = 0.014 ma Professor Bosco leung has proposed these steps in VLSI for wireless communications in section 8.4.2 [16], [17]-[18]. The circuit diagram of a single delay cell is shown below: of biasing Circuit Figure 4. Schematic C. Tuning circuit: Tuning circuit is designed here to conserve the effect of frequency variations, Here in present paper we have chosen the tuning voltage range from 0 V to 0.7 V i.e. the corresponding values of V tune (min) = 0 V and V tune (max) = 0.7 V. Gain of Ring oscillator can be given as : Figure 3. Schematic of the delay cell B. Biasing circuit: A constant biasing scheme is most widely used. In this circuit we have used the more complicated replica biasing scheme because of having the advancement that VCO becomes less susceptible to thermal and other various types of variations [19]-[20] that are made on circuit, it also has the benefit to maintain the Vswing voltage to a constant value. For a high frequency operating region of 2.4 GHz and avoiding the inconsistency of the tuning current to perpetuate the voltage dropp constant across current sources a replica bias played a significant role here in our circuit. Figure 5. Schematic of the tuning circuit 187 183

D. Overall circuit design: In this project we have used the 5 stage slow slewing saturated delay cell ring oscillator in cascaded manner with a combination of replica bias and a tuning circuit. A slow slewing saturated delay cell is used here for having a longer gate delay and it is a current based delay cell because deferential source coupled pair is used. The overall circuit with a delay cell, replica bias and tuning circuit is shown below: overall magnitude of loop function must be one and total phase difference must be equal to twice the multiple of. The oscillation frequency and minimal gain of ring oscillator can be given by correspondingly in equations (9) and (10). By using the triode equation, we can determine the size ratio (W/L) of any transistor of the circuit presented in Figure (6): Figure 6. Overall circuit of slow slewing saturated delay cell The resistance of the source coupled transistors can be adjusted by the gate voltage, which is formulated here. It can be seen in Figure (1) that two pmos transistors act as a sub-threshold forward biased diode. Gate voltage has an exponential effect on the I sd which is expressed in equation (5) below: III. RESULT AND SIMULATION In the present paper simulation results have been performed on the cadence simulation tool at with supply voltage variation of [1.8-1.0] V for the 180 nm technology and [1.7-0.7] V for the 45nm technology. Figure 7 shows the simulation result of VCO ring output which produces the frequency variation of 1.88 GHz to 2.4 GHz with the variation of the input voltage from 1.0 V to 1.7 V, which is modeled at 180 nm technology. For this reason, the resistance has to be tightly controlled while using the current controlled oscillator. So Rsd can be adjusted with the application of replica bias feedback controlled gate voltage. In the case of a linear model of ring oscillator with tranconductance parallel loaded of R & C. The gain of stages in inverting mode can be explained as: Figure 7. Output waveform of VCO at 180 nm. Technology Figure 8 shows the simulation result of VCO ring output which produces the frequency variation of 1.88 GHz to 2.4 GHz with the variation of the input voltage from 0.7 V to 1.0 V, which is modeled at 45 nm technology. According to Barkhausen criterion, the necessary condition for the oscillation of ring oscillator is given by following equations (7) and (8). We can see from here that 188 184

Figure 8. Output waveform of VCO (45 nm. technology) Figure 9 shows the output waveform of leakage power of ring VCO modeled at 45nm technology, which is evaluated as 48.62μW by cadence virtuoso tool with supply voltage of 1.2 V. Figure 11. DC Response and tranconductance (45 nm. technology) Figure 12 represents the output waveform of the slew rate of ring VCO at 45nm technology simulated on cadence virtuoso tool. Slew rate is calculated as 3.194 107. Figure 12. Slew rate of ringvco (45 nm. technology) Figure 9. Leakage Power waveform (45 nm. technology) Figure 10 represents the output waveform of leakage current having value of 42.52μA in ring VCO at 45nm technology simulated on cadence virtuoso tool. Simulation output is marked as in Figure below. Figure 13 presents here the fair voltage gain of ring VCO which shows the increasing values from [0.1331 to 0.1382] for the corresponding values of supply voltage vary from [0.3171 to 0.7] V. Figure 13. Voltage gain of ring VCO (45 nm. technology) Figure 10. Leakage current waveform (45 nm. technology) Figure 11 represents the output waveform of transconductance of ring VCO at 45nm technology simulated on cadence virtuoso tool. Simulation output 7.013 10-6 is marked as in Figure below. 185 189 Figure14 shows the Phase noise calculated for the ring VCO as shown in Figure6 which is simulated by giving it the supply voltage of.7v and the peak value we get is 7.963dBc/Hz.

Figure 14. Phase noise in ring VCO (45 nm. technology) TABLE I. VCO Circuit Present work Operating frequency (GHz) COMPARISON OF PERFORMANCE OF VCOS AT DIFFERENT TECHNOLOGIES. Input Voltage (V) Modeling Technology (nm) Overall power consumption (mw) 2.15-2.73 1.8 180 2.80 2.15-2.73 1.2 180 1.54 2.15-2.73 1.0 180 1.28 1.88-2.4 1.7 45 0.189 1.88-2.4 1.2 45 0.0486 1.88-2.4 0.7 45 0.0484 IV. CONCLUSION The Implementation of voltage controlled ring oscillator is presented here by using the five stages of slow slewing saturated delay cells at 180nm and 45nm technology. From the simulation results improvement in power consumption has achieved by varying the input voltage. We have achieved power consumption variation [2.811 to 1.283] mw with varying input voltage from [1.8 to 1.0] V at 180nm technology and improved power consumption of [190.12 to 48.40] μw with varying input voltage from [1.7 to 0.7] V at 45nm technology with the generation of rapid frequency of 2.4 GHz. V. ACKNOWLEDGEMENT The authors would like to thank ITM University and Cadence Pvt. Ltd, Bangalore. REFERENCES [1] Design of low-voltage wide tuning range cmos multipass voltagecontrolled ring oscillator by jie ren, dalhousie university halifax, nova scotia march 2011. [2] S. Y. Lee and J. Y. Hsieh, Analysis and implementation of a 0.9Vvoltage-controlled oscillator with low phase noise and low powerdissipation, IEEE Transaction on Circuits and Systems II, vol. 55,no.7, pp. 624-627, Jul. 2008. [3] B. Catli and M. M. Haskell, A 0.5V 3.6/5.2 GHz CMOS multibandvco for ultra low-voltage wireless applications, IEEE InternationalSymposium on Circuits and Systems, May 2008, pp. 996-999. [4] C. K. K. YANG, R. FARJAD-RAD, M. A. HOROWITZ, A 0.5- m CMOS 4.0-Gbit/s serial link transceiver with data recovery using oversampling, IEEE J. Solid-State Circuits, vol. 33, (1998), 713-722. [5] L. S. Paula, S. Banpi, E. Fabris, and A. A. Susin, A wide band CMOS differential voltage-controlled ring oscillators, InternationalIEEE Northeast Workshop on Circuits and System Design, Jun. 2008,pp. 9-12.2008. [6] T. Cao, D. T. Wisland, T. S. Lande, and F. Moradi, Low-voltage, low-power, and wide-tuning range VCOfor frequency modulator, IEEE Conference NORCHIP, Nov. pp. 79-84.2008. [7] H. R. Kim, C. Y. Cha, S. Min Oh, M. S. Yang, and S. G. Lee, A very low-power quadrature VCO with back-gate coupling, IEEE Journalof Solid-State Circuits, vol. 39, no. 6, Jun. 2004. [8] M. J. Deen, M. H. Kazemeini, and S. Naseh, Performancecharacteristics of an ultra-low power VCO, International Symposiumon Circuits and Systems, May 2003, pp. 697-700.2003. [9] K. Roy and S. C. Prasad, Low power CMOS circuit design, WielyPvt Ltd, India, Feb. 2002, pp. 214-219. [10] B. Bero, J. Nyathi, Bulk CMOS device optimization for highspeedand ultra-low power operations, IEEE International MidwestSymposium on Circuits and Systems, vol. 2, Aug. 2006, pp. 221 225. [11] S. Docking, M. Sachdev, A Method to Derive an Equation for the Oscillation Frequency of a Ring Oscillator, IEEE Trans. on Circuits and Systems - I: Fundamental Theory and Applications, vol. 50, 2,(2003), 259-264. [12] A. Hajimiri, S. Limotyrakis, and T. H. Lee, Jitter and phase noise inring oscillators, IEEE Journal of Solid-State Circuits, vol. 34, no. 6,pp. 790-804, Jun. 1999. [13] Docking S and Sachdev M. IEEE J Solid State Circuit, 39 (2004) 533. [14] Alioto M. and Palumbo G, IEEE Trans or Circuits and Syst I, 48 (2001) 210. [15] Sanyal A. Rastogi, A. Wei Chen Kundu, S. Computers, IEEE Transactions on July 2010, 59. [16] Design of ring oscillator based VCO written by George Lee, Professor Leung March 29, 2005 [17] C. H. PARK, O. KIM, B. KIM, A 1.8-GHz self-calibrated phase locked loop with precise I/Q matching, IEEE J. Solid-State Circuits, vol. 36, (2001), 777-783. [18] B. RAZAVI, A 2-GHz 1.6-mW phase-locked loop, IEEE J. Solid- State Circuits, vol.32,(1997), 730-735. [19] G. JOVANOVI C, M. STOJCEV, A Method for Improvement Stability of a CMOS Voltage Controlled Ring Oscillators, ICEST 2007, Proceedings of Papers, vol. 2, pp. 715-718, Ohrid, Jun 2007. [20] TODD CHARLES WEIGANDT, Low-Phase-Noise, Low-Timing- Jitter Design Techniques for Delay Cell Based VCOs and Frequency Synthesizers, PhD dissertation, University of California, Berkeley, 1998. 190 186