EMC Lessons Learnt on Gigabit Ethernet Implementation for ADAS & AV Rubén Pérez-Aranda (rubenpda@kdpof.com)
KD in a nutshell Fabless silicon vendor KD develops state of the art semiconductors for optical communications of 100 Mbps, 1 Gbps, and ngbps for Automotive applications, among others Incorporated in 2010. ~30 workers, most of them Engineers Located in Tres Cantos, Madrid, Spain ISO 9001:2015 Standardized technology: IEEE Std 802.3bv Physical Layer Specifications and Management Parameters for 1000 Mb/s Operation Over Plastic Optical Fiber KD supplies Ethernet PHY chipset for many automotive applications: HV batteries, BMS, EV, safe backbone, smart antenna modules, infotainment, ADAS, AV The key: cable harness provides galvanic isolation and is free of EMC problems Currently, Tier-1s and OEMs are implementing ECUs with KD chipset for 1 Gbps and 100 Mbps 2
Why EMC topic? ADAS & AV are emerging, demanding to communications networks: Higher speeds (e.g. 1 Gbps) Lower latencies (e.g. < 100 us) Ethernet is being positioned to be the communications technology to make the fusion of sensors, actuators and AI computing units Faster speeds make more difficult to meet the EMC constraints: Wider electromagnetic spectrum needs to be used Systems become less immune to radiated and conducted noise Systems emit noise in higher frequencies with higher power OK but is optical, why EMC? EMC specifications highly impact in: The Ethernet PHY IC design: clock strategy, data interfaces, etc. The integration of the IC at ECU level: schematic, PDN, SI, layout, etc. The components selection: clock reference, power management, filters, decoupling, etc. We will see the process to make a Gigabit Ethernet PHY EMC compliant and the lessons learnt 3
The target: GE Ethernet PHY 1000BASE-RHC PHY compliant with IEEE Std 802.3bv Optical header connector: PMD sublayer + MDI TX: driver IC (KD9101) + LED IC RX: TIA IC (KD9201) + Photodiode IC Optical lenses for light coupling Mechanical attachment, mating EMC shielding (PMD RX handles μa) Transceiver IC (KD1053): PCS and PMA sublayers Modulation, FEC, channel equalization, timing recovery, Ethernet frames en/decoding MAC layer I/F: RGMII, SGMII, etc Mixed-Signal IC: DAC, ADC, PLLs, DSP Safety sensors: voltage, temperature, Management: MDIO PTP, SyncE, 4
The reference design Objectives: To be a guide for Tier 1 of how to integrate the PHY in an ECU To solve components selection (clocks, PMIC, Cs, Rs, Ls, filters) To solve power distribution networks (decoupling, filtering, stability) To solve signal integrity To recommend PCB stack-up and layout To demonstrate full functionality (e.g. WU/Sleep) To be a technology evaluation vehicle To operate in temperature range: -40º +105 ºC To support car battery supply conditions To be EMC compliant w/o metal box PHY SyncE Power management PS filters and protections SFP I/F (SGMII, 1000Base-X) Battery Configuration Wake-up & Sleep Management I/F Indicators 5
Noise emissions compliance (EMI) RE. In front of the EUT RE. In front of the harness 1 GHz < f < 6 GHz 200 MHz < f < 1000 MHz 30 MHz < f < 200 MHz Horn antenna. V/H. 3 positions. Logo-periodic antenna. V/H. Biconic antenna. V/H. RE. In front of the harness CE. Current method CE. Voltage method 0.15 MHz < f < 30 MHz 0.15 MHz < f < 320 MHz 0.15 < f < 108 MHz Monopole antenna Current clamp LISN (AN) 6
Noise immunity compliance (EMS) RI, RF. In front of the EUT RI, RF. In front the harness RI, BCI 1 GHz < f < 6 GHz. CW, PM217 200 MHz < f < 1 GHz. CW, AM, PM18 0.1 MHz < f < 400 MHz. CW, AM Horn antenna. V/H. 3 positions. Logo-periodic antenna. V/H. Current clamp. Several positions, wires configurations. RI, Radar pulse. In front the EUT RI, Handy transmitters 1.2 1.4 GHz. 2.7 3.1 GHz. PM300 26 MHz < f < 6000 MHz, CW, AM, PM18, PM217, PM300 Horn antenna. V/H. 3 positions. Different antennas 7
Lesson 1: standards vs. OEM s specs Just an example, CISPR 25:2016, radiated emissions between 1 and 3 GHz, component level CISPR 25 specifies test and calibration methods, but only give recommendations on the limits OEMs norms are usually derived from international standards, with amendments If we combine w/c limit of several OEMs (Volvo, JLR, MBN, BMW, Ford), we have a much harder spec to meet 8
Lesson 2: the EMC qualification process M <<< N Redesign M cycles N cycles EMC Qualified EMC Compliance EMC Precompliance 1 EMC compliance session =COST 1 EMC pre-compliance laboratory 9
EMC pre-compliance: radiated emissions PSU w/ FLT SA LISN LISN LNA 40dB VBAT TEM cell GND DC-block Port 1 Port 2 EUT 50Ω load PORT RF shielding box pre-re: Near-field E/H aligned with TEM cell Far-field results can be correlated if radiative structures do not change (differential analysis) Very useful to debug PDN, SS, decoupling, layout, and noise emissions root causes High repeatability! AESIN CONFERENCE 2nd Oct 2018 10
EMC pre-compliance: conducted emissions LISN PSU w/ FLT LISN VBAT TEM cell GND EUT SA PORT RF Splitter RF shielding box pre-ce CM: 0º resistive splitter It correlates with far-field RE below 1 GHz in front of the harness It correlates with current method CE < 320 MHz pre-ce DM: Inductive 180º splitter Used together with pre-ce CM to correlate voltage method and current method CE results AESIN CONFERENCE 2nd Oct 2018 11
EMC pre-compliance: radiated immunity RF-HPA PSU RF-Switch (for PM) RF-HPAs Opt. Att. Pulses Generator SA monitor PSU DM/CM filters RF Shield with TEM CELL inside RF Generator Eth. tester connection Golden MDIO link margin monitor for sensitivity PSU (golden, DUT) 12
Lesson 3: Power supply (CM & DM) filters pre-ce CM: RGMII baseline pre-ce CM: RGMII, PS filter 13
Lesson 4: PM IC spread-spectrum PM IC simulation predicts noise reduction pre-ce CM: RGMII baseline pre-ce CM: RGMII, PS filter, PM IC SS 14
Lesson 5: DSP and RGMII spread-spectrum KD1053 IC clock architecture was designed from the beginning taking into consideration EMC performance 5 PLLs within the IC: Clean low jitter clocks: 1 PLL for DAC + 1 PLL for ADC Spread-spectrum modulated clocks: 1 PLL for DSP TX, 1 PLL for DSP RX, 1 PLL for xmii I/F TX pre-ce CM: RGMII baseline pre-ce CM: RGMII, PS filter, PM IC SS, DSP SS, I/F SS 31dB @ 125 MHz 17 db @ 500 MHz 15
Lesson 6: SGMII interface Data I/F based on SerDes may present additional advantages in EMC: Differential matched transmission lines vs. single-ended unmatched signals of RGMII Embedded clock vs. source synchronous transmission with 125 MHz clock of RGMII Reduced number of traces: 2 TX + 2 RX traces vs. 6 + 6 of RGMII pre-ce CM: RGMII baseline pre-ce CM: SGMII, PS filter, PM IC SS, DSP SS, I/F SS 16
Lesson 7: Spread spectrum is very important in high frequency pre-re TEM cell measurements show noise cleaning produced by clock SS in DSP and RGMII interface As higher the harmonic is, the effect of SS is more important Highlighted the reduction by SS for some RGMII harmonics pre-re: RGMII baseline pre-re: RGMII, PM IC SS, DSP SS, I/F SS -18dB -14dB -13dB -15dB -16dB -16dB Sinc response due to RGMII random data 17
Lesson 8: 25 MHz XTAL vs. Oscillator 25 MHz clock reference. Should we use XTAL or OSC? No easy response from EMC viewpoint XTAL: better noise emissions performance, cheaper, but it may be worse in immunity OSC: more robust against noise, but you can measure energy in harmonic +100, because very short tr/tf and MEMS based OSC? Controlled tr/tf, lower emissions with good immunity. But worse jitter, which penalizes the sensitivity pre-re: RGMII, PM IC SS, DSP SS, I/F SS OSC pre-re: RGMII, PM IC SS, DSP SS, I/F SS XTAL 18
Lesson 9: Differential strip-lines vs. micro-strips After reducing the others, noise peaks from optical transmitter interface become the most important noise Current steering differential interface implemented with micro-strip traces Common mode conversion in the GND (unavoidable, reduced with low inductance GND) Near E-field coupled into the header connector shield (bouncing) that may act as radiating structure in far-field Proposed improvement: strip-lines. To be measured soon E pre-re: SGMII, PM IC SS, DSP SS, I/F SS Micro-strips Near field probe Strip-lines AESIN CONFERENCE 2nd Oct 2018 19
Lesson 10: XTAL layout for immunity performance 20
Thank you!