Design of Low Voltage Low Power and Highly Efficient DC-DC Converters

Deign of Low Voltage Low Power and Highly Efficient DC-DC Converter Theoretical Guideline Mater thei in Electronic Sytem at Linköping Intitute of Technology by Raid Hadzimuic Reg nr: LITH-ISY-EX-3404-004 Linköping, 004

Avdelning, Intitution Diviion, Department Intitutionen för ytemteknik 581 83 LINKÖPING Datum Date 004-03-05 Språk Language Svenka/Swedih X Engelka/Englih Rapporttyp Report category Licentiatavhandling X Examenarbete C-uppat D-uppat Övrig rapport ISBN ISRN LITH-ISY-EX-3404-004 Serietitel och erienummer Title of erie, numbering ISSN URL för elektronik verion http://www.ep.liu.e/exjobb/iy/004/3404/ Titel Title Författare Author Deign av en Låg Spänning, Låg Effekt DC-DC Omvandlare med Hög Verkninggrad, Teoretika Riktlinjer Deign of Low Voltage Low Power and Highly Efficient DC-DC Converter, Theoretical Guideline Raid Hadzimuic Sammanfattning Abtract In thi thei a predefined deign parameter are ued to preent theoretical guideline for deign of low voltage, and low power DC-DC converter with high power efficiency and low level of EMI (Electro-Magnetic Interference). Thi converter i ued to alter the DC voltage upplied by the power ource. Several DC-DC converter of different type and topologie are decribed and analyzed. Switched converter of buck topology i found to atify the deign criteria mot adequately and therefore i choen a the olution for the tak of the thei. Three control cheme are analyed PWM (Pule-Width Modulation), PFM (Phae-Frequency Modulation), and Sliding control. PWM i found to be mot appropriate for implementation with thi type of converter. Further, baic operation of the buck converter which include two mode of operation CCM (Continuou-Conduction Mode) and DCM (Dicontinuou-Conduction Mode) i decribed. Power loe aociated with it are analyed a well. Finally everal technique for power converion improvement are preented. Nyckelord Keyword DC-DC, converter, low, voltage, power, CCM, DCM, PWM, pule, width, modulation

Abtract In thi thei a predefined deign parameter are ued to preent theoretical guideline for deign of low voltage, and low power DC-DC converter with high power efficiency and low level of EMI (Electro-Magnetic Interference). Thi converter i ued to alter the DC voltage upplied by the power ource. Several DC-DC converter of different type and topologie are decribed and analyzed. Switched converter of buck topology i found to atify the deign criteria mot adequately and therefore i choen a the olution for the tak of the thei. Three control cheme are analyed PWM (Pule-Width Modulation), PFM (Phae-Frequency Modulation), and Sliding control. PWM i found to be mot appropriate for implementation with thi type of converter. Further, baic operation of the buck converter which include two mode of operation CCM (Continuou-Conduction Mode) and DCM (Dicontinuou-Conduction Mode) i decribed. Power loe aociated with it are analyed a well. Finally everal technique for power converion improvement are preented. 1

1 Introduction... 4 1.1 Background... 4 1. The Tak... 6 1.3 Method... 6 1.4 Delimitation... 6 Switched DC-DC Converter... 7.1 Overview... 7. Buck Converter... 8.3 Boot Converter... 10.4 Buck-Boot Converter... 10.5 Converter Topology Selection... 11 3 Control Scheme for DC-DC Converter... 13 3.1 Pule-Width Modulation (PWM)... 13 3. Pule-Frequency Modulation (PFM)... 15 3.3 Sliding Control... 16 3.4 Control Scheme Selection... 18 4 Buck Converter, Mode of Operation... 0 4.1 Baic Theory... 0 4. Continuou-Conduction Mode (CCM)... 3 4.3 Boundary Between Continuou- and Dicontinuou-Conduction... 4 4.4 Dicontinuou-Conduction Mode (DCM)... 5 4.5 Output Voltage Ripple... 7 4.6 Deign Iue... 9 5 Source of Power Diipation... 30 5.1 Conduction Lo... 30 5. Gate Drive Lo... 31 5.3 Timing Error... 31 5.3.1 No dead-time: Short-Circuit Lo... 31 5.3. Dead-Time too Long: Body Diode Conduction... 31 5.3.3 Dead-Time too Short: Capacitive Switching Lo... 3 5.4 Stray Inductive Switching Lo... 3 5.5 Control Circuitry Operating Power... 33 6 Switching Technique... 34 6.1 Hard Switching... 34 6. Soft Switching... 35 7 Technique for High Power Efficiency... 36 7.1 Synchronou Rectification... 36 7.1.1 Synchronou Rectifier Control... 37 7. Zero Voltage Switching... 37 7.3 Adaptive Dead-Time Control... 39 7.4 Power Tranitor Sizing... 43 7.5 Gate-Drive Deign... 44

7.5.1 Determination of the Inverter Chain... 45 7.6 Concluion... 47 8 Reult... 48 3

1 Introduction 1.1 Background Adaptively regulating the power upply voltage offer ignificant energy aving due to the energy quared dependence on power upply voltage for digital circuit. However, power upply voltage reduction come at the expene of longer propagation delay of the gate. Hence, there i a trade-off between propagation delay and power conumption [3]. Performance of digital ytem ha been increaing rapidly, both due to higher clock frequencie and number of tranitor. Unfortunately, the power conumption in digital ytem ha alo increaed due to increaed number of device. Hence, the power conumption i of primary concern. Modern highperformance microproceor can conume more than 100 W and require expenive cooling and power upply ytem. The proliferation of portable device alo emphaize the need for low power diipation, to extend battery life time. The power conumption in ynchronou CMOS digital ytem i dominated by their dynamic power conumption, which i governed by the following equation Pdynamic = α Cw VDD Vwing fclk where α i the witching activity, Cw i the total witched capacitance, VDD i the power upply voltage, Vwing i the internal wing (uually equal VDD for mot CMOS circuit), and fclk i the frequency of operation. The energy i E = α Cw VDD Vwing 4

Dynamically adjuting the power upply voltage to the minimum required for a given clock frequency, enable reduced power conumption. Previou olution uing thi technique for adaptive power upply regulation demontrate converion efficiencie greater than 90% acro a wide range of regulated voltage level [6], [7], [9]. Poible power aving achievable by implementation of thi technique are hown in figure 1. Figure 1: Power aving achievable by uing adaptive power upply regulation. Thi technique i referred to a adaptive power upply regulation, and require a mechanim that track the wort cae delay path through the digital circuitry with repect to proce, temperature, and battery voltage in order to determine the minimum power upply voltage required for proper operation. Expreion wort-cae critical path refer to the phyical ignal path in the circuit with the longet propagation time delay. Model of the wort-cae critical path can be deigned uing a ring ocillator a decribed in [17]. In the literature everal example of thi power aving technique have been reported. For example it ha been applied to general purpoe microproceor and digital ignal proceing (DSP) chip for mobile and other application where minimizing energy conumption i a priority. Thee ytem commonly rely on the burty nature of their operation to dynamically adjut the peed and power upply voltage in order to minimize the energy conumed for the required computational tak. Furthermore, thee ytem employ both hardware and oftware baed cheme to monitor the computational requirement of the ytem. 5

Adaptive power upply regulation can alo be ued for power optimization baed on varying computational requirement of the part within a chip. An extreme example i to partition large block within a digital chip and to operate them at their optimum clock frequency and power upply voltage. However, the overhead aociated with communication between the block and to efficiently provide eparate power upply voltage to them i a formidable challenge. A ubet of thi example would be to identify a block within a digital chip that conume a ignificant part of the power and could operate at a lower power upply voltage. In other word, a block whoe critical delay path are much horter than the ret of the digital chip uch that, a a eparate entity, it could operate at a much lower voltage for the ame clock rate. 1. The Tak Primary tak of thi thei i to preent theoretical guideline which decribe procedure and technique for deign of variable low voltage, low power, and highly power efficient DC-DC converter with low level of EMI (Electro- Magnetic Interference). Selection of the adequate control cheme for the DC-DC converter i the econdary objective. The reult of thi work can mainly be ued for implementation in digital circuit ince thee circuit are le enitive for witching noie than their analog counterpart. It may alo be ued in wirele communication application ince EMI i kept low. A mentioned earlier, thi include general purpoe microproceor and digital ignal proceing (DSP) chip for mobile and other application where minimizing the energy conumption i a priority. 1.3 Method In order to complete the aim of thi work, comparion of previou work in thi field will be made. The outcome of thi tudy i ued to preent the adequate procedure and technique for deign of a pecific DC-DC converter which i part of an adaptive power upply regulation cheme. Analytical model of ome baic circuit relevant for thi work are preented. 1.4 Delimitation Power efficiency of the circuit i the main priority in deign proce and hould be high (around 90%). Input voltage Vin for the reference circuit i et to V and the average output voltage Vout i regulated between 1.9V and 0.9V in four approximately equal tep. The maximum output current i et to 50mA at 1.9V. 6

Switched DC-DC Converter.1 Overview The main purpoe of a DC-DC converter i to upply a regulated DC output voltage to a variable-load reitance from an untable DC input voltage. DC-DC converter are commonly ued in application requiring regulated DC power, uch a computer, medical intrumentation and communication device. DC- DC converter are alo ued to provide a table variable DC voltage for DC motor peed control application. There are three type of DC-DC converter in ue today, linear converter, witched capacitor converter (alo known a charge pump), and witched converter. Linear converter can only generate lower output voltage from the higher input voltage []. Their converion efficiency i never greater than Vout/Vin. In practice, mot linear converter operate with typical converion efficiencie of only 30% [18]. Thi i the major limitation which make linear converter not uitable for the tak of thi thei. However they are commonly ued in analog circuit to enure a contant (or nearly contant) power upply voltage. Switched capacitor converter implement witche and capacitor to perform voltage converion. Since they do not ue magnetic component like inductor the amount of EMI (Electro Magnetic Interference) i low which make thee converter uitable for application which are enitive to thi phenomenon. However, in analye preented in [4] it wa hown that thee converter are not appropriate for the application which require the output voltage to be regulated between everal different value. Switched converter operate by paing energy in dicrete packet over a witch. Hence, the output voltage can be higher, lower or inverted compared to the input voltage. They offer higher power efficiency than their linear and witched capacitor counterpart [4], [18]. However, witched converter generate ignificant amount of electrical noie caued by the witching activity. Preence of thi phenomenon known a voltage ripple i their main drawback, fortunately thi problem can be olved a it will be hown later in thi ection. 7

The output voltage in witched DC-DC converter i generally controlled uing a witching technique, a illutrated by the baic witched DC-DC converter hown in figure. Figure : Baic witched DC-DC converter. There are tree main topologie of witched DC-DC converter ued today: 1. Buck or tep-down converter are ued to produce an output voltage between ground and the input voltage.. Boot or tep-up converter operate in the oppoite manner compared to the tep-down converter generating higher voltage at the output than at the input. 3. Buck-Boot converter are ued in application where the output voltage i required to have level both higher and lower than the input voltage. The mot widely ued method for controlling the output voltage through the witch (ee figure ) i pule-width modulation (PWM). The pule-width modulation control technique maintain a contant witching frequency and varie the ratio of the charge cycle (time when the witch i on) and the dicharge cycle (time when the witch i off) a the load varie. Thi technique afford high power efficiency. In addition, becaue the witching frequency i fixed, the noie pectrum i relatively narrow, allowing imple low-pa filter technique to greatly reduce the peak-to-peak voltage ripple at the output. Thi i a reaon why, PWM i popular in telecommunication application where noie interference i of concern [].. Buck Converter A mentioned earlier, tep-down converter are ued to convert an input voltage to a lower level at the output. Baic principle of a buck topology i hown in figure 3. When the witch i in poition one, the output voltage i equal to the input voltage and when the witch i in poition two, the output voltage i equal 8

to zero. The reulting average voltage level at the output i a function of the time when the witch i in poition one and two repectively. Thi function i called duty ratio and it i defined by the expreion D = Vo/Vin, where Vo donate the average output voltage and Vin i the DC voltage generated by the power ource. Figure 3: Baic buck topology. The main problem of thi baic circuit i the voltage ripple of the output ignal of the converter. For thi reaon a LC-filter i ued to decreae the voltage ripple. Thi modified circuit i hown in figure 4. Figure 4: Buck topology, modified circuit. Since the average current through the load reitor R i approximately the ame a the average current of the inductor, the voltage Vo acro the load reitor contain le ripple. A diode i ued when the witch i in poition two. Thi allow the capacitor to be charged in both witching poition. When the witch i in poition one the energy i tranferred from the power ource to the capacitor and when the witch i in poition two the capacitor i charged with the energy tored in the inductor. Thi type of operation reult in high power efficiency for buck converter. 9

.3 Boot Converter A boot converter topology i obtained by rearranging the component of a buck converter according to figure 5. Figure 5: Boot topology. During the time the witch i cloed energy i tranferred to the inductor while the diode i preventing the capacitor to dicharge through the witch. When the witch open current through the inductor continue to flow in the ame direction a during the previou cycle. Thi forward-biae the diode and both the input voltage ource and the inductor are tranferring energy to the load. Hence, a voltage boot occur acro the load, which caue the output voltage to be higher than the input voltage. The capacitor mut be large enough to keep the output voltage approximately contant..4 Buck-Boot Converter Certain application require voltage level to be both higher and lower than the ource voltage. A olution to thi i a buck-boot converter. A imple buck-boot converter i hown in figure 6. Figure 6: Buck-Boot topology. The baic operation of a buck-boot converter i the following. When the witch i cloed energy from the ource i tranferred to the inductor and the diode i revered-biaed, thu, it i off. At the ame time the capacitor i dicharged into the output load RL and the output voltage i falling. 10

Next, the witch i open and the inductor maintain the current direction. Thi forward-biae the diode. During thi period the inductor i tranferring energy to the capacitor. In other word, the capacitor i being charged a the inductor i being dicharged, and the output voltage i riing. Previou dicuion implie, that by adjuting the on time of the witch compared to the time of one witching period, the output voltage Vo can be et to either lower or higher level than the input voltage V. If the ratio of the on time of the witch and the witching period approache zero than the output voltage alo approache zero. If the ratio approache one, than the output voltage level theoretically ha no upper limit [19]..5 Converter Topology Selection It will be hown later that in order to obtain higher power efficiencie for low voltage low power converter the diode in the converter decribed in previou ection hould be replaced by an active witch Mn a hown in figure 7 (buck cae). Figure 7: Buck converter with active witch Mn intead of diode. The baic converter topologie decribed earlier are a mall ubet of many DC- DC converter topologie that have been reported in the literature. Other important clae of converter topologie include tranformer-coupled circuit and oft-witching topologie, uch a reonant converter. Although many of thee topologie have important advantage in ome application, tranformer coupling i uually unuitable in portable ytem, and oft-witching can be obtained without the ue of reonant technique. Thu, the baic topologie are appropriate for mot portable application [4]. In buck and boot converter, a part of the output energy i upplied directly from the input ource, reducing the energy torage requirement of the inductor, and thu, it phyical ize. In a buck-boot converter, becaue none of the energy i tranferred directly, it i tranferred from the input into the inductor, and then in a eparate portion of the cycle, from the inductor to the output, a larger 11

inductor i typically required in thi circuit. Thu, the buck and boot topologie are generally preferred ince the inductor i a ignificant part of the circuit area. Becaue of it more evere inductor requirement, a buck-boot topology hould only be ued for voltage polarity inverion, or in application which require both up- and down-converion of the input voltage ource. Linear regulator and witched-capacitor converter, which have the advantage that they require no magnetic component (inductor), are analyzed in [4]. However, their power efficiency i fundamentally limited by the converion ratio. They hould therefore be ued judiciouly in application where phyical ize and thereby the production cot are of far greater concern than power conumption, or where the converion ratio i within a range that allow acceptable power efficiency. The dicuion above implie that the mot appropriate olution for the tak of thi thei i the witched buck converter. Since, it offer high power efficiency over a wide range of regulated output voltage level. 1

3 Control Scheme for DC-DC Converter Next tep i to elect a uitable control cheme for the buck circuit conidering the high power efficiency requirement of thi project. Three control cheme approache will be analyzed and decribed in the following ection. 3.1 Pule-Width Modulation (PWM) The PWM control technique ha been briefly decribed in ection.1. It employ witching at contant frequency, i.e., T=ton+toff where T i contant time witching period and ton and toff repreent the time the witch i on and off, repectively. By adjuting the ton/toff ratio the average output voltage can be controlled. Thi operation can be repreented by the following equation t V D = T V on out = where D donate duty ratio of the witch. in A popular olution for generation of witch control ignal i to compare Vcontrol with a repetitive waveform a hown in figure 8a and 8b. 13

Figure 8: Pule-Width Modulation, a) ytem block chematic, b) control ignal (ource [5]). vcontrol i obtained by amplifying the difference between the actual output voltage from the converter and it deired value. The frequency of the repetitive waveform, repreented by the awtooth voltage in figure 8b, etablihe the witching frequency. Thi frequency i kept contant in a PWM control. When the amplified error ignal, which varie lowly with time relative to the witching frequency, i greater then the awtooth waveform, the witch control ignal become high, cauing the witch to turn on. Otherwie, the witch i off. In term of vcontrol and the maximum value of the awtooth waveform Vˆt in figure 8b, the witch ratio can be expreed a D t on control = = (1) T v Vˆ t Lower power efficiency for mall load i the main drawback of thi control cheme [4]. The main advantage i the ue of ingle witching frequency which make the level of output ripple highly controllable. 14

3. Pule-Frequency Modulation (PFM) One control cheme which obtain high power efficiency over a wide range of load i pule-frequency modulation (PFM). In thi cheme, the converter i operated only in hort burt at mall load a i conceptually illutrated in figure 9. Figure 9: Pule-Frequency Modulation, operation concept. Between burt, both power witche, Mp and Mn in figure 7 are turned off, and the circuit i idle with zero inductor current. During thi period, the filtering capacitor at the output ource the load current. When the output i dicharged to a certain threhold V-, the converter i activated for another burt, charging Cf. Thu, the load-independent loe in the circuit are reduced [4]. Further, for maller load current the idle time increae and thereby decreae power conuption. Output i regulated when the charge delivered through the inductor i equal to the charge conumed by the load. Thi implie that the inductor mut be deigned to be able to deliver the maximum charge conumed by the load during ytem operation. The major drawback of PFM control i that the witching period (the time between charge burt) i a function of the load. Thu, the converter appear almot chaotic and the witching noie i unpredictable. Thi i not well uited for wirele communication application. 15

3.3 Sliding Control The baic operation of the liding control i hown in figure 10 where the output voltage, V, i the regulated output. Figure 10: Sliding control, ytem block chematic. The comparator witche the input to the buck converter baed on the polarity of the compenator output, d(vref-v)/dt+(vref-v)/τ where Vref i the reference voltage. Unlike in PWM regulator, the witching frequency of the buck converter with liding control i not fixed by an external ource and i a function of Vref. The feedback i highly nonlinear due to the comparator. However, thi kind of ytem can be intuitively undertood by it phae portrait, a hown in figure 11. 16

Figure 11: Sliding control, ytem phae portrait. The buck converter contain two pole, o the feedback loop i a econd-order ytem. The phae portrait in figure 11 decribe the tranient operation of the circuit by the time trajectorie of the tate variable, (V, dv/dt), with the time variable being implicit. The comparator introduce a boundary line, d(vref-v)/dt+(vref-v)/τ=0 that divide the tate pace into two region. In the upper region, the input ignal to the buck converter i low and the tate follow the light trajectory curve. In the lower region, the input ignal to the buck converter i high and the tate follow the dark curve. When certain, o called liding condition on τ i met, the trajectorie from both region point toward the boundary line, and thu the tate i contrained on the line. Therefore, the ytem operate approximately a a firt-order ytem with the time contant τ. Thi ideal liding control law force the witching frequency to be infinitely high. Ue of comparator with hyterei like chmittrigger olve thi problem. The comparator in figure 10 drive the buck converter low when the compenator output i greater than +, and high when it i le than -. The larger the hyterei, the lower the witching frequency and the larger the voltage ripple. Sliding control offer high power efficiency over a wide range of load [9]. However, a in the cae of PFM, witching frequency i not contant making noie control difficult. 17

Few actual implementation of liding control in low voltage low power application have been done o far. Thi make it hard to fully evaluate potential of thi control technique. Detailed theoretical decription of liding control i given in [0]. 3.4 Control Scheme Selection In previou ection three control cheme have been preented. Their advantage and diadvantage compared to each other are ummarized below PWM Advantage: high power efficiency at large load, high noie and EMI control due to contant witching frequency. Diadvantage: lower power efficiency at mall load. PFM: Advantage: high power efficiency at mall load. Diadvantage: variable witching frequency (noie and EMI problem in ome application). Sliding Control Advantage: high power efficiency over a wide range of load Diadvantage: variable witching frequency (noie and EMI problem in ome application). Since the olution (ee ection 1.) of thi thei may a well be ued in wirele communication application PFM and liding control cheme can not be conidered a an alternative due to noie and EMI iue. For the intereted reader, an example of application that ue PFM i given in [14]. Circuit implementation of liding control i ummarized in [9]. Comparion of the previou work where PWM have been ued ee [6-8] how that PWM cheme i dominant in the field of low power, low voltage application. The fact that mot hand-held wirele communication application are alo the mot common low voltage low power application could be one reaon for the popularity of thi control technique. 18

If the power efficiency i conidered, ince it i one of the main prioritie in deign proce of thi olution, PWM provide olution with power efficiency over 90% including control circuitry. Good noie and EMI emiion control are other advantage which make PWM uitable for implementation in thi work. Furthermore, previou work done by other author and deigner on PWM control cheme provide a large knowledge bae which can be ued in deign proce. Therefore, a PWM control cheme i choen for implementation in thi project together with buck DC-DC converter topology. 19

4 Buck Converter, Mode of Operation When converter topology and control cheme have been elected it i time to get more familiar with two different mode of operation of buck converter. Continuou-conduction mode and dicontinuou-conduction mode are the topic of thi ection. The converter i analyed in teady tate, which mean that voltage and current wave form are repreented by their average value over one witching period. Loe in the inductive and the capacitive element are neglected in thi analyi. 4.1 Baic Theory Buck converter produce a lower average output voltage Vo than the input ource voltage Vd. Thi type of converter i mainly ued in regulated DC power upply. The circuit in figure 1a repreent a buck converter with a trictly reitive load. Auming an ideal witch, a contant input voltage Vd, and a purely reitive load, the output voltage Vo i illutrated in figure 1b. Figure 1: a) Simple buck circuit with reitive load b) The output voltage a a function of time (ource [5]). The average output voltage can be expreed in term of the witch duty ratio 1 1 t V o = + T 0 ince ton vcontrol D = = T Vˆ (3) t then Vd V o = vcontrol = kvcontrol V ˆ (4) t T ton T on vo ( t) dt = Vd dt dt = Vd = DVd T ton () 0 0 T 0

Vo can be controlled by varying the duty ratio Ton/T of the witch. Alo, the average output voltage Vo varie linearly with the control voltage, a i the cae in linear amplifier. Thi circuit ha two major limitation. 1. The circuit that i driven by the DC-DC converter would not jut exhibit a reitive component but, alo an inductive or capacitive part. With that in mind, the witch would have to aborb or to conume energy from the inductor and therefore it maybe detroyed.. The output voltage varie between zero and Vd which i not acceptable in mot application. Uing a diode or a rectifier (tranitor Mn in figure 7) a hown in figure 13a olve the problem of energy torage. The output voltage fluctuation are attenuated by uing low-pa filter coniting of an inductor and a capacitor. Figure 13b how the waveform of the ignal voi before the low-pa filter. Thi waveform conit of a DC component Vo and the harmonic of the witching frequency f a depicted in the ame figure. The magnitude repone of the low-pa filter i hown in figure 13c. The cut-off frequency fc of thi filter i much lower than the witching frequency f, thu ignificantly attenuating the amount of ripple in the output voltage caued by the witching frequency. Alo from figure 13a it can be oberved that in a buck converter, the average inductor current i equal to the average output current Io, ince the average capacitor current in teady tate i zero [5], [11]. 1

Figure 13: a) Buck converter b) The ignal voi before the low-pa filter both in time and frequency domain c) Magnitude repone of the low-pa filter (ource [5]).

4. Continuou-Conduction Mode (CCM) Thi mode of operation i defined by the condition that the inductor current i alway greater than zero. The average output voltage in thi mode of operation i expreed in (). A the conduction of current through the inductor occur during the entire witching period, the average output voltage i the product of the duty ratio and the DC input voltage. If all power loe aociated with all the circuit element are neglected, the input power Pd equal the output power Po. P d = P o Therefore V I = V d d o I o and I I d Vd = = (5) V D o 1 o According to (5) thi circuit reemble a DC tranformer baed on the timeintegral of the inductor voltage which equal zero over one witching period []. Thi alo implie that the area A and B in the figure 14 mut be equal. The operation of the circuit hown in figure 13a in teady tate conit of two tate a illutrated in figure 14. The firt tate, hown in figure 14a, when the witch i on, the diode i revere-biaed and current flow through the inductor from the voltage ource to the load. When the witch i turned off the inductor current freewheel through the diode a hown in figure 14b. A repreentative et of inductor voltage and current waveform for the continuou-conduction mode i hown in the ame figure. 3

Figure 14: Schematic of the buck circuit depending on the witch poition a) Switch on b) Switch off (ource [5]). 4.3 Boundary Between Continuou- and Dicontinuou- Conduction In CCM the inductor current (IL) i by definition alway greater than zero and in DCM (dicontinuou-conduction mode) it i lower than zero. Naturally, thi implie that boundary between CCM and DCM hould be pecified by condition when the inductor current i equal to zero. Thi condition occur at the end of the off period a hown in figure 15a. 4

Figure 15: a) Inductor current il at the boundary between CCM and DCM b) Average output current ILB a a function of duty ratio D (ource [5]). The average inductor current over the clock period, where the ubcript B refer to the boundary, i I 1 LB 1 T 1 il, peak = ildt = T T 0 T on i L peak = = = t DT, ( Vd Vo ) = ( Vd Vo ) I ob (6) L L Thi mean that during an operation condition (with a defined et of value for T, Vd, Vo, L and D), if the average output current (which i equal to the average inductor current) become le then ILB given by (6), then il will become negative. 4.4 Dicontinuou-Conduction Mode (DCM) There are two operation condition in which the converter may operate. Thee condition are defined by the characteritic of the input and the output ignal from the converter. Input and output ignal characteritic depend on the application of the converter. One condition aume contant Vd while Vo change in time and in the other the relationhip i revered. Application of thi work deal with the former and therefore thi condition i aumed in the following analyi. It ha been hown in () that Vo = VdD. Now, the average inductor current at the edge of the continuou-conduction mode from Eq. (6) i I LB DT TVd = ( Vd Vo ) = 1 L L D( D ) (7) 5

Figure 15b how ILB a a function of duty ratio D. All other parameter remain contant. Thi plot indicate that the output current required for a continuouconduction mode i maximum at D = 0.5 and therefore I LB TVd, max = (8) 8L Combining (7) and (8) a new expreion for ILB i given I LB = 4I LB max D( 1 D), (9) Next the voltage ratio Vo/Vd for dicontinuou-conduction mode will be calculated. Firt, it i aumed that the converter operate at the boundary of continuou conduction a in figure 15 with pecific value for T, L, Vd and D. If thee factor are kept contant and the power to the load i decreaed (e.g. the load reitance increae), then the average inductor current will decreae. Thi reult in larger value of Vo than before and dicontinuou inductor current. The inductor current a a function of time i illutrated in figure 16. Figure 16: Inductor current il in the DCM (ource [5]). The inductor current and voltage VL are zero during the T interval and the power to the load reitor i upplied by the filter capacitor alone. Equating the integral of the inductor voltage over one clock period to zero yield ( V V ) DT + ( V ) 1 T = 0 D o o (10) 6

V V o d = D D + 1 (11) where D + < 1.0. 1 From figure 16, Vo il, peak = 1T (1) L Therefore 1 I o DT 1 ( t) dt + T DT = i 0 L 1 DT T i L ( t) dt = uing (1) and geometry formula for the area of the triangle formed by il and time axe t in figure 16 D + 1 = il, peak (13) T = V o ( D + 1) 1 L (uing equation 1) (14) T = V d D 1 L (uing equation 11) (15) = 4I LB,max D 1 (uing equation 8) (16) I o 1 = 4I D (17) LB,max From equation 11 and 17 V V o d = D D 1 + 4 I I o LB,max (18) Thi analyi how that in DCM, duty ratio D i not longer a imple function of output and input voltage. It alo depend on the output current Io. 4.5 Output Voltage Ripple The voltage at the output of the buck converter contain ome tolerable amount of ripple generated by the PWM ignal [13]. Thi output voltage ripple i a meaure of the deviation in the output voltage from the average value. The peak- 7

to-peak voltage ripple for the buck converter in the continuou-conduction mode can be computed for a pecified value of output capacitance by computing the additional charge Q provided by the ripple current in the inductor, ee figure 17. Thi analyi aume that the entire ripple current flow through the capacitor, while the average value of the inductor current (IL) flow through the load reitor [1] [5]. The peak-to-peak voltage ripple i calculated by taking the area under the inductor current il (the additional charge Q) and dividing by the capacitance reulting in (19) [1]. V Q C 1 C 1 I T T V = 8C L L o o = = 1 ( D) T (19) V V o o = 1 8 T ( 1 D) LC π = ( 1 D) f f c (0) where witching frequency f=1/t and f c 1 = (1) π LC Figure 17: Additional charge Q created by the ripple current (ource [5]). Equation (0) and (1) how that amount of ripple in the output ignal can be controlled by electing an appropriate fc. Typically, fc i choen at leat ten time lower then f. To integrate paive filter component (L and C) which define fc on-chip i a challenging tak due to their ize. Even if f i in range of few MHz filter component are uually implemented off-chip. 8

Thi analyi how alo that amount of ripple i independent of the output load power a long a the converter operate in CCM. In mot application the ripple i kept below 1% [5]. 4.6 Deign Iue The purpoe of the theoretical analye preented in perviou ection wa to how how circuit performance depend on the mode of operation. Buck converter can be deigned to operate in one or both mode of operation depending on the pecific application of the converter. If the deign parameter preented in ection 1.4 are conidered the converter for low voltage and low power application hould be deigned to operate in both CCM and DCM (ee ection 7.). 9

5 Source of Power Diipation Buck converter contain many ource of power diipation like the erie reitance RCin, paraitic capacitance Cx, tray inductance L and the drain body diode of power tranitor. All of thee are hown in figure 18. Figure 18: Buck converter with major ource of diipation. Thi ection will preent major ource of power diipation that decreae the power efficiency of thi circuit. 5.1 Conduction Lo When current flow through nonideal component like tranitor, reitor, capacitor and interconnection network loe are inevitable. Reitive loe are computed a P q = i rm R () where i rm i root-mean quared current and R i the reitance of the component. The rm current can be divided into two component i = i + i rm rm( DC) rm( AC) (3) For PWM control cheme the rm current are given by i = D I rm( DC) o (4) and 30

i 1 I rm ( AC) = D (5) 3 Here, 0 D 1 i the duty cycle of the current flow through the component, Io i the DC load current, and I i the peak-to-peak inductor current ripple. The DC part of conduction lo varie quadratically with the load current, while the AC component i approximately contant (if the ripple i mall) and may degrade the power efficiency for mall load. 5. Gate Drive Lo The average power diipated by increaing and decreaing the tranitor gate potential in each cycle i given by P g = E g f (6) where Eg i energy tranferred to the gate per off-on-off tranition cycle (which can include ome energy due to Miller effect), and include diipation in the drive circuitry. The gate-drive lo i independent of the load current and will therefore degrade the power efficiency for mall load current. 5.3 Timing Error There are three type of loe aociated with timing error in the witching of the MOSFET. Each i independent of the load voltage. 5.3.1 No dead-time: Short-Circuit Lo During FET tranition a hort-circuit path may temporarily exit between the input rail. To avoid thee potentially high loe in the buck converter (non overlapping clock) it i neceary to provide dead-time in the conduction of the MOSFET to enure that the two device never conduct at the ame time. 5.3. Dead-Time too Long: Body Diode Conduction If the length of the dead-time are too long, the body diode of the NMOS tranitor may be forced to tranfer the inductor current for a mall period of time in each cycle. Since in low-voltage application, the forward bia diode voltage ( V diode 0. 7V ) can be comparable to the output voltage, it conduction lo may be ignificant. Thi lo i given by 31

P diode I V t f (7) o diode err where terr i the timing error between complementary power MOSFET conduction interval. Alo, when the PMOS device i turned on, the exce minority carrier charge mut be removed from the body diode, diipating an energy bounded by E rr = Q rr V in (8) where Qrr i the tored charge in the body diode. 5.3.3 Dead-Time too Short: Capacitive Switching Lo In a traditional witched converter, the MOSFET Mp charge the paraitic capacitance Cx (ee figure 18) to Vin in each cycle, diipating an average power P Cx( LH ) 1 = C XVin f (9) where Cx include tranitor paraitic like revere-biaed drain-body junction diffuion capacitance Cdb and ome or all of the gate-drain overlap (Miller) capacitance Cgd, wiring capacitance from their interconnection, and tray capacitance aociated with Lf. When Mp i turned off, the inductor begin to dicharge Cx from Vin to ground. If Mn i turned on exactly when Vx reache ground, thi tranition i lole. If the NMOS device i turned on too late, Vx will be dicharged below ground, until the body diode i forced to conduct (ee above). If the NMOS device i turned on too early, it will dicharge Vx to ground through it channel, introducing loe P Cx( HL) = 1 C X V X f 1 C X V in f (30) 5.4 Stray Inductive Switching Lo Energy tored in the tray inductance L, (ee figure 18) in the loop formed by the input decoupling capacitor Cin and the tranitor caue power diipation according to P L = E f (31) L 3

where E 1 L ( I I ) L = S min + max and I I min max I = I o (3) I = I o + (33) The value of L dependent on PCB layout, packaging, bonding, and chip layout, and i reduced by minimizing the area of thi critical high current loop. In a multilayer interconnection technology, the lowet tray inductance i obtained by uing a conductor that overlap a return path in a different layer, with thin dielectric eparating the layer. In a careful deign: 1 nh < L < 10 nh 5.5 Control Circuitry Operating Power The PWM and other control circuitry conume tatic power. In low-power application, thi control power contribute to the total loe, even at full-load. Thee loe can be generated by component like op-amp and other analog circuit. 33

6 Switching Technique Previou ection covered ome baic theoretical relationhip and lo analyi aociated with operation of imple buck converter. Several deign technique for buck converter in order to increae their power efficiency have been propoed in the literature. Thee will be decribed in the next ection. Since power efficiency alo depend on the witching technique in ue, thi ection will decribe the two mot common today, hard witching and oft witching. 6.1 Hard Switching Term, hard witching refer to the treful witching behavior of the power MOSFET device of figure 18. In practice, thi mean that the MOSFET device during witching ha to withtand high voltage and current imultaneouly. Thi reult in high witching loe and tre. Two dahed curve with the pike in the figure 19 repreent voltage-current relationhip trough the witch under hard witching condition. The area under each curve repreent witching loe aociated with on-to-off and off-to-on witch tranition. In order to decreae the tre in the device, paive nubber circuit coniting of erie connected reitor and capacitor, are added to the converter deign. Snubber are connected in parallel with the MOSFET to protect them from high current and voltage. Thi mean that all witching loe are diverted to nubber a well. The voltage-current relationhip for the witch implementing nubber i alo plotted in figure 19. Since, the witching lo i proportional to the witching frequency, it i the major limiting factor for the maximum witching frequency of the power converter. In pite thee limitation aociated with the hard witching technique it i till in ue, ee ection 7.. 34

I Safe Operating Area On Hard-witching nubbered Soft-witching Off V Figure 19: Voltage-current relationhip through the witch under different witching condition. 6. Soft Switching Soft witched converter have witching waveform imilar to thoe of hard witched converter except that the riing and falling edge of the waveform are moothed with le tranient pike, ee the dahed curve cloe to the origin in figure 19. Notice how the voltage-current relationhip under oft witching condition follow ame curve trajectory. Becaue the witching lo and tre have been reduced, oft witched converter can be operated at the high frequency (typically 500 khz to a few MHz). Thi i important property which reult in reduced converter ize and hence increaed power denity. Soft witching converter alo provide an effective olution to uppre EMI and have been applied to DC-DC, AC-DC and DC-AC converter. More detailed decription of oft witching technique i given in ection 7. [13]. 35

7 Technique for High Power Efficiency Section 5 decribed and analyzed ome major mechanim of lo in a CMOS buck converter. In thi ection, deign technique to reduce the power diipation generated by thee ource are preented. 7.1 Synchronou Rectification One of the mot ignificant deign technique for lo minimization in low voltage, low power converter i ynchronou rectification. Becaue of it importance it ha been mentioned in ection 3.4. Synchronou rectification implie the ue of an active witch intead of a diode in the converter power tage, ee figure 0. By replacing the diode in figure 0 with an NMOS device which i on when the diode would have conducted (Mn in figure 7), the forward drop can be made arbitrarily mall by making the device ufficiently large. Hence, the NMOS device, ued a a ynchronou rectifier, can perform the ame function a the diode, but more efficiently. Neglecting all other loe, including the gate-drive for the ynchronou rectifier, the maximum power efficiency of the low voltage buck converter approache 100%. Conider the conventional buck circuit of figure 0. Figure 0: Conventional buck circuit. The maximum power efficiency of the converter i limited by the forward bia diode voltage, Vdiode. Since the diode conduct for a fraction (1-D) of the witching period, the maximum power efficiency i given by V o η max = (34) Vo + (1 D) Vdiode If the deign parameter given in ection 1.4 are conidered and a conventional buck converter a hown in figure 0 i ued to generate an output voltage of 1 V, even uing a low-voltage Shottky diode with a forward drop of 0.3 V, at the 36

battery cell voltage of Vin= V, ηmax i lower than 87%. With a ilicon bipolar Vdiode=0.7 V loe increae dramatically and ηmax drop below 74%. 7.1.1 Synchronou Rectifier Control The ue of a ynchronou rectifier may reduce conduction lo at low output voltage level, but it alo require an additional gate driver which conume power a well. Furthermore, a mentioned in ection 5, without adequate control of the rectifier, a hort-circuit path may exit between the input rail during tranient. However, a will be dicued in ection 7.3 an example of rectifier control circuit to minimize the time Mp and Mn conduct imultaneouly i preented. Thi i performed in a feedback loop which obtain nearly ideal zerovoltage witched turn-on tranition of both power MOSFET [4]. 7. Zero Voltage Switching When the buck circuit of figure 1 i hard witched, it diipate power in proportional to Cx Vin² f a a reult of the gradual charging of the paraitic capacitance Cx through a reitive path, Mp. Alo, it i likely to introduce either ubtantial hort-circuit lo (if no dead-time i provided), or revere recovery lo (if a dead-time i provided). In a oft witched circuit, the filter inductor i ued a a current ource to charge and dicharge capacitor Cx in an ideally lole manner, allowing additional capacitance to be hunted acro Cx, lowing the tranition of the inverter output node Vx. In thi way, appropriate dead-time may be ued to allow tranitor witching with Vd=0. Thi ignificantly decreae the aociated witching loe. Figure 1: Buck converter with paraitic capacitance Cx. 37

Figure ZVS wave form. Figure 1 and figure how the buck converter and related periodic teadytate waveform for ideal zero-voltage witching operation. The oft witching proce i imilar to that decribed in [3],[5], [15]. Preume that at a given time (the origin in figure ), the rectifier Mn i on, connecting the node Vx to ground. During thi time, the output voltage i contant and greater than zero, a teady negative potential i applied acro Lf, and ilf i linearly decreaing. If the rectifier i turned off when the ilf become negative (and the PMOS device, Mp, remain off), Lf act roughly a a current ource, charging Vx. To accomplih a lole low-to-high tranition at the Vx, the PMOS device i turned on when Vx=Vin. In thi cheme, a pa device (Mp) gate tranition occur exactly when Vdp (drain-ource voltage) = 0. With the PMOS device on, the Vx node i connected to Vin. Thu, a contant poitive voltage i applied over Lf, and ilf increae linearly, until the high-tolow tranition at Vx i initiated by turning off Mp. A hown in figure, at thi time, the current ilf i poitive (converter operate in continuou-conduction mode). Again, Lf act a a current ource, thi time dicharging Cx. If the NMOS device i turned on with Vx = 0, loe aociated with the high-to-low tranition of the Vx node are decreaed, and Mn i witched at Vdn = 0. 38

In thi oft-witching approach, the filter inductor i ued to charge and dicharge all capacitor at the inverter output node in a lole manner. Becaue the tranitor are witched at zero drain-ource voltage, thi technique i known a zero-voltage witching (ZVS), and greatly decreae the capacitive witching lo. The ue of oft witching in low-voltage application i to ome degree controverial. Author of [16] propoe ue of hard witching intead of oft witching in their low voltage DC-DC converter olution. It i motivated by experimental reult, which how that the conduction lo i higher than the witching lo. Thi implie that oft witching olution imilar to that decribed earlier uffer from higher conduction loe caued by reonant current ince it i negative during a hort period of time. Their hard witched approach implement a zero current ening block which clamp il at zero, reducing the power diipation. Switche till follow the ZVS technique. Although there are theoretical and experimental reult which indicate that thi olution hould be highly power efficient, final circuit meaurement preented in [16] including control cheme do not obtain a power efficiency greater than 78%. 7.3 Adaptive Dead-Time Control To guarantee ideal ZVS of the power tranitor, the period when neither conduct (the dead-time), τ D, mut exactly equal the Vx node tranition time τ DLH = τ xlh τ = DHL τ xhl In practice, it i hard to maintain thee relationhip. A indicated by figure, the inductor current ripple i ymmetric about the average load current. A the average load reitance varie, the DC component of the ilf waveform i hifted, and the current available for commutating the Vx node i adapted. Thu, Vx node tranition time are load dependent. In ome implementation of oft-witching, a value of the average load may be aumed, reulting in approximation of the Vx node tranition time. Fixed dead-time are baed on thee approximation. Thi reult in reduced loe, but perhap not to negligible level. To demontrate the potential problem of fixed dead-time operation, figure 3a how the effect of non-proper ZVS on converion efficiency during a high-tolow tranition at the Vx node. In figure 4b, the dead-time i too hort, making 39

the NMOS device to turn on with Vdn>0, partially dicharging Cx through a reitive path which introduce loe. In figure 4b, the dead-time i too long, and the Vx node fall below zero until the drain-body junction of Mn become forward biaed. In low-voltage application, the forward-bia body diode voltage i a large fraction of the output voltage; thu, body diode conduction mut be avoided for power efficient operation according to (34). When the rectifier (Mn) turn on, it remove the extra minority carrier charge from the body diode and charge the inverter output node back to ground, diipating additional energy. Figure 3: Problem of fixed dead-time operation. Figure 4 how a block diagram of the approach which according to [4] provide effective ZVS over a wide range of load. Figure 4: Block diagram of a poible approach for implementation of ZVS. A phae detector update an error ignal baed on the relative timing of Vx and the gate-drive ignal of the tranitor. A delay generator adapt the dead-time 40