Materials and Device Solutions Beyond Moore Prof. Dr.- Ing. T. Mikolajick Scientific Director NaMLab GmbH Chair of Nanoelectronic Materials, IHM, TU Dresden Thomas.Mikolajick@namlab.com Thomas.Mikolajick@tu-dresden.de 1
Outline Introduction Nanowire Electronics Memristor Summary and Outlook 2
Outline Introduction Nanowire Electronics Memristor Summary and Outlook 3
Moore s Law The success of semiconductor technology is based on the scaling of minimum feature sizes 4
Will there be a sixth paradigm? Exponential growth in electronic systems did start before IC technology!? No Exponential is forever G. Moore, Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International Source: R. Kurzweil 5
Will there be a sixth paradigm? Silicon based computing is still significantly less powerfull than the brain It is likely that (exponential) growth will expand beyond IC technology but forever can be delayed G. Moore, Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International Source: R. Kurzweil 6
General Statements Moore s Law is about reducing the feature size more components per die higher speed Going beyond means to break one or more major paradigms like separation between wiring and switching separation between memory and computing high performance = high speed of single element Need to achieve today s complexities almost from the beginning Is there room for a radical new solution? 7
Outline Introduction Nanowire Electronics Memristor Summary and Outlook 8
Silicon Nanowires: Ultimate CMOS The gate all around structure is considered as the ultimate CMOS device Possible Scaling path for MOSFETs 25 stage ringoscillator using 3nm long Si-NW transistors S. Bangsaruntip et al., Proceedings of VLSI Technology, 2010 (IBM) 9
Alternative Device Concepts The Junctionless gated resistor omits the S/D junctions The Nanowire Tunnel FET enables subthreshold slope < 60mV/Dek The Schottky Barrier FET (see later slides) omits channel doping Junctionless gated resistor Nanowire tunnel FET S = V g ψ s ψ s ( I ) log 10 ds Body factor m <1 n < kt/q ln10 n-type: n-channel w. p- poly Si gate p-type: p- channel w. n- poly Si gate J.P. Colinge et al. Nature Nanotech 5, 225 (2010) M. Björk, J. Knoch, et al. APL 92, 193504 (1998) J. Knoch et al. EDL 29, p. 372 (2008) A. Verhurst JAP 104; 064514 (2008) 10
Bottom up and top down Top down: straight forward scaling from today's technology Bottom up: simple and controlled fabrication of nm structures Si-NW top down etching Si-NW Bottom up growth SiH 4 (g) Si-nanowire (s) Au/Si (l) Si or SiO 2 Substrate S. C. Rustagi et al., IEEE EDL, Vol. 28, No. 11, 2007 11
Motivation for SBFET Complementary MOS logic provides low standby power circuits Classical CMOS scaling demands increasingly sharp doping profiles Doping fluctuations in channel become critical in nm sized volumes [T. Mikolajick, V. Häublein und H. Ryssel, Applied Physics A 64, 1997, S. 555-560] Accurate doping control in nanowires is challenging Doping efficiency (ionization of impurities) is related to nanowire diameter and gate shielding [M. Diarra, Y.-M. Niquet et al. Pys. Rev. B 75, p. 045301 (2007)] Schottky barrier FET as Alternative to classical field effect transistor device Use of abrupt metal semiconductor interfaces External control over carrier injection through Schottky junctions Avoid doping of semiconductors (S/D and channel) 12
Si-NW Growth on amorphous SiO 2 Deposition parameters: d Au = 0.5 nm p SiH4 = 5 Torr T = 450 C Si-NWs after deposition Si-NWs grown on SiO 2 surface Ø = 20-30nm <112> W.M. Weber, et al. Phys.Stat.Sol.b 243, 3340-3345 (2006) 13
Contact NWs with selective electro-less Ni plating Nickel embeds NWs Good adhesion of stack Prevents NW contamination with resist Annealing at 480 C Cross section SiO 2 Si Si-NW Ti Deposition of Ni reservoir Ni Co Si-NW SiO 2 Si-NW embedded in Ni reservoir Ni 14
Shortening the gate-length Silicidation process allows reduction of the channel 7nm long device length far beyond the lithographically defined dimensions Reduction of channel length before anneal SEM of Si-NW back gate transistor after anneal NiSi 2 Ni 200 nm source L G drain NiSi 2 NiSi 2 Si SiO 2 Ni 15
Top gated SBFETs Enhanced gate control is provided by high-k / metal top gate stack Appropriate interface treatment required Accurate placement of top gates on Schottky contacts using e-beam litho Schematic cross section of top gate NMtransistor G single top gate transistor L g ~ 98 nm d NW = 10 nm twin top gate transistor S TG-2 Si high-k TG-1 SiO 2 D High-k materials used 16
Si-NW SBFETs with tunable polarity Leverage 1-D properties of NWs Same transistor provides p- and n- type transport Double gate NW-SBFET p-type transfer characteristic 100p - + + + - - 1 2 3 V TG-L V TG-R I d [A] 10p 1p 100f 1 2 V TG-R = -2V V ds = -1V 10f -2-1 0 1 2 V TG-L [V] n-type transfer characteristic 100p 1 10p - + + - + - 2 V TG-L V TG-R Weber W. M. et al. IEEE Proc. Nanotech Conf. 2008, p 580 (2008) 3 I d [A] 1p 100f 3 1 2 V TG-L V TG-R = +2V V ds = +1V 10f -2-1 0 1 2 V TG-L [V] 3 V TG-R 17
Reconfigurable Gates Inverter can be formed by connecting two DG-SB FETs No doping required Sketch of doping free Si-NW Inverter GND V dd -V dd V out V in 18
Inverter without dopants Doping free logic devices Same device for switching and load SEM of Si-NW Inverter V out Transfer function of Si-NW Inverter 0.0-0.5-1.0-1.5-1.5-1.0-0.5 0.0 V in Switching of Si-NW Inverter V in V o u t 0 5 0 0 1 0 0 0 1 5 0 0 T im e [s ] 0.0-0.5-1.0-1.5-2.0 Potential [V] 19
Outline Introduction Nanowire Electronics Memristor Summary and Outlook 20
Memory resistor definition First proposed by Leon O. Chua in 1971 as the fourth basic circuit element. Main Characteristic 2 terminal device similar behavior as ohmic resistor resistance not constant Example charge controlled memristor with memristance M v(t) = M(q(t)) dϕ (q) M(q) dq i(t) The value of memristance at t 0 depends on idt, thus it behaves like a resistor with memory. t 0 21
The missing memristor found May 2008: Strukov et.al. (HP Labs) describe the electrical behavior of the thin film system Pt/TiO/Pt by a Memristor model with µ V average Ion mobility pinched hysteresis in I-V-characteristic Beside ion-migration many other physical effects with memristive behavior are known: thermochemical- and phase-transitions, shottky barrier lowering by electron trapping or spin transfer, metal-insulator transition (MIT).. 22
Memristor effects Resistive Switching Thermal Effects Electronic Effects Magnetic Effects Ionic Effects Phase change Charge trapping on trapping centers Anisotropic Magnetic Resisstance (AMR) and Giganto Magnetic resisstance. (GMR) Obsolete for memories/memristors Kation Migration (Electrometallization) Magnetic Tunneling resistivity with magnetic switches Fuse-Antifuse effects Insulator conductor transistion caused by charge Anion Migration - redox effects Ferroelectric tunneling barriere Magnetic tunnelin resisitivity with spin momentum transfer T. Mikolajick et al., Advanced Engineering Materials, 2009 Modified from R. Waser and M. Aono, Nature Materials, 2007 23
Memristor application Combination of logic and memory functionality within one device on nm-scale gives the opportunity for new system architectures: nonvolatile memories defect tolerant circuits with self-repair and self-organization reconfigurable electronics by software instructions system (re)configuration affords non-regular computer architectures weaken and strengthen of connections models synaptic plasticity 24
Memristor @ NaMLab Resistive RAM/ Memristor based on TiOx Al (400nm) TiO 2 (30nm) 7sccm Pt (20nm) Current (A) 1E-3 1E-5 1E-7 1E-9 1E-11 1E-13 1E-15 2 3 SET 1 4 RESET -3-2 -1 0 1 2 Voltage (V) Current (A) 1E-7 1E-9 1E-11 1E-13 1E-15 1 2 3 4 5 1E-17-0.50-0.25 0.00 0.25 0.50 Voltage (V) Produced RRAM devices based on TiO 2 Integrated switchable diode Multilevel states 25
Memristor @ NaMLab Small teststructures required for detailed switching studies sub-µ electrode structures developed using e-beam lithography will be used for integration of different material systems 26
Outline Introduction Nanowire Electronics Memristor Summary and Outlook 27
Summary and Outlook Mores law is expected to reach its physical limits in the next decade The continuing need for more computing power calls for electronics with higher performance/complexity than what will be possible by Moore's law There is large number of competing concepts, which break the paradigms of classical CMOS technologies in a more or less radical way NaMLab is working on reconfigurable Nanowire devices as well as Memristors as possible devices for a post Moore electronics 28
Visit Science Park, Hall 4, Boot 4.616 Datum 19.10.2010 " Material Research for Future Electronics" Nano Wire Devices - Nano wire transistors - Nano wire sensors 19.10.2010 Energy Harvesting - Dielectrics for photovoltaic - Advanced battery materials 20.10.2010 Memory Concepts - Non volatile memories - Memristors 21.10.2010 Micro Devices - Transistors - Photodiodes - High-k devices 29
Symposium of the Nanoelectronic Centre of the Faculty of Electrical and Computer Engineering at the University of Technology Dresden (NanoZEIT) Room "Columbus, Hall 4 Wednesday, October 20 th, 2010 10:00 Uhr - 16:30 Uhr 30
Thank you for your attention! 31