Applications l High frequency DC-DC converters SMPS MOSFET PD - 9399A IRFR9N20D IRFU9N20D HEXFET Power MOSFET V DSS R DS(on) max I D 200V 0.38Ω 9.4A Benefits Low Gate-to-Drain Charge to Reduce Switching Losses Fully Characterized Capacitance Including Effective C OSS to Simplify Design, (See App. Note AN0) Fully Characterized Avalanche Voltage and Current l l l D-Pak IRFR9N20D I-Pak IRFU9N20D Absolute Maximum Ratings Parameter Max. Units I D @ T C = 25 C Continuous Drain Current, V GS @ V 9.4 I D @ T C = 0 C Continuous Drain Current, V GS @ V 6.7 A I DM Pulsed Drain Current 38 P D @T C = 25 C Power Dissipation 86 W Linear Derating Factor 0.57 W/ C V GS Gate-to-Source Voltage ± 30 V dv/dt Peak Diode Recovery dv/dt ƒ 5.0 V/ns T J Operating Junction and -55 to 75 T STG Storage Temperature Range Soldering Temperature, for seconds 300 (.6mm from case ) C Typical SMPS Topologies l Telecom 48V input Forward Converter Notes through are on page www.irf.com 6/29/00
Static @ T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions V (BR)DSS Drain-to-Source Breakdown Voltage 200 V V GS = 0V, I D = 250µA V (BR)DSS/ T J Breakdown Voltage Temp. Coefficient 0.23 V/ C Reference to 25 C, I D = ma R DS(on) Static Drain-to-Source On-Resistance 0.38 Ω V GS = V, I D = 5.6A V GS(th) Gate Threshold Voltage 3.0 5.5 V V DS = V GS, I D = 250µA I DSS Drain-to-Source Leakage Current 25 V µa DS = 200V, V GS = 0V 250 V DS = 60V, V GS = 0V, T J = 50 C I GSS Gate-to-Source Forward Leakage 0 V GS = 30V na Gate-to-Source Reverse Leakage -0 V GS = -30V Dynamic @ T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions g fs Forward Transconductance 4.3 S V DS = 50V, I D = 5.6A Q g Total Gate Charge 8 27 I D = 5.6A Q gs Gate-to-Source Charge 4.7 7. nc V DS = 60V Q gd Gate-to-Drain ("Miller") Charge 9.0 4 V GS = V, t d(on) Turn-On Delay Time 7.5 V DD = 0V t r Rise Time 6 ns I D = 5.6A t d(off) Turn-Off Delay Time 3 R G = Ω t f Fall Time 9.3 V GS = V C iss Input Capacitance 560 V GS = 0V C oss Output Capacitance 97 V DS = 25V C rss Reverse Transfer Capacitance 29 pf ƒ =.0MHz C oss Output Capacitance 670 V GS = 0V, V DS =.0V, ƒ =.0MHz C oss Output Capacitance 40 V GS = 0V, V DS = 60V, ƒ =.0MHz C oss eff. Effective Output Capacitance 74 V GS = 0V, V DS = 0V to 60V Avalanche Characteristics Parameter Typ. Max. Units E AS Single Pulse Avalanche Energy 0 mj I AR Avalanche Current 5.6 A E AR Repetitive Avalanche Energy 8.6 mj Thermal Resistance Parameter Typ. Max. Units R θjc Junction-to-Case.75 R θja Junction-to-Ambient (PCB mount)* 50 C/W R θja Junction-to-Ambient Diode Characteristics Parameter Min. Typ. Max. Units Conditions D I S Continuous Source Current MOSFET symbol 9.4 (Body Diode) showing the A G I SM Pulsed Source Current integral reverse 38 (Body Diode) p-n junction diode. S V SD Diode Forward Voltage.3 V T J = 25 C, I S = 5.6A, V GS = 0V t rr Reverse Recovery Time 30 ns T J = 25 C, I F = 5.6A Q rr Reverse RecoveryCharge 560 nc di/dt = 0A/µs t on Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by L S L D ) 2 www.irf.com
I D, Drain-to-Source Current (A) 0 VGS TOP 5V 2V V 8.0V 7.0V 6.5V 6.0V BOTTOM 5.5V 5.5V 20µs PULSE WIDTH T J = 25 C 0. 0. 0 V DS, Drain-to-Source Voltage (V) I D, Drain-to-Source Current (A) 0 VGS TOP 5V 2V V 8.0V 7.0V 6.5V 6.0V BOTTOM 5.5V 5.5V 20µs PULSE WIDTH T J = 75 C 0. 0. 0 V DS, Drain-to-Source Voltage (V) Fig. Typical Output Characteristics Fig 2. Typical Output Characteristics I D, Drain-to-Source Current (A) 0 T J = 75 C T J = 25 C V DS= 50V 20µs PULSE WIDTH 0. 4 6 8 2 V GS, Gate-to-Source Voltage (V) R DS(on), Drain-to-Source On Resistance (Normalized) 3.0 I D = 9.4A 2.5 2.0.5.0 0.5 V GS = V 0.0-60 -40-20 0 20 40 60 80 0 20 40 60 80 T J, Junction Temperature ( C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance Vs. Temperature www.irf.com 3
C, Capacitance(pF) IRFR9N20D/IRFU9N20D 000 00 0 V GS = 0V, f = MHZ C iss = C gs C gd, C ds SHORTED C rss = C gd C oss = C ds C gd Ciss Coss Crss 0 00 V DS, Drain-to-Source Voltage (V) V GS, Gate-to-Source Voltage (V) 20 6 2 8 4 I = D 5.6A V DS = 60V V DS = 0V V DS = 40V FOR TEST CIRCUIT SEE FIGURE 3 0 0 5 5 20 25 30 Q G, Total Gate Charge (nc) Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage 0 00 OPERATION IN THIS AREA LIMITED BY R DS(on) I SD, Reverse Drain Current (A) T J = 75 C T J = 25 C V GS = 0 V 0. 0.2 0.4 0.6 0.8.0.2.4 V SD,Source-to-Drain Voltage (V) I D, Drain Current (A) 0 us 0us ms ms TC = 25 C TJ = 75 C Single Pulse 0. 0 00 V DS, Drain-to-Source Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area 4 www.irf.com
.0 V DS R D I D, Drain Current (A) 8.0 6.0 4.0 2.0 Fig a. Switching Time Test Circuit V DS 90% R G V GS V GS Pulse Width µs Duty Factor 0. % D.U.T. - V DD 0.0 25 50 75 0 25 50 75 T C, Case Temperature ( C) Fig 9. Maximum Drain Current Vs. Case Temperature % V GS t d(on) t r t d(off) t f Fig b. Switching Time Waveforms Thermal Response (Z thjc ) 0. D = 0.50 0.20 0. 0.05 0.02 0.0 SINGLE PULSE (THERMAL RESPONSE) Notes:. Duty factor D = t / t 2 2. Peak T J = P DM x Z thjc TC 0.0 0.0000 0.000 0.00 0.0 0. t, Rectangular Pulse Duration (sec) PDM t t2 Fig. Maximum Effective Transient Thermal Impedance, Junction-to-Case www.irf.com 5
R G V DS 20V tp Fig 2a. Unclamped Inductive Test Circuit tp L D.U.T I AS 0.0Ω V (BR)DSS 5V DRIVER - V DD A E AS, Single Pulse Avalanche Energy (mj) 200 60 20 80 40 TOP BOTTOM I D 2.3A 4.0A 5.6A 0 25 50 75 0 25 50 75 Starting T, Junction Temperature ( J C) Fig 2c. Maximum Avalanche Energy Vs. Drain Current I AS Fig 2b. Unclamped Inductive Waveforms Current Regulator Same Type as D.U.T. Q G 50KΩ Q GS Q GD 2V.2µF.3µF D.U.T. V - DS V G V GS 3mA Charge I G I D Current Sampling Resistors Fig 3a. Basic Gate Charge Waveform Fig 3b. Gate Charge Test Circuit 6 www.irf.com
Peak Diode Recovery dv/dt Test Circuit D.U.T ƒ - Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer - - R G dv/dt controlled by R G Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test - V DD Driver Gate Drive Period P.W. D = P.W. Period V GS =V * D.U.T. I SD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt V DD Re-Applied Voltage Inductor Curent Body Diode Forward Drop Ripple 5% I SD * V GS = 5V for Logic Level Devices Fig 4. For N-Channel HEXFET Power MOSFETs www.irf.com 7
D-Pak (TO-252AA) Package Outline Dimensions are shown in millimeters (inches) 5.46 (.25) 5.2 (.205) 6.73 (.265) 6.35 (.250) - A -.27 (.050) 0.88 (.035) 2.38 (.094) 2.9 (.086).4 (.045) 0.89 (.035) 0.58 (.023) 0.46 (.08) 4.02 (.040).64 (.025) 2 3 6.22 (.245) 5.97 (.235).42 (.4) 9.40 (.370) 6.45 (.245) 5.68 (.224) LEAD ASSIGNMENTS - G A TE.52 (.060).5 (.045) 2X.4 (.045) 0.76 (.030) 3X - B - 0.89 (.035) 0.64 (.025) 0.25 (.0) M A M B 0.5 (.020) M IN. 0.58 (.023) 0.46 (.08) 2 - D R A IN 3 - S O U R CE 4 - D R A IN 2.28 (.090) 4.57 (.80) NOTES: DIMENSIONING & TOLERANCING PER ANSI Y4.5M, 982. 2 CONTROLLING DIMENSION : INCH. 3 C O N FO R M S TO JE D E C O U TLIN E TO -252 AA. 4 DIMENSIONS SHOW N ARE BEFORE SOLDER DIP, SOLDER DIP MAX. 0.6 (.006). D-Pak (TO-252AA) Part Marking Information 8 www.irf.com
I-Pak (TO-25AA) Package Outline Dimensions are shown in millimeters (inches) 5.46 (.25) 5.2 (.205) 6.73 (.265) 6.35 (.250) - A - 4.27 (.050) 0.88 (.035) 2.38 (.094) 2.9 (.086) 0.58 (.023) 0.46 (.08) LEAD ASSIGNMENTS - G ATE.52 (.060).5 (.045) 6.22 (.245) 5.97 (.235) 6.45 (.245) 5.68 (.224) 2 - D RA IN 3 - SOURCE 4 - D RA IN 2 3 - B - 2.28 (.090).9 (.075) 9.65 (.380) 8.89 (.350) NOTES: DIMENSIONING & TOLERANCING PER ANSI Y4.5M, 982. 2 CONTROLLING DIMENSION : INCH. 3 C O NF O R MS TO JEDE C O UTLINE TO -25 2AA. 4 D IM EN SIO N S S HO W N A R E BE FO RE SO L DE R D IP, SOLDER DIP MAX. 0.6 (.006). 3X.4 (.045) 0.76 (.030) 2.28 (.090) 2X 3X 0.89 (.035) 0.64 (.025) 0.25 (.0 ) M A M B.4 (.045) 0.89 (.035) 0.58 (.023) 0.46 (.08) I-Pak (TO-25AA) Part Marking Information www.irf.com 9
D-Pak (TO-252AA) Tape & Reel Information Dimensions are shown in millimeters (inches) TR TRR TRL 6.3 (.64 ) 5.7 (.69 ) 6.3 (.64 ) 5.7 (.69 ) 2. (.476 ).9 (.469 ) FEED DIRECTION 8. (.38 ) 7.9 (.32 ) FEED DIRECTION NOTES :. CONTROLLING DIMENSION : MILLIMETER. 2. ALL DIMENSIONS ARE SHOW N IN MILLIMETERS ( INCHES ). 3. OUTLINE CONFORMS TO EIA-48 & EIA-54. 3 INCH NOTES :. OUTLINE CONFORMS TO EIA-48. 6 mm Notes: Repetitive rating; pulse width limited by max. junction temperature. Starting T J = 25 C, L = 6.4mH R G = 25Ω, I AS = 5.6A. ƒ I SD 5.6A, di/dt A/µs, V DD V (BR)DSS, T J 75 C Pulse width 300µs; duty cycle 2%. C oss eff. is a fixed capacitance that gives the same charging time as C oss while V DS is rising from 0 to 80% V DSS * When mounted on " square PCB (FR-4 or G- Material). For recommended footprint and soldering techniques refer to application note #AN-994. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (3) 252-75 IR EUROPEAN REGIONAL CENTRE: 439/445 Godstone Rd, Whyteleafe, Surrey CR3 OBL, UK Tel: 44 (0)20 8645 8000 IR CANADA: 5 Lincoln Court, Brampton, Ontario L6T3Z2, Tel: (905) 453 2200 IR GERMANY: Saalburgstrasse 57, 6350 Bad Homburg Tel: 49 (0) 672 96590 IR ITALY: Via Liguria 49, 07 Borgaro, Torino Tel: 39 0 45 0 IR JAPAN: K&H Bldg., 2F, 30-4 Nishi-Ikebukuro 3-Chome, Toshima-Ku, Tokyo 7 Tel: 8 (0)3 3983 0086 IR SOUTHEAST ASIA: Kim Seng Promenade, Great World City West Tower, 3-, Singapore 237994 Tel: 65 (0)838 4630 IR TAIWAN:6 Fl. Suite D. 207, Sec. 2, Tun Haw South Road, Taipei, 673 Tel: 886-(0)2 2377 9936 Data and specifications subject to change without notice. 6/00 www.irf.com
Note: For the most current drawings please refer to the IR website at: http://www.irf.com/package/