Power FINFET, a Novel Superjunction Power MOSFET Wai Tung Ng Smart Power Integration & Semiconductor Devices Research Group Department of Electrical and Computer Engineering Toronto, Ontario Canada, M5S 3G4 E-mail: ngwt@vrg.utoronto.ca 2011 1
Outline Overview of Power Semiconductor Devices Design issues for Low Voltage Super-Junction Devices A Low Voltage Lateral Super-Junction FINFET Basic Idea of SJ-FINFET Structure Device Simulation Works Process Flow and IC Fabrication Experimental Results Summary 2
Applications of Smart Power ICs 100 10 Linear Regulator Automotive AC Motors Load Current (A) 1 0.1 0.01 Digital Bipolar linear Display Switching Regulators Telecom Fluorescent Ballast 0.001 1 10 100 1000 Supply Voltage (V) 3
Worldwide Power Semiconductor Market $16B LV LV LV LV LV LV SWR SWR SWR SWR SWR SWR Source: M. Vukicevic, Data Processing Market to Dominate Power Semiconductor Market in 2007: Market Tracker, isuppli Corp., Q1, 2007. 4
HVNMOS process (cont d) Another example of CMOS compatible HV-CMOS with a variety of 40V devices with minimal process changes. HV n-edmos HV p-edmos Floating Source HV n-fsmos source/body drain source source/body drain source source/body drain source/body SiO 2 SiO 2 SiO 2 SiO 2 SiO 2 SiO 2 SiO 2 SiO 2 SiO 2 SiO 2 p+ n+ n+ n+ p+ n+ p+ p+ p+ n+ p+ n+ n+ n+ p+ n-drift region p-drift region n-drift region Tox = 120Å p-well n-well p-well HV n-well p-substrate source HV n-edsmos HV p-edsmos Low Voltage CMOS drain body source drain body source/body drain source/body SiO SiO SiO 2 SiO 2 SiO 2 p+ p+ p+ SiO 2 2 n+ SiO 2 2 SiO 2 SiO 2 SiO 2 SiO 2 n+ p+ n+ p+ n+ n+ p+ p+ n+ n-drift region n-drift region p-drift region p-drift region p-well n-well p-well n-well Tox = 780Å p-substrate 5
Lateral Super-Junction Power MOSFETs Super-Junction (SJ) power MOSFET is a promising devicetoachievealowr on,sp because the drift region is composed of heavily doped alternating n/p-pillars. However, conventional SJ structure is not very attractive for low voltage MOSFETs (<100V) due to the fact that the channel resistance becomes comparable to the drift region resistance at low voltage ratings. Source p+ n+ p Gate n- n- n+ Drain Source p+ n+ p Gate n p n n p n+ Drain Oxide Oxide Conventional LDMOSFET Superjunction LDMOSFET 6
D Impact of the p/n pillar thickness z y x l y p l n x p d n d p l z S G Specific on-resistance (mωcm2) 1000 100 10 1 0.1 0.01 0.001 Si Majority-Carrier Lateral Devices Si-limit SJ Devices (Lz = 10µm) V gs V 0.0001 ds 10 100 1000 Breakdown voltage (V) Fujihira, Fuji, JJAP, 1997 7
Features of Super-Junction MOSFETs Drift region structure: n-drift region replaced by alternatively stacked, charge-coupled/heavily doped, n- and p- thin layers or pillars. Low specific on-resistance: Current flow only through the heavily doped parallel n-pillars. High breakdown voltage: requires full-depletion of SJ structures (a space-charged region, acting like a pure intrinsic layer); simply depends on drift region length; independent on dose. Charge counterbalance condition: controlling the doping of p- and n-type SJ layers according to the RESURF theory. Fabrication process: complicated and need precise process controls. 8
Lateral Power Devices Performance BV vs. R on-sp has been a performance matrix that many researchers have been chasing for years. R on-sp for power devices in the low voltage range (<100V) depends on many factors. 10 100 1000 R on,sp [ m Ω cm 2 ] 10 3 10 2 10 1 10 0 10-1 10-2 10-3 Toshiba-0.8μm CMOS/BESOI[4] BCD5[7] d=5μm Dual path double-resurf LDMOS[11] SJ-LDMOS/SOS[13] Unbalanced SJ-LDMOS[12] Motorola[3] Thick drift LDMOS LUDMOS[10] BV dss [ V ] IDLDMOS[14] Si_Limit[8],[9] SJVDMOS[9] Cool_MOS[9] SOI Resurf[2]-[6] HexLDMOS Simple Resurf Data Source 9
Main Issue: Low Voltage SJ-MOSFETs Chen et al, NUS, ISPSD, 2007 Sub-200V Si-limit Miura et al, NEC, ISPSD, 2005 10
Basic Idea of SJ-FINFET Structure Source Gate Drain Z Y X Fill trench with p-pillar to form SJ device n-drift region SOI substrate Reduction of channel resistance Reduction of n-drift resistance E-field relaxation (i.e. higher BV) More efficient use of silicon SOI substrate 11
Proposed Lateral SJ-FINFET Structure Cross-section: A-A X Z Y Source Gate A B W top C n n W n C p n+ n+ p S DTI p W p n 2 W n Drain 0.6 0.3 0.3 Poly-Si T Gox 0.035 SJ unit-cell W top p-body BOX 2.5 1.0 SJ unit-cell Wside A p+ n W side n+ L ch L drift n+ p-body B BOX T epi Cross-section: B-B W top 0.3 W p W n 0.3 0.3 0.3 p-substrate DTI p-drift n-drift 2.5 Wside Compatibility with modern CMOS process is an essential design consideration (S p ) (S n ) BOX 0.5 0.5 SJ unit-cell SJ unit-cell 12
Process Flow for the SJ-FINFET Structure (a) p-body implant (b) SJ-drift trench & implant (c) p-pillar diffusion (d) gate trench (e) n-doped poly-si gate (f) n+ source implant (g) p+ contact opening (h) Al metallization 13
Parameters for 3D Simulations These parameters were also used in the fabrication of the prototypes. Parameters Values Drift length, L drift (µm) 3 to 12 n-drift width, W n (µm) 0.6 n-drift doping conc., N D (cm -3 ) 7.4 10 16 p-drift width, W p (µm) 0.3 p-drift doping conc., N A (cm -3 ) 7.4 to 9.8 10 16 p-body doping conc., N p-body (cm -3 ) 5.0 10 17 p-substrate doping conc., N sub (cm -3 ) 2.0 10 14 n+ source/drain contact, N s/d (cm -3 ) 1.0 10 20 p+ contact, N p+ (cm -3 ) 5.0 10 19 Gate oxide thickness, T Gox (nm) 35 Top channel width, W top (µm) 0.6 Side channel width, W side (µm) 2.0 and 3.0 Gate length, L gate (µm) 1.0 Channel length, L ch (µm) 0.5 SOI thickness, T epi (µm) 2.6 and 3.6 DTI depth (µm) 2.0 and 3.0 Buried oxide thickness, T box (µm) 2.0 14
Power FINFET SJ-FINFET Initial MESH Structure Drain SJ drift Gate SJ unit-cell (w/o DTI & Gox) DTI Source Drain p-body BOX p-sub SJ unit-cell (w/ DTI & Gox) channel Source p-body p-drift p-sub 15
Formation of the p/n pillars Implant After annealing @ Y = -3 B, 8e13 cm -2, 45 kev, ± 12 Boron N-epi P-pillar N-epi P-pillar Phosphorus 16
Formation of the n+ source/drain contacts @ Y = -3 P, 5e14 cm -2, 180 kev, ± 45 As, 9e14 cm -2, 200 kev, ± 45 Phosphorus N+ N+ P-body N-epi. N-epi Boron P-body Arsenic 17
I ds (A/cm 2 ) 400 300 200 100 SJ-FINFT Device Simulation Results On-state @ V g =10V @Ld=3.0μm @Ld=3.5μm @Ld=4.0μm @Ld=4.5μm @Ld=5.0μm @Ld=6.0μm @Ld=8.0μm @Ld=12.0μm I ds (A) 1E-04 1E-05 1E-06 1E-07 1E-08 Off-state @Ld=3.0μm @Ld=3.5μm @Ld=4.0μm @Ld=4.5μm @Ld=5.0μm @Ld=6.0μm @Ld=8.0μm @Ld=12.0μm 0 0 0.02 0.04 0.06 0.08 0.1 V ds (V) 1E-09 0 50 100 150 200 V ds (V) @ V ds =1V, L drift = 3.0µm @ L drift = 3.0µm W n = W p = 0.3µm N p-drift = 9.5e16/cm 3 V th ~1.7V N n-drift = 7.4e16/cm 3 18
SJ-FINFT Device Simulation Results (cont d) 120 BV (V) 100 80 60 W side / L drift = 2µm / 6µm W side / L drift = 3µm / 6µm W side / L drift = 2µm / 3µm W side / L drift = 3µm / 3µm Specific on-resistance (mω cm 2 ) 1 Other Published Data Simulated conventional lateral SJ-LDMOS BV 1.9-2.0 Simulated SJ-FINFET (О: 2µm and : 3µm) Si-limit: BV 2.5 40-30 -25-20 -15-10 -5 0 Charge imbalance (N n -N p )/N p (%) 0.1 90V 165V 10 100 Breakdown voltage (V) 19
SJ-FINFT: Device Simulation Results SJ-FINFT Device Simulation Results (cont d) Gate @ L gate =1µm, L ch =0.5µm, L drift =3µm Relaxing the electric field at this point achieves higher breakdown voltage R source R ch R n-drift R drain 0.6 Source Gate n-drift Drain 4.5 Ron,sp (mω cm 2 ) 0.5 0.4 0.3 0.2 0.1 0 SJ SOI-LDMOS source n-drift drain channel W side = 2µm W side = 3µm SJ-FINFET 0 1 2 3 4 5 Y-distance (μm) E field (x10 5 V/cm) 4 3.5 3 2.5 2 1.5 1 0.5 0 0 1 2 3 4 5 (μm) L drift E c for Si ~ 5 x 10 5 V/cm, BV~(E c L drift ) / 2 20
Final Chip Layout & Die Image 50000µm (Mask=5cm, Die=1cm) 50000µm (Mask=5cm, Die=1cm) Total 9 Mask Layers 21
Fabricated SJ-FINFETs: Optical & SEM Images Drain Poly-Si: Top Gate Drain Poly-Si: Top Gate Gate Gate P-pillar Trench Source Poly-Si: Trench Gate P-pillar Trench Source Poly-Si: Trench Gate Poly-Si: Trench Gate Source Trench P-pillar Trench Drain Trench L drift Poly-Si: Top Gate 22
SJ-FINFETs: After Al-Metallization L drift = 3.5µm L drift = 6.0µm L drift = 10.0µm L drift = 12.0µm 23
Measured Data: Transfer I-V Characteristics L drift =3.5µm, W=200µm, T ox = 35nm @ V ds = 0.1V 6E-03 5E-03 4E-03 I ds (A) 3E-03 2E-03 1E-03 The measured threshold voltage of the SJ-FINFET was approximately 1.7V V th ~ 1.7V 0E+00 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 V gate (V) 24
Measured Data: Output I-V Characteristics The R on,sp of the SJ-FINFET is approximately 30% smaller than that of the conventional SJ-LDMOSFET. SJ-LDMOS: L drift =3.5µm, W=200µm SJ-FINFET: Ldrift=3.5µm, W=200µm 0.10 0.10 0.09 0.08 0.09 0.08 V g = 10V I ds (A) 0.07 0.06 0.05 0.04 V g = 10V V g = 8V V g = 6V I ds (A) 0.07 0.06 0.05 0.04 V g = 8V V g = 6V 0.03 0.02 0.01 0.00 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 V ds (V) V g = 4V V g = 2V 0.03 0.02 0.01 0.00 V g = 4V V g = 2V 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 V ds (V) 25
Measured Data: BV versus R on,sp The measured data is comparable with other published data and it shows a good agreement in the data trend between the simulation and measurement. For similar BV ratings, about 30% lower R on,sp was found in the fabricated Specific on-resistance (mω cm 2 ) 1.4 1.2 1 0.8 0.6 0.4 0.2 0 Other published data Simulated SJ-FINFET Fabricated SJ-FINFET Fabricated SJ-LDMOS Fabricated SJ-FINFET [1] Fabricated [3] SJ-LDMOS [3] [2] [4] Si-limit [1] [5] [6] 0 20 40 60 80 100 120 140 Breakdown voltage (V) [7] Simulated SJ-FINFET Data from [1], [3], [7] are for conventional LDMOSFETs Data from [2], [4]-[6] are for conventional SJ-LDMOSFETs 26
Summary Low voltage lateral SJ-FINFET devices with deep trench p-drift region were proposed and fabricated to improve the electrical characteristics of conventional planar gate SJ-LDMOSFETs. For the similar BV ratings, the specific on-resistances of the fabricated SJ-FINFET devices were approximately 30% lower than that of the fabricated SJ- LDMOSFETs. The current work represents the first experimental confirmation that the super-junction concept is advantageous for sub-200v applications. More details will be presented at IEDM 2010. 27
Acknowledgements Visiting Scientist: Yasuhiko Onishi, Fuji Electric, Japan Prof. Johnny K. O. Sin, Hong Kong University of Science & Technology Staff in Nano-electronic Fabrication Facility (NFF), Hong Kong University of Science & Technology Auto21 Networks of Centres of Excellence of Canada Natural Sciences and Engineering Research Council of Canada U of T Open Fellowship 28