Features Floating channel designed for bootstrap operation Fully operational to + V Tolerant to negative transient voltage, dv/dt immune Gate drive supply range from V to V Undervoltage lockout for both channels. V and V input logic compatible Matched propagation delay for both channels Logic and power ground +/- V offset Lower di/dt gate driver for better noise immunity Output source/sink current capability. A/.8 A RoHS compliant Data Sheet No. PD IRS8/IRS8(S)PbF HIGH AND LOW SIDE DRIVER Packages Feature Comparison Part Input logic Crossconduction prevention logic 8-Lead PDIP IRS8 8-Lead SOIC IRS8S Deadtime (ns) Ground Pins 8 COM HIN/LIN no none 8 VSS/COM 8 Internal COM HIN/LIN yes 8 Program - VSS/COM 8 Internal COM IN/SD yes 8 Program - VSS/COM -Lead PDIP IRS8 -Lead SOIC IRS8S Description The IRS8/IRS8 are high voltage, high speed power MOSFET and IGBT drivers with independent high-side and low-side referenced output channels. Proprietary HVIC and latch immune CMOS technologies enable ruggedized monolithic construction. The logic input is compatible with standard CMOS or LSTTL output, down to. V logic. The output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high-side configuration which operates up to V. ton/toff (ns) 8/ 8/ 8/7 Typical Connection up to V V B HIN HIN HO LIN LIN V S TO LOAD COM LO IRS8 HO IRS8 up to V V B (Refer to Lead Assignments for correct pin configuration). These diagrams show electrical connections only. Please refer to our Application Notes and DesignTips for proper circuit board layout. HIN LIN V SS HIN LIN V SS V S COM LO TO LOAD www.irf.com
Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Symbol Definition Min. Units V B High-side floating absolute voltage -. (Note ) V S High-side floating supply offset voltage V B - V B +. V HO High-side floating output voltage V S -. V B +. Low-side and logic fixed supply voltage -. (Note ) V LO Low-side output voltage -. +. V IN Logic input voltage (HIN & LIN) V SS -. +. V SS Logic ground (IRS8 only) - +. dv S /dt Allowable offset supply voltage transient V/ns P D Package power dissipation @ T A + C Rth JA Thermal resistance, junction to ambient (8-lead PDIP). (8-lead SOIC). (-lead PDIP). (-lead SOIC). (8-lead PDIP) (8-lead SOIC) (-lead PDIP) 7 (-lead SOIC) T J Junction temperature T S Storage temperature - T L Lead temperature (soldering, seconds) Note : All supplies are fully tested at V and an internal V clamp exists for each supply. Recommended Operating Conditions The input/output logic timing diagram is shown in Fig.. For proper operation the device should be used within the recommended conditions. The V S and V SS offset rating are tested with all supplies biased at a V differential. Symbol Definition Min. Units VB High-side floating supply absolute voltage V S + V S + V S High-side floating supply offset voltage Note V W C/W C V HO High-side floating output voltage V S V B Low-side and logic fixed supply voltage V LO Low-side output voltage V V IN Logic input voltage (HIN & LIN) V SS V SS Logic ground (IRS8 only) - T A Ambient temperature - C Note : Logic operational for V S of - V to + V. Logic state held for V S of - V to -V BS. (Please refer to the Design Tip DT97- for more details). www.irf.com
Dynamic Electrical Characteristics V BIAS (, V BS ) = V, V SS = COM, C L = pf, T A = C. Symbol Definition Min. Units Test Conditions ton Turn-on propagation delay 8 7 V S = V toff Turn-off propagation delay V S = V or V MT Delay matching, HS & LS turn-on/off tr Turn-on rise time tf Turn-off fall time ns V S = V Static Electrical Characteristics V BIAS (, V BS ) = V, V SS = COM and T A = C unless otherwise specified. The V IL, V IH, and I IN parameters are referenced to V SS /COM and are applicable to the respective input leads HIN and LIN. The V O, I O, and Ron parameters are referenced to COM and are applicable to the respective output leads: HO and LO. Symbol Definition Min. Units Test Conditions V IH Logic input voltage. = V to V V IL Logic input voltage.8 V V OH High level output voltage, V BIAS - V O. I O = A V OL Low level output voltage, V O. I O = ma I LK Offset supply leakage current V B = V S = V I QBS Quiescent V BS supply current I QCC Quiescent supply current I IN+ Logic input bias current V IN = V I IN- Logic input bias current. V IN = V UV+ V BSUV+ UV- V BSUV- and V BS supply undervoltage positive going threshold and V BS supply undervoltage negative going threshold 8. 8.9 9.8 7. 8. 9. UVH Hysteresis..7 µa V V IN = V or V V BSUVH IO+ Output high short circuit pulsed current..9 IO- Output low short circuit pulsed current.8. A V O = V, PW µs V O = V, PW µs www.irf.com
www.irf.com Functional Block Diagrams 8 LIN UV DETECT DELAY HIN VS HO VB PULSE FILTER HV LEVEL SHIFTER R R S Q UV DETECT PULSE GENERATOR VSS/COM LEVEL SHIFT VSS/COM LEVEL SHIFT COM LO VCC 8 LIN UV DETECT DELAY COM LO VCC HIN VSS VS HO VB PULSE FILTER HV LEVEL SHIFTER R R S Q UV DETECT PULSE GENERATOR VSS/COM LEVEL SHIFT VSS/COM LEVEL SHIFT
Lead Definitions Symbol Description HIN LIN VSS V B HO V S LO COM Logic input for high-side gate driver output (HO), in phase (IRS8/IRS8) Logic input for low-side gate driver output (LO), in phase (IRS8/IRS8) Logic ground (IRS8 only) High-side floating supply High-side gate drive output High-side floating supply return Low-side and logic fixed supply Low-side gate drive output Low-side return Lead Assignments HIN V B 8 HIN V B 8 LIN HO 7 LIN HO 7 COM V S COM V S LO LO 8-Lead PDIP 8-Lead SOIC IRS8PbF IRS8SPbF 7 HIN LIN V B VSS HO V S COM LO -Lead PDIP 9 8 7 HIN LIN V B VSS HO V S COM LO -Lead SOIC 9 8 IRS8PbF IRS8SPbF www.irf.com
Figure. Input/Output Timing Diagram Figure. Switching Time Waveform Definitions Figure. Delay Matching Waveform Definitions www.irf.com
Turn-On Propagation Delay (ns) M ax. - - 7 Turn-On Propagation Delay (ns) M ax. 8 Figure A. Turn-On Propagation Delay Figure B. Turn-On Propagation Delay vs. Supply Voltage Turn-Off Propagation Delay (ns) - - 7 Turn-Off Propagation Delay (ns) M ax. 8 Figure A. Turn-Off Propagation Delay Figure B. Turn-Off Propagation Delay vs. Supply Voltage www.irf.com 7
Turn-On Rise Time (ns) 8 Max - - 7 Turn-On Rise Time (ns) 8 8 Figure A. Turn-On Rise Time vs. Temperature Figure B. Turn-On Rise Time vs. Supply Voltage 8 8 Turn-Off Fall Time (ns) Typ Turn-Off Fall Time (ns) - - 7 Figure 7A. Turn-Off Fall Time vs. Temperature 8 Figure 7B. Turn-Off Fall Time vs. Supply Voltage www.irf.com 8
Input Voltage (V) Min. Input Voltage (V) Min. - - 7 8 V BAIS Figure 8A. Logic "" Input Voltage Figure 8B. Logic "" Input oltage vs. Supply Voltage Logic "" Input Voltage (V) - - 7 Logic "" Input Voltage (V) 8 Figure 9A. Logic "" Input Voltage Figure 9B. Logic "" Input Voltage vs. Supply Voltage www.irf.com 9
High Level Output Voltage (V)...... - - 7 High Level Output Voltage (V)..... Max. 8 V BAIS Figure A. High Level Output Voltage (Io = ma) Figure B. High Level Output Voltage vs. Supply Voltage (Io = ma).. Low Level Output (V).... Low Level Output (V)..... - - 7. 8 Figure A. Low Level Output Figure B. Low Level Output vs. Supply Voltage www.irf.com
Offset Supply Leakage Current ( µa) - - 7 Offset Supply Leakage Current (µa) V B Boost Voltage (V) Figure A. Offset Supply Leakage Current Figure B. Offset Supply Leakage Current vs. V B Boost Voltage V BS Supply Current ( µa) - - 7 Mi n. V BS Supply Current (µa) 8 Mi n. V BS Floating Figure A. V BS Supply Current Figure B. V BS Supply Current vs. V BS Floating Supply Voltage www.irf.com
Supply Current (µa) Mi n. Supply Current (µa) Min. - - 7 8 Figure A. Supply Current vs. Temperature Figure B. Supply Current vs. Supply Voltage Logic "" Input Bias Current ( µa) 8 - - 7 Logic "" Input Bias Current (µa) 8 8 Figure A. Logic "" Input Bias Current Figure B. Logic "" Input Bias Current vs. Supply Voltage www.irf.com
Lo gic "" Input Bia s Current (µa) Max - - 7 Temperature ( C) Figure A. Logic "" Input Bias Current Logic "" Input Bias Current (µa) Max 8 Figure B. Logic "" Input Bias Current vs. Voltage V C C and V B S UV Thr es hold (+) (V) 9 Min. 8 7 - - 7 V C C a n d V B S U V T h r e s h o l d ( - ) ( V ) 9 8 Min. 7 - - 7 Figure 7. and V BS Undervoltage Threshold (+) Figure 8. and V BS Undervoltage Threshold (-) www.irf.com
Output Source Current (A) Min. - - 7 Output Source Current (A) Min. 8 Figure 9A. Output Source Current Figure 9B. Output Source Current vs. Supply Voltage. Output Sink Current (A)... Min. Output Sink Current (A) Min.. - - 7 Figure A. Output Sink Current 8 Figure B. Output Sink Current vs. Supply Voltage www.irf.com
Temprature ( o C) 8 V 7 V V Temprature ( o C) 8 V 7 V V Figure. IRS8 vs. Frequency (IRFBC), = Ω, Figure. IRS8 vs. Frequency (IRFBC), = Ω, V 7 V V 8 V 7 V V 8 Figure. IRS8 vs. Frequency (IRFBC), = Ω, Figure. IRS8 vs. Frequency (IRFPE), = Ω, www.irf.com
8 V 7 V V 8 V 7 V V Figure. IRS8 vs. Frequency (IRFBC), = Ω, Figure. IRS8 vs. Frequency (IRFBC), = Ω, V 7 V 8 V 7 V V 8 V Figure 7. IRS8 vs. Frequency (IRFBC), = Ω, Figure 8. IRS8 vs. Frequency (IRFPE), = Ω, www.irf.com
8 V 7 V V 8 V 7 V V Figure 9. IRS8S vs. Frequency (IRFBC), = Ω, Figure. IRS8S vs. Frequency (IRFBC), = Ω, V 7 V V 7 V V 8 V Figure. IRS8S vs. Frequency (IRFBC), = Ω, Tempreture ( o C) 8 Figure. IRS8S vs. Frequency (IRFPE), = Ω, www.irf.com 7
8 V 7 V V Figure. IRS8S vs. Frequency (IRFBC), = Ω, 8 V 7 V V Figure. IRS8S vs. Frequency (IRFBC), = Ω, V 7 V V 8 V 7 V V 8 Figure. IRS8S vs. Frequency (IRFBC), = Ω, Figure. IRS8S vs. Frequency (IRFPE), = Ω, www.irf.com 8
Case outlines 8-Lead PDIP - - (MS-AB) A E X D 8 7 e B H. [.] A. [.] X.7 [.] FOOTPRINT 8X.7 [.8] 8X.78 [.7] DIM INC HES MILLIMETERS MIN MAX MIN MAX A A...88.98...7. b.... c.7.98.9. D E.89.97.98.7.8.8.. e. BASIC.7 BASIC e. BASIC. BASIC H K L y.8.99...9. 8.8.....7 8 e A C y K x 8X b A. [.] C A B. [.] 8X L 7 8X c NOTES:. DIMENSIONING & TOLERANCING PER ASME Y.M-99.. CONTROLLING DIMENSION: MILLIMETER. DIMENSIONS ARE SHOWN IN MILLIMETERS [INCHES].. OUTLINE CONFORMS TO JEDEC OUTLINE MS-AA. 8-Lead SOIC DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS. MOLD PROTRUSIONS NOT TO EXCEED. [.]. DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS. MOLD PROTRUSIONS NOT TO EXCEED. [.]. 7 DIMENSION IS THE LENGTH OF LEAD FOR SOLDERING TO A SUBSTRATE. -7 - (MS-AA) www.irf.com 9
-Lead PDIP - - (MS-AC) -Lead SOIC (narrow body) -9 - (MS-AB) www.irf.com
Tape & Reel 8-lead SOIC LOADED TA PE FEED DIRECTION B A H D F C N OTE : CONTROLLING D IMENSION IN MM E G CARRIER TAPE DIMENSION FOR 8SOICN M etr ic Im p erial Code Min Max Min Max A 7.9 8... 8 B.9... C.7...8 D.... 8 E... 8. F.... 8 G. n/a.9 n/a H... 9. F D E C B A G H REEL DIMENSIONS FOR 8SOICN M etr ic Im p erial Code Min Max Min Max A 9...97. B.9..8.8 C.8...9 D.9..7 7. 9 E 98...88. F n/a 8. n/a.7 G. 7..7.7 H...88. www.irf.com
Tape & Reel -lead SOIC LOADED TA PE FEED DIRECTION B A H D F C N OTE : CONTROLLING D IMENSION IN MM E G CARRIER TAPE DIMENSION FOR SOICN M etr ic Im p erial Code Min Max Min Max A 7.9 8... 8 B.9... C.7..8. D 7. 7..9. 99 E.... F 9. 9..7. 78 G. n/a.9 n/a H... 9. F D E C B A G H REEL DIMENSIONS FOR SO IC N M etr ic Im p erial Code Min Max Min Max A 9...97. B.9..8.8 C.8...9 D.9..7 7. 9 E 98...88. F n/a. n/a.88 G 8...78.8 H. 8...7 www.irf.com
LEADFREE PART MARKING INFORMATION Part number Date code IRxxxxxx S YWW? IR logo Pin Identifier? MARKING CODE P Lead Free Released Non-Lead Free Released?XXXX Lot Code (Prod mode - digit SPN code) Assembly site code Per SCOP - ORDER INFORMATION 8-Lead PDIP IRS8PbF -Lead PDIP IRS8PbF 8-Lead SOIC IRS8SPbF -Lead SOIC IRS8SPbF 8-Lead SOIC Tape & Reel IRS8STRPbF -Lead SOIC Tape & Reel IRS8STRPbF SOIC8 & are MSL qualified. This product has been designed and qualified for the industrial level.. Qualification standards can be found at www.irf.com IR WORLD HEADQUARTERS: Kansas St., El Segundo, California 9 Tel: () -7 Data and specifications subject to change without notice. /7/ www.irf.com