Data Sheet No. PD-O Features Floating channel designed for bootstrap operation Fully operational to +V Tolerant to negative transient voltage dv/dt immune Gate drive supply range from to V Undervoltage lockout.v, V and V input logic compatible Cross-conduction prevention logic Internally set deadtime High side output in phase with input Shut down input turns off both channels Matched propagation delay for both channels Description The IR are high voltage, high speed power MOSFET and IGBT drivers with dependent high and low side referenced output channels. Proprietary HVIC and latch immune CMOS technologies enable ruggedized monolithic construction. The logic input is compatible with standard CMOS or LSTTL output, down to.v logic. The output drivers feature a high pulse cur- Typical Connection HIGH AND W SIDE DRIVER Product Summary V OFFSET I O +/- V OUT t on/off (typ.) Deadtime (typ.) Packages Lead SOIC IRS V max. ma / ma - V & ns ns Lead PDIP IR rent buffer stage designed for minimum driver cross-conduction. The floating channel can be used to drive an N- channel power MOSFET or IGBT in the high side configuration which operates from to volts. up to V IR(S) V CC V CC V B COM V S TO AD (Refer to Lead Assignment for correct pin configuration)
IR(S) Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Symbol Definition Units V B High side floating absolute voltage -. V S High side floating supply offset voltage V B - V B +. V High side floating output voltage V S -. V B +. V CC Low side and logic fixed supply voltage -. V Low side output voltage -. V CC +. V Logic input voltage ( & ) -. V CC +. dv s /dt Allowable offset supply voltage transient V/ns P D Package power dissipation @ T A + C ( lead PDIP). ( lead SOIC). W Rth JA Thermal resistance, junction to ambient ( lead PDIP) C/W ( lead SOIC) T J Junction temperature T S Storage temperature - T L Lead temperature (soldering, seconds) V C Recommended Operating Conditions The Input/Output logic timing diagram is shown in Figure. For proper operation the device should be used within the recommended conditions. The V S offset rating is tested with all supplies biased at V differential. Symbol Definition Units V B High side floating supply absolute voltage V S + V S + V S High side floating supply offset voltage Note V High side floating output voltage V S V B V CC Low side and logic fixed supply voltage V V Low side output voltage V CC V Logic input voltage ( & ) V CC T A Ambient temperature - C Note : Logic operational for V S of - to +V. Logic state held for V S of -V to -V BS.
IR(S) Dynamic Electrical Characteristics V BIAS (V CC, V BS ) = V, C L = pf and T A = C unless otherwise specified. Symbol Definition Units Test Conditions ton Turn-on propagation delay V S = V toff Turn-off propagation delay V S = V tsd Shutdown propagation delay tr Turn-on rise time tf Turn-off fall time 9 DT Deadtime, LS turn-off to HS turn-on & HS turn-on to LS turn-off MT Delay matching, HS & LS turn-on/off ns Static Electrical Characteristics V BIAS (V CC, V BS ) = V and T A = C unless otherwise specified. The V, V TH and I parameters are referenced to COM. The V O and I O parameters are referenced to COM and are applicable to the respective output leads: or. Symbol Definition Units Test Conditions V IH Logic () & Logic () input voltage V CC = V to V V IL Logic () & Logic () input voltage. V CC = V to V V,TH+ input positive going threshold V V CC = V to V V,TH- input negative going threshold. V CC = V to V V OH High level output voltage, V BIAS - V O I O = A V OL Low level output voltage, V O mv I O = A I LK Offset supply leakage current V B = V S = V I QBS Quiescent V BS supply current V = V or V I QCC Quiescent V CC supply current µa V = V or V I + Logic input bias current V = V I - Logic input bias current V = V V CCUV+ V CC supply undervoltage positive going.9 9. threshold V CCUV- V CC supply undervoltage negative going.. 9 V threshold I O+ Output high short circuit pulsed current V O = V PW µs ma I O- Output low short circuit pulsed current V O = V PW µs
IR(S) Functional Block Diagram V B DEAD TIME HV LEVEL SHIFT PULSE FILTER R S Q PULSE GEN V S Vcc UV DETECT V CC DEAD TIME COM Lead Definitions Symbol V B V S V CC COM Description Logic input for high and low side gate driver outputs ( and ), in phase with Logic input for shutdown High side floating supply High side gate drive output High side floating supply return Low side and logic fixed supply Low side gate drive output Low side return Lead Assignments V CC V B V CC V B V S V S COM COM Lead PDIP Lead SOIC IR IRS
IR(S) () () % % t on t r t off t f 9% 9% % % Figure. Input/Output Timing Diagram Figure. Switching Time Waveform Definitions % % % t sd 9% 9% DT % DT 9% Figure. Shutdown Waveform Definitions % Figure. Deadtime Waveform Definitions () () % % % MT MT 9% Figure. Delay Matching Waveform Definitions
IR(S) Turn-On Delay Time (ns) - - Figure A. Turn-On Time Turn-On Delay Time (ns) Figure B. Turn-On Time vs Supply Voltage Turn-On Delay Time (ns Input Voltage (V) Figure C. Turn-On Time vs Input Voltage Turn-Off Delay Time (ns) Ty p. - - Figure A. Turn-Off Time Turn-Off Delay Time (ns) Turn-Off Delay Time (ns Typ Input Voltage (V) Figure B. Turn-Off Time vs Supply Voltage Figure C. Turn-Off Time vs Input Voltage
IR(S) Shutdown Delay Time (ns) - - Shutdown Delay Time (ns) Figure A. Shutdown Time Figure B. Shutdown Time Turn-On Rise Time (ns) - - Turn-On Rise Time (ns) Figure 9A. Turn-On Rise Time Figure 9B. Turn-On Rise Time Turn-Off Fall Time (ns) - - Turn-Off Fall Time (ns) Max. Figure A. Turn-Off Fall Time Figure B. Turn-Off Fall Time
IR(S) Deadtime (ns) Deadtime (ns) Max. - - Figure A. Deadtime Figure B. Deadtime Input Voltage (V) Input Voltage (V) - - Vcc Supply Voltage (V) Figure A. Logic "" () & Logic () & Inactive Input Voltage Figure B. Logic "" () & Logic () & Inactive Input Voltage Input Voltage (V).... Input Voltage (V).... - - Figure A. Logic "" () & Logic () & Active Input Voltage Vcc Supply Voltage (V) Figure B. Logic "" () & Logic () & Active Input Voltage
IR(S) High Level Output Voltage (V).... - - High Level Output Voltage (V).... Vcc Supply Voltage (V) Figure A. High Level Output Figure B. High Level Output Low Level Output Voltage (V).... - - Low Level Output Voltage (V).... Vcc Supply Voltage (V) Figure A. Low Level Output Figure B. Low level Output Offset Supply Leakage Current (µa) - - Offset Supply Leakage Current (µa) VB Boost Voltage (V) Figure A. Offset Supply Current Figure B. Offset Supply Current 9
IR(S) VBS Supply Current (µa) 9 Ty p. VBS Supply Current (µa) 9 Max. Ty p. - - VBS Floating Supply Voltage (V) Figure A. VBS Supply Current Figure B. VBS Supply Current Vcc Supply Current (µa) Vcc Supply Current (µa) - - Vcc Supply Voltage (V) Figure A. Vcc Supply Current Figure B. Vcc Supply Current Logic Input Current (µa) Ty p. Logic Input Current (µa) - - Vcc Supply Voltage (V) Figure 9A. Logic"" Input Current Figure 9B. Logic"" Input Current
Output Source Current (ma) Output Source Current (ma) IR(S) Logic Input Current (µa) - - Logic "" Input Current (ua) VCC Supply Voltage (V) Figure A. Logic "" Input Current Figure B. Logic "" Input Current VCC UV Threshold +(V) 9 Ty p. - - Figure A. Vcc Undervoltage Threshold(+) VCC UV Threshold - (V) 9 - - Figure B. Vcc Undervoltage Threshold(-) - - Figure A. Output Source Current Figure B. Output Source Current
IR(S) Output Sink Current (ma) Ty p. - - Output Sink Current (ma) Figure A. Output Sink Current Figure B. Output Sink Current Case Outlines Lead PDIP -
IR(S) - Lead SOIC IR WORLD HEADQUARTERS: Kansas St., El Segundo, California 9 Tel: () - Data and specifications subject to change without notice. //