5841 ND 5842 5841 ND 5842 BiMOS II 8-BIT SERIL-INPUT, LTCHED DRIVERS Data Sheet 26185.14B* UCN5841 & UCN5842 BSOLUTE MXIMUM RTINGS at 25 C Free-ir Temperature Output Voltage, V CE (UCN5841 & 5841SLW)...... 50 V (UCN5842)................. 80 V Output Voltage, V CE(sus) (UCN5841 & 5841SLW)..... 35 V (UCN5842)................ 50 V Logic Supply Voltage Range,................. 4.5 V to 15 V with Reference to V EE...... 25 V Emitter Supply Voltage, V EE........ -20 V Input Voltage Range, V IN........... -0.3 V to + 0.3 V Continuous Output Current, I OUT..................... 500 m Package Power Dissipation, P D................... See Graph Operating Temperature Range, T................ -20 C to +85 C Storage Temperature Range, T S................ -55 C to +150 C For inductive load applications. Dwg. No. -12,659 Caution: CMOS devices have input static protection but are susceptible to damage when exposed to extremely high static electrical charges. The merging of low-power CMOS logic and bipolar output power drivers permit the UCN5841/42 and 5841SLW integrated circuits to be used in a wide variety of peripheral power driver applications. The three devices in this series each have an eight-bit CMOS shift register and CMOS control circuitry, eight CMOS data latches, and eight bipolar current-sinking Darlington output drivers. The 500 m NPN Darlington outputs, with integral transient-suppression diodes, are suitable for use with relays, solenoids, and other inductive loads. Except for the maximum driver output voltage ratings, the UCN5841, 5841SLW, and UCN5842 are identical. The UCN5842 offers premium performance with a minimum output-breakdown voltage rating of 80 V (50 V sustaining). ll drivers can be operated with a split supply where the negative supply is up to -20 V. BiMOS II devices have higher data-input rates than the earlier BiMOS circuits. With a 5 V logic supply, they will typically operate at better than 5 MHz. With a 12 V supply, significantly higher speeds are obtained. The CMOS inputs are compatible with standard CMOS and NMOS logic levels. TTL circuits may require the use of appropriate pull-up resistors. By using the serial data output, drivers can be cascaded for interface applications requiring additional drive lines. Suffix devices are furnished in a standard 18-pin plastic DIP; suffix LW indicates a 20-lead wide-body SOIC. FETURES To 3.3 MHz Data-Input Rate CMOS, NMOS, TTL Compatible Inputs Internal Pull-Up/Pull-Down Resistors Low-Power CMOS Logic and Latches, High-Voltage Current-Sink Outputs Output Transient-Protection Diodes Single or Split Supply Operation DIP or SOIC Packaging utomotive Capable lways order by complete part number, e.g., 5841SLW.
FUNCTIONL BLOCK DIGRM ( Package Shown) Dwg. No. -12,661 POWER GROUND CLOCK SERIL DT IN GROUND LOGIC SUPPLY SERIL DT OUT STROBE OUTPUT ENBLE POWER GROUND NO CONNECT. 1 2 3 4 5 6 7 8 9 10 5841SLW SUB CLK ST OE SUB NC LTCHES SHIFT REGISTER NC 20 19 18 17 16 15 14 13 12 11 OUT 1 OUT 2 OUT 3 OUT 4 OUT 5 OUT 6 OUT 7 OUT 8 K NO CONNECT. Dwg. PP-029-3 LLOWBLE PCKGE POWER DISSIPTION IN WTTS 2.5 2.0 1.5 1.0 0.5 0 25 SUFFIX '', R = 60 C/W θj SUFFIX 'LW', R = 70 C/W θj 50 75 100 125 150 MBIENT TEMPERTURE IN C Dwg. GS-009-1 115 115 Northeast Cutoff, Box 15036 Worcester, Northeast Massachusetts Cutoff, Box 15036 01615-0036 (508) 853-5000 Worcester, Copyright Massachusetts 1985, 1996 llegro 01615-0036 MicroSystems, (508) 853-5000 Inc.
ELECTRICL CHRCTERISTICS at T = +25 C, = 5 V, V EE = 0 V (unless otherwise specified). pplicable Limits Characteristic Symbol Devices Test Conditions Min. Max. Unit Output Leakage Current I CEX 5841* V OUT = 50 V 50 µ V OUT = 50 V, T = +70 C 100 µ UCN5842 V OUT = 80 V 50 µ V OUT = 80 V, T = +70 C 100 µ Collector-Emitter V CE(ST) ll I OUT = 100 m 1.1 V Saturation Voltage I OUT = 200 m 1.3 V I OUT = 350 m, = 7.0 V 1.6 V Collector-Emitter V CE(sus) 5841* I OUT = 350 m, L = 2 mh 35 V Sustaining Voltage UCN5842 I OUT = 350 m, L = 2 mh 50 V Input Voltage V IN(0) ll 0.8 V V IN(1) ll = 12 V 10.5 V = 10 V 8.5 V = 5.0 V 3.5 V Input Resistance R IN ll = 12 V 50 kω = 10 V 50 kω = 5.0 V 50 kω Supply Current I DD(ON) ll ll Drivers ON, = 12 V 16 m ll Drivers ON, = 10 V 14 m ll Drivers ON, = 5.0 V 8.0 m I DD(OFF) ll ll Drivers OFF, = 12 V 2.9 m ll Drivers OFF, = 10 V 2.5 m ll Drivers OFF, = 5.0 V 1.6 m Clamp Diode I R 5841* V R = 50 V 50 µ Leakage Current UCN5842 V R = 80 V 50 µ Clamp Diode V F ll I F = 350 m 2.0 V Forward Voltage * Complete part number includes a prefix ( or UCN) and a suffix (SLW or ).
TYPICL INPUT CIRCUITS CLOCK DT IN C B D E F STROBE STROBE OUTPUT IN ENBLE OUTPUT ENBLE OUT N G Dwg. No. -12,627 Dwg. EP-010-3 CLOCK SERIL DT IN Dwg. EP-010-4 TIMING CONDITIONS (T = +25 C, = 5.0 V, Logic Levels are and Ground). Minimum Data ctive Time Before Clock Pulse (Data Set-Up Time)..................................... 75 ns B. Minimum Data ctive Time fter Clock Pulse (Data Hold Time)....................................... 75 ns C. Minimum Data Pulse Width................................. 150 ns D. Minimum Clock Pulse Width................................ 150 ns E. Minimum Time Between Clock ctivation and Strobe............ 300 ns F. Minimum Strobe Pulse Width............................... 100 ns G. Typical Time Between Strobe ctivation and Output Transition..................................... 500 ns TYPICL OUTPUT DRIVER K OUT V EE SUB Dwg. EP-021-8 Serial Data present at the input is transferred to the shift register on the logic 0 to logic 1 transition of the CLOCK input pulse. On succeeding CLOCK pulses, the registers shift data information towards the SERIL DT OUTPUT. The SERIL DT must appear at the input prior to the rising edge of the CLOCK input waveform. Information present at any register is transferred to its respective latch when the STROBE is high (serial-to-parallel conversion). The latches will continue to accept new data as long as the STROBE is held high. pplications where the latches are bypassed (STROBE tied high) will require that the ENBLE input be high during serial data entry. When the ENBLE input is high, all of the output buffers are disabled (OFF) without affecting the information stored in the latches or shift register. With the ENBLE input low, the outputs are controlled by the state of the latches. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
TYPICL PPLICTION RELY/SOLENOID DRIVER Using Split Supply UCN5842 Dwg. No. -12,547 TRUTH TBLE Serial Shift Register Contents Serial Latch Contents Output Contents Data Clock Data Strobe Output Input Input I 1 I 2 I 3... I 8 Output Input I 1 I 2 I 3... I 8 Enable I 1 I 2 I 3... I 8 H H R 1 R 2... R 7 R 7 L L R 1 R 2... R 7 R 7 X R 1 R 2 R 3... R 8 R 8 X X X... X X L R 1 R 2 R 3... R 8 P 1 P 2 P 3... P 8 P 8 H P 1 P 2 P 3... P 8 L P 1 P 2 P 3... P 8 L = Low Logic Level H = High Logic Level X = Irrelevant P = Present State R = Previous State X X X... X H H H H... H
UCN5841 and UCN5842 18 Dimensions in Inches 10 0.014 0.008 0.280 0.240 0.430 MX 0.300 1 0.070 0.100 9 0.045 0.920 0.880 0.005 MIN 0.210 MX 0.015 MIN 0.150 0.115 0.022 0.014 Dwg. M-001-18 in 18 Dimensions in Millimeters (Based on 1 = 25.4 mm) 10 0.355 0.204 7.11 6.10 7.62 10.92 MX 1 1.77 2.54 9 1.15 23.37 22.35 0.13 MIN 5.33 MX 0.39 MIN 3.81 2.93 0.558 0.356 Dwg. M-001-18 mm NOTES: 1. Exact body and lead configuration at vendor s option within limits shown. 2. Lead spacing tolerance is non-cumulative. 3. Lead thickness is measured at seating plane or below. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
5841SLW Dimensions in Inches (Based on 1 mm = 0.03937 ) 20 11 0.0125 0.0091 0.2992 0.2914 0.419 0.394 0.050 0.016 0.020 0.013 1 2 3 0.5118 0.4961 0.050 0 TO 8 0.0926 0.1043 0.0040 MIN. Dwg. M-008-20 in 20 Dimensions in Millimeters 11 0.32 0.23 7.60 7.40 10.65 10.00 1.27 0.40 0.51 0.33 1 2 3 13.00 12.60 1.27 0 TO 8 2.65 2.35 0.10 MIN. Dwg. M-008-20 mm NOTES: 1. Exact body and lead configuration at vendor s option within limits shown. 2. Lead spacing tolerance is non-cumulative.
BiMOS II (Series 5800) & DBiC IV (Series 6800) INTELLIGENT POWER INTERFCE DRIVERS SELECTION GUIDE Function Output Ratings * Part Number SERIL-INPUT LTCHED DRIVERS 8-Bit (saturated drivers) -120 m 50 V 5895 8-Bit 350 m 50 V 5821 8-Bit 350 m 50 V 5841 8-Bit 350 m 80 V 5842 9-Bit 1.6 50 V 5829 10-Bit (active pull-downs) -25 m 60 V 5810-F 12-Bit (active pull-downs) -25 m 60 V 5811 20-Bit (active pull-downs) -25 m 60 V 5812-F 32-Bit (active pull-downs) -25 m 60 V 5818-F 32-Bit 100 m 30 V 5833 32-Bit (saturated drivers) 100 m 40 V 5832 PRLLEL-INPUT LTCHED DRIVERS 4-Bit 350 m 50 V 5800 8-Bit -25 m 60 V 5815 8-Bit 350 m 50 V 5801 SPECIL-PURPOSE FUNCTIONS Unipolar Stepper Motor Translator/Driver 1.25 50 V 5804 ddressable 28-Line Decoder/Driver 450 m 30 V 6817 * Current is maximum specified test condition, voltage is maximum rating. See specification for sustaining voltage limits. Negative current is defined as coming out of (sourcing) the output. Complete part number includes additional characters to indicate operating temperature range and package style. Internal transient-suppression diodes included for inductive-load protection. llegro reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the design of its products. Components made under military approvals will be in accordance with the approval requirements. The information included herein is believed to be accurate and reliable. However, llegro assumes no responsibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000