Cascaded Noise Shaping for Oversampling A/D and D/A Conversion Bruce A. Wooley Stanford University

Outline Oversampling modulators for A-to-D conversion Cascaded ΣΔ modulators Low-voltage ΣΔ modulator design for MHz-bandwidth signals Cascaded noise shaping for bandpass oversampling D-to-A conversion Bruce A. Wooley - 2 - Stanford University, 2005

Analog-to-Digital Conversion Digital Processor 00001011 11000011 01001000 Filtering Sampling Quantization Processing Quantizer model: e Q [n] p(e Q ) Σ 1/Δ -Δ/2 Δ/2 Bruce A. Wooley - 3 - Stanford University, 2005

Quantization Noise Shaping N B S Q (f) -f S /2 -f B f B f S /2 Quantizer resolution increased by 3 db per octave of OVERSAMPLING S Q (f) N B -f S /2 -f B f B f S /2 Quantizer resolution increased through NOISE SHAPING Bruce A. Wooley - 4 - Stanford University, 2005

Oversampling Modulators Embed quantizer in a feedback loop to achieve larger improvement in resolution with increased oversampling Feedback can be used for PREDICTION (Δ modulation) or NOISE SHAPING (ΣΔ modulation) Noise shaping modulators are more robust and easier to implement than predictive modulators Bruce A. Wooley - 5 - Stanford University, 2005

Sigma-Delta (or Delta-Sigma) Modulation E Q (z) Integrator X(z) Σ z -1 1 z -1 A/D Y(z) D/A Y(z) = z "1 X(z) (1" z "1 )E Q (z) N E (f) = [ 2sin ( "f / f S )] 2 N Q (f) Bruce A. Wooley - 6 - Stanford University, 2005

ΣΔ Modulator Response 0.6 Modulator Input, Quantizer Output 0.4 0.2 0-0.2-0.4-0.6 0 50 100 150 200 250 Time (t/t) Bruce A. Wooley - 7 - Stanford University, 2005

Noise Shaping Ideal Digital Lowpass Filter First-Order Noise Shaping f B f N f S /2 Frequency Bruce A. Wooley - 8 - Stanford University, 2005

Higher-Order Noise-Shaping Modulators The order of the noise shaping can be increased using either or Single quantizer modulators Multi-loop noise differencing Single loop with multi-order filtering Cascaded (multistage) modulators Bruce A. Wooley - 9 - Stanford University, 2005

Noise-Differencing ΣΔ Modulators Y(z) = z 1 X(z) (1 z 1 ) L E(z) Noise Shaping LP Filter L=3 L=2 L=1 f B f N f S /2 Frequency Bruce A. Wooley - 10 - Stanford University, 2005

ΣΔ Modulator Dynamic Range (with 1-bit quantization) 140 120 Dynamic Range (db) 100 80 60 40 L=3 L=2 L=1 20 0 4 8 16 32 64 128 256 512 Oversampling Ratio Bruce A. Wooley - 11 - Stanford University, 2005

Single-Quantizer ΣΔ Modulator E(z) X(z) A(z) Y(z) F(z) Y(z) = H X (z)x(z) H E (z)e(z) where and H X (z) = A(z) 1 A(z)F(z), H E (z) = 1 1 A(z)F(z) A(z) = H X(z) H E (z), F(z) = 1" H E(z) H X (z) Bruce A. Wooley - 12 - Stanford University, 2005

Noise Differencing Modulators Y(z) = z 1 X(z) (1 z 1 ) L E(z) Can implement with a single quantizer and L nested loops Limit cycle instability for L > 2 For L = 2 z "1 A(z) = (1" z "1 ) 2 and F(z) = 2 " z "1 Integrator 1 Integrator 2 Integrator L E X 1 1 z!1 " 1!z!!1 " " " 1!z!1 1!z!1!! Y Bruce A. Wooley - 13 - Stanford University, 2005

2nd-Order Modulator Implementation X! " " z!1 A(z) " z!1 E " Y F(z) "! " z!1! E X! " " z!1! " " z!1 " Y Unity Transfer Function z!1 " "! z!1 Bruce A. Wooley - 14 - Stanford University, 2005

Bruce A. Wooley - 15 - Stanford University, 2005 2nd-Order ΣΔ Modulator X! Y E " " " z!1 " z!1 "! X! Y E " " " z!1 " z!1 "! "!

Bruce A. Wooley - 16 - Stanford University, 2005 2nd-Order ΣΔ Modulator X! Y E " " " z!1 " z!1 " 2! X! Y E " " " z!1 "! 2 1 " z!1 2!

2nd-Order Noise-Differencing ΣΔ Modulator * (with 1-bit quantization) Can scale only w/ 1-bit quantizer x(nt)! 1 2 INTEGRATOR 1! DELAY! 1 2 INTEGRATOR 2! DELAY QUANTIZER 1-bit A/D y(nt) q(nt) D/A * B. Boser, JSSC, Dec.1988 Bruce A. Wooley - 17 - Stanford University, 2005

Cascaded ΣΔ Modulators Quantizer error quantized by subsequent stage and then digitally filtered and subtracted from output of preceding stage Cancellation of lower-order noise-shaping terms depends on matching of analog and digital paths No potential instability if use first- and second-order stages Bruce A. Wooley - 18 - Stanford University, 2005

Cascaded Noise-Shaping Modulator Analog In x!" e y Delay! Digital Out ADC Digital Difference Matches noise shaping of quantization error in first-stage Bruce A. Wooley - 19 - Stanford University, 2005

Maximum Improvement in Dynamic Range 80.0 60.0 Simulation Closed form equation 40.0 20.0 0.0 0.01 Independent of OSR 0.1 1 10 Coefficient Mismatch (%) Bruce A. Wooley - 20 - Stanford University, 2005

Third-Order (2-1) Cascaded Modulator x 2 nd order!" y 1 Error Cancellation y e 1 1 st order!" y 2 Y 1 (z) = z "2 X(z) (1" z "1 ) 2 E 1 (z) Y 2 (z) = z "1 E 1 (z) (1" z "1 )E 2 (z) Y(z) = z "1 Y 1 (z) " (1" z "1 ) 2 Y 2 (z) = z "3 X(z) (1" z "1 ) 3 E 2 (z) Bruce A. Wooley - 21 - Stanford University, 2005

2-1 Cascaded ΣΔ Modulator x $ # $ # y 1 - - b "! $ - $ - # y 2 Bruce A. Wooley - 22 - Stanford University, 2005

Matching Error in 2-1 Cascade 10 Loss in Dynamic Range (db) 8 6 4 2 0 Calculated Simulated -2-10 -5 0 5 10 Matching Error (%) Bruce A. Wooley - 23 - Stanford University, 2005

Spectrum of 2-1 Cascade w/ Mismatch 0 Spectral Power (db) -50-100 -150-200 0 5 10 15 20 25 Frequency (khz) Bruce A. Wooley - 24 - Stanford University, 2005

Matching Error in 1-1-1 Cascade 35 Loss in Dynamic Range (db) 30 25 20 15 10 5 Calculated Simulated 0-2 -1.5-1 -0.5 0 0.5 1 1.5 2 Matching Error (%) Bruce A. Wooley - 25 - Stanford University, 2005

Spectrum of 1-1-1 Cascade w/ Mismatch 0 Spectral Power (db) -50-100 -150-200 0 5 10 15 20 25 Frequency (khz) Bruce A. Wooley - 26 - Stanford University, 2005

Advantages of 2-1 Cascade Low sensitivity to precision of analog circuits Suppression of spurious noise tones resulting for correlation of quantization noise with input Considerable design flexibility No potential instability Bruce A. Wooley - 27 - Stanford University, 2005

Analog Integration in CMOS Continuous Time (tune g m or MOS-R) g m -C MOSFET-C Sampled Data Switched current Switched capacitor Bruce A. Wooley - 28 - Stanford University, 2005

Analog Integration in CMOS Continuous-time (g m -C or MOSFET) Tune g m or MOS resistor Performance limited by timing jitter, waveform asymmetry and integrator linearity Switched-current Limitations: current sources must be cascoded to increase output resistance high supply voltage large V GS V T needed to reduce sensitivity to V T mismatch high power dissipation sensitive to switch parasitics and charge injection noise introduced into compressed signal Switched-capacitor approach preferable for obtaining high resolution at low supply voltage and low power dissipation Bruce A. Wooley - 29 - Stanford University, 2005

Low-Power ΣΔ Modulator Design * C i x 1 2 C s 1 2! H(z) Q y High-resolution converters should by limited by thermal noise kt/c noise in switched-capacitor circuits First stage limit performance and therefore dissipates a large fraction of power Minimize power by minimizing capacitor size in switched-c implementations * S. Rabii, JSSC, June 1997 Bruce A. Wooley - 30 - Stanford University, 2005

ΣΔ Modulator Implementation 1/5 1/6 x 1/5 "!! # 1/3 " # y 1 H 1 (z) 1/20 3/4! "! y 2 # H 2 (z) "! 1/5 y Bruce A. Wooley - 31 - Stanford University, 2005

First Stage of Modulator 1.8V 0V 1.8V 0V S2 S5 S6 0.3V 0.3V 20pF 0.9V S7 Vi() S1 4pF S3 S4! S5 S6 S8! Vi(!)!! S1 4pF S3 S4 S5 S6 S8 0.3V 20pF 0.9V S7 S2 S5 S6 0.3V 1.8V 0V 1.8V 0V S1, S5:!1 delayed, CMOS S3, S7:!1, NMOS S2, S6:!2 delayed, CMOS S4, S8:!2, NMOS Bruce A. Wooley - 32 - Stanford University, 2005

2-Stage Class A/AB Amplifier 1.8 V V cmfb1 M 8 M 13 V bz V bz M 9 M 7 M 10 V out () M z V in () M 1 M 2 V in (!) M z V out (!) C C C C V bias V o1 (!) V o1 () M 11 M 5 M 3 M 4 M 6 M 12 Bruce A. Wooley - 33 - Stanford University, 2005

Die Photo of 1.8-V CMOS ΣΔ Modulator Bruce A. Wooley - 34 - Stanford University, 2005

Measured SNR and SNDR 100 SNR 80 SNDR 60 40 20 0-100 -80-60 -40-20 0 Input Level (db) Bruce A. Wooley - 35 - Stanford University, 2005

Measured Baseband Output Spectrum 0-20 -40!20 db, 2 khz Input -60-80 -100-120 -140-160 0 5 10 15 20 25 Frequency (khz) Bruce A. Wooley - 36 - Stanford University, 2005

Dynamic Range vs. Oversampling Ratio 110 100 90 80 70 60 20 50 100 200 300 Oversampling Ratio Bruce A. Wooley - 37 - Stanford University, 2005

Dynamic Range & Power vs. Supply Voltage 100 4.0 99 3.5 3.0 98 Power Dynamic range 2.5 97 1.5 1.7 1.9 2.1 2.3 2.5 Supply Voltage (V) 2.0 Bruce A. Wooley - 38 - Stanford University, 2005

1.8-V CMOS ΣΔ Modulator Performance Dynamic range Peak SNR Peak SNDR Bandwidth Oversampling ratio Power dissipation Active area Technology Threshold voltages 99 db 99 db 95 db 25 khz 80 2.5 mw 1.5 mm 2 0.8-µm CMOS 0.65 V, 0.75 V Bruce A. Wooley - 39 - Stanford University, 2005

Power Efficiency Figure of Merit Power efficiency as a Figure of Merit: FoM = DynamicRange " Bandwidth Power = 22N " BW Power (MHz / mw) where Dynamic Range is a POWER, not voltage, ratio N = effective # of bits of resolution For circuits in which the dynamic range is limited by thermal noise and the bandwidth is not limited by technology: Quadratic dependence on voltage dynamic range Linear dependence on bandwidth Bruce A. Wooley - 40 - Stanford University, 2005

ADC Power Efficiency Bruce A. Wooley - 41 - Stanford University, 2005

Low-Voltage Broadband ΣΔ Modulation * Target objective is low-voltage, high-resolution broadband A/D conversion for applications such as ADSL, CDMA 2000, IS-95, and GSM Objectives Conversion rate 2.5 MSample/s Dynamic range 92 db (15 bits) Power supply 1.2V Power dissipation ~ 80 mw Technology 0.25-µm CMOS * K. Nam, 2004 CICC Bruce A. Wooley - 42 - Stanford University, 2005

Analog Challenges @ Low V DD Reduced voltage headroom Limited choice of op amp topologies Dynamic range decreases unless noise floor is reduced Low-voltage analog high power In this work consider architecture and circuits needed to achieve low voltage and low power Bruce A. Wooley - 43 - Stanford University, 2005

Low-Voltage, Low-Power Strategies Low oversampling ratio & high-order modulator Maximize the full-scale input amplitude for a given V DD Multi-bit quantization Single-stage op amps Linear integrator settling allows use of slower op amps Bruce A. Wooley - 44 - Stanford University, 2005

Architectural Decisions Single-bit or multi-bit quantization multi-bit single-bit feedback causes op amp slew need fast op amp single-bit quantization results in larger quantization noise leakage into the output in cascaded modulators Single-quantizer or cascade cascade Even with multi-bit quantization op amp slewing can limit performance of a high-order single-quantizer modulator use 2nd-order modulator for first stage 2-2 cascade with 5-bit and 3-bit quantizers Bruce A. Wooley - 45 - Stanford University, 2005

Conventional First-Order ΣΔ Modulator X U 1 V 1 Y 1 z -1 N-bit z -1 DAC Y = z 1 X (1 z 1 )E U 1 = (1 z 1 )X (1 z 1 )E magnitude depends on input amplitude and frequency V 1 = z 1 X z 1 E magnitude depends on input Op amps designed to ensure minimum SNDR degradation for large signals inefficient power allocation Bruce A. Wooley - 46 - Stanford University, 2005

Reduced Integrator Swing-Range ΣΔ Modulator X U 1 V 1 W 1 Y 1 z -1 N-bit z -1 Y = X (1 z 1 )E DAC U 1 = (1 z 1 )E U 1 LSB V 1 = z 1 E V 1 0.5 LSB U 1 & V 1 are DECOUPLED from the input X attractive at low V DD W 1 = X z 1 E swing-range burden is moved to W 1 Approach can be extended to higher-order modulators Bruce A. Wooley - 47 - Stanford University, 2005

Second-Order RISR ΣΔ Modulator X U z -1 z -1 1 V 1 V 2 W 1 1 z -1 Y 1 z -1 N-bit 2 Y = X (1 z 1 ) 2 E DAC U 1 = (1 z 1 ) 2 E U 1 2 LSB V 1 = z 1 (1 z 1 )E V 1 LSB V 2 = z 2 E V 2 0.5 LSB W 1 = X z 1 (z 1 2)E * J. Silva, Elec Letters, June 2001 Bruce A. Wooley - 48 - Stanford University, 2005

Trade-Offs in RISR ΣΔ Modulators 1.00 0.75 0.50 0.25 0.00 1.00 0.75 0.50 L=1 L=2 L=3 L=4 U 1 = (1 z 1 ) L E L = 2 & N = 5 for first stage For V REF = 1.2V, X FS = 1.1V U 1 max = 150mV V 1 max = 75mV V 2 max = 37.5mV 0.25 0.00 1 2 3 4 5 6 Number of quantizer bits # X FS = 2N " (2 L " 1) & % $ 2 N ( V REF " 1 ' Bruce A. Wooley - 49 - Stanford University, 2005

Implementation Issues Integrator op amp: requirements are greatly relaxed small input signal range linear settling dominates slow op amp can be used power saving relaxed dc gain requirement small output range Quantizer: more stringent requirements multiple signals summed at quantizer input offset increases swing ranges need offset cancellation very fast regeneration needed since latch must be strobed after sampling of the input is complete Bruce A. Wooley - 50 - Stanford University, 2005

Experimental Prototype X U z -1 z -1 1 V 1 V 2 Y 1 1 z -1 1 z -1 5-bit 2 DWA-DAC Y out V 2 z -1 z -1 z -1 1 z -1 1 3-bit Y 2 2 DAC Bruce A. Wooley - 51 - Stanford University, 2005

First-Stage Implementation * DWA-DAC RefP RefN X S4P j S4N j S1 j C S1j j=1,...,32 S2 S3 C I1 S5 C S2 S8 S6 S7 C I2 5-bit Y 1! 1,! 1d! 2,! 2d S1 j, S3, S5, S7 S4P j or S4N j, S2, S6, S8 * actual implementation is fully differential Bruce A. Wooley - 52 - Stanford University, 2005

Low Distortion Input Sampling *! 1 V DD V DD V DD M4 M2 C boost M5 M3 M1 X! 1 M Sj C S1j j=1,...,32 * M. Dessouky, JSSC, March 2001 Bruce A. Wooley - 53 - Stanford University, 2005

First Op Amp V DD V DD V DD V B1 2.4 ma 2.4 ma V B2 V in1 M1 M2 V in2 V out1 V out2 0.4 V 9.8 ma 9.8 ma V B3 Dc gain 57dB g m1 96mS CMFB Power 29mW BW CL 122MHz V CM (in) 0.15mV V CM (out) 0.65V Bruce A. Wooley - 54 - Stanford University, 2005

Quantizer Comparator (1 of 32) X! 1 C q! 1d V Ri! 2d! 2! 2d V 1! 1 C q! 1d V os! latch -V 1 V 2! 2d! 1 C q! 2! 1d C P A 1 A 2 CM! 2d! 2! 1,! 1d! 2,! 2d! latch Bruce A. Wooley - 55 - Stanford University, 2005

Prototype Die Photo Intg4 Quant2 Intg3 Intg2 Quant1 Intg1 DWA & Logic CLK Bruce A. Wooley - 56 - Stanford University, 2005

Measured SNR and SNDR 100.0 80.0 60.0 f in =366KHz SNR SNDR 40.0 20.0 0.0-100.0-80.0-60.0-40.0-20.0 0.0 Input Level (db) Bruce A. Wooley - 57 - Stanford University, 2005

Measured Output Spectrum 0 4-dB, 109-kHz Input -50 SFDR = 97dB -100-150 0.00 0.25 0.50 0.75 1.00 1.25 Frequency (MHz) Bruce A. Wooley - 58 - Stanford University, 2005

Performance Summary Analog Supply Voltage Sampling Rate Signal Bandwidth Dynamic Range Peak SNDR @ 366-kHz input Analog Power Digital Power Active Area Technology 1.2 V 40 MHz 1.25 MHz 96 db 89 db 44 mw 43 mw * 8.6 mm 2 0.25-µm CMOS * Estimate 10 mw digital power in 0.13-µm CMOS Bruce A. Wooley - 59 - Stanford University, 2005

Bandpass Oversampling D/A Conversion * Consider the use of cascaded noise shaping for bandpass D/A conversion in RF transmitters Move IF into the digital domain to eliminate dc offset I & Q mismatch Merge D/A conversion, noise shaping, reconstruction and mixing to IF Explore the use of cascaded noise shaping with semidigital filtering * D. Barkin, 2003 VLSI Ckts Symp Bruce A. Wooley - 60 - Stanford University, 2005

Traditional Wireless Transmitter Architecture cos!t I M FIR/ROM DAC LPF Out Q M FIR/ROM DAC LPF sin!t Digital Analog Bruce A. Wooley - 61 - Stanford University, 2005

Bandpass Oversampling DAC cos(!t) = [ 1, 0, -1, 0,... ] I M Noise Shaping DAC Filtering Analog IF Output Q M Noise Shaping Digital Analog sin(!t) = [ 0, 1, 0, -1,... ] Mix to IF (at f S /4) following cascaded noise shaping Error cancellation performed at IF Bruce A. Wooley - 62 - Stanford University, 2005

Lowpass Cascaded Noise Shaping Digital Input 2 nd Order!" Modulator 1 Signal Stage 1 Error 3 rd Order!" Modulator Noise Estimate 4 (1 - z -1 ) 2 2nd-order differentiator matches noise shaping in first stage Bruce A. Wooley - 63 - Stanford University, 2005

Bandpass DAC Architecture I Cascaded "# Modulator 1 4 (1 - z -1 ) 2-1,1! 1! 1 DAC Filtering Q Cascaded "# Modulator 1 4 (1 - z -1 ) 2 1,-1! 2! 2 f s /2 f s I and Q modulators operate at f S /2, saving power Bruce A. Wooley - 64 - Stanford University, 2005

Discrete Time - Continuous Time Interface Signal 1-1,1 Semi-Digital Filter Noise Estimate -1,1 Digital (1 - z -1 ) Filter 2 4 11 6 1 2 64 Digital Analog Semi-digital filtering for reconstruction of signal Good for 1-bit signal path, but not multi-bit noise estimation path Digital filter reduces out-of-band quantization noise Digital filter transfer function matches that of semi-digital filter Bruce A. Wooley - 65 - Stanford University, 2005

Semi-Digital Filter * Digital Input 1 z -1 z -1 z -1 a 1 a 2 a N Analog Output Mismatch among current sources alters the transfer function but doesn t introduce nonlinearity Area limits number of taps and precision of coefficients Good for 1-bit signal path but not multi-bit noise estimation path * D. Su, JSSC, Dec. 1993 Bruce A. Wooley - 66 - Stanford University, 2005

Bandpass Data Weighted Averaging * 1 Semi-Digital Filter -1,1-1,1 Digital (1 - z -1 ) 2 4 Filter 11 6 BP DWA Pointer Calc 1 2 64 f s /2 Notch f s /4 Notch I & Q pointer calculations are independent 7 5 3 8 2 I 7 5 3 8 2 Q 6 4 2 6 3 Time --> * T. Shui, et al., ISCAS, 1998 Bruce A. Wooley - 67 - Stanford University, 2005

Bandpass DAC Die Photo Noise Shapers Digital Filters Current Source Array Bias Bruce A. Wooley - 68 - Stanford University, 2005

DAC Output Spectrum Power Spectral Density (db) 0-50 2-3 (4 bit) Digital Noise Shaper Output Measured DAC Output 46 db -100 0 20 40 60 80 100 Frequency (MHz) Bruce A. Wooley - 69 - Stanford University, 2005

SNR and SNDR 100 SFDR & SNDR (db) 80 60 40 20 0 Measured SFDR Measured SNDR -20-100 - 80-60 - 40-20 0 Signal Power (db) Bruce A. Wooley - 70 - Stanford University, 2005

Bandpass DAC Performance Technology Center frequency Bandwidth Peak SNDR Dynamic range Minimum out-of-band suppression Mirror for 6 db Input Active area Power (except for current sources) 0.25-µm CMOS 50 MHz 6.25 MHz 76 db 85 db 80 db 90 db 2.1 mm 2 100 mw Bruce A. Wooley - 71 - Stanford University, 2005

Summary Cascades of first- and second-order noise-shaping modulator stages can be used for A/D and D/A conversion lowpass and bandpass data conversion If properly designed, advantages include no potential instability decorrelation of quantization noise and input low sensitivity to analog precision Still room for architectural and circuit innovation to meet the challenges presented by technology scaling to sub-100nm dimensions performance demands of new applications Bruce A. Wooley - 72 - Stanford University, 2005

References I OVERSAMPLING A-to-D CONVERSION 1. B. E. Boser and B. A. Wooley, The Design of Sigma-Delta Modulation Analog-to- Digital Converters, IEEE J. Solid-State Circuits, vol. 23, pp. 1298-1308, Dec.1988. 2. W. R. Bennett, Spectra of Quantized Signals, Bell Sys. Tech. Journal, vol. 27, pp. 446-472, July 1948. 3. F. de Jager, Delta Modulation, a Method of PCM Transmission Using the 1-Unit Code, Philips Res. Report, vol. 7, pp. 442-446. 4. C. Cutler, Transmission Systems Employing Quantization, U.S. Patent No. 2,927,962, Mar. 8, 1960. 5. H. Inose and Y. Yasuda, A Unity Bit coding Method by Negative Feedback, Proc. IEEE, vol. 51, pp. 1524-1533, Nov. 1963. 6. J. C. Candy, A Use of Limit Oscillations to Obtain Robust Analog-to-Digital Converters, IEEE Trans. Commun., vol. COM-22, pp. 296-305, Mar. 1974. 7. S. K. Tewksbury and R. W. Hallock, Oversampled, Linear Predictive and Noise- Shaping Coders of Order N>1, IEEE Trans. Circuits and Sys., vol. CAS-25, pp. 436-447, July 1978. 8. R. M. Gray, Spectral Analysis of Quantization Noise in a Single-Loop Sigma-Delta Modulator with DC Input, IEEE Trans. Commun., vol. 37, pp. 956-958, Sept. 1989. Bruce A. Wooley - 73 - Stanford University, 2005

References II 9. J. C. Candy, A Use of Double Integration in Sigma Delta Modulation, IEEE Trans. Commun., vol. COM-33, pp. 249-258, Mar. 1985. 10. B. P. Brandt, D. E. Wingard, and B. A. Wooley, Second-Order Sigma-Delta Modulation for Digital-Audio Signal Acquisition, IEEE J. Solid-State Circuits, vol. 26, pp. 618-627, Apr. 1991. 11. J. C. Candy and G. C. Temes, Oversampling Delta-Sigma Converters, IEEE Press, 1992. 12. S. R. Norsworthy, R. Schreier, G. C. Temes, Delta-Sigma Data Converters: Theory, Design and Simulation, IEEE Press, 1997. CASCADED ΣΔ MODULATION 9. L. Longo and M. Copeland, A 13 bit ISDN-band Oversampled ADC using Two- Stage Third Order Noise Shaping, IEEE Proc. Custom IC Conf., pp. 21.2.1-21.2.4, Jan. 1988. 10. Y. Matsuya, et al., A 16-bit Oversampling A-to-D Conversion Technology Using Triple Integration Noise Shaping, IEEE J. Solid-State Circuits, vol. SC-22, pp. 921-929, Dec. 1987. 11. L. A. Williams III and B. A. Wooley, Third-Order Cascaded Sigma-Delta Modulators, IEEE Trans. Circuits and Sys., vol. 38, pp. 489-498, May 1991. Bruce A. Wooley - 74 - Stanford University, 2005

References III 16. L. A. Williams III and B. A. Wooley, A Third Order Sigma-Delta Modulator with Extended Dynamic Range, IEEE J. Solid-State Circuits, vol. 29, pp. 193-202, Mar. 1994. 17. B. P. Brandt and B. A. Wooley, A 50-MHz Multibit Sigma-Delta Modulator for 12-b 2- MHz A/D Conversion, IEEE J. Solid-State Circuits, vol. 26, pp. 1746-1756, Dec. 1991. 18. S. Rabii and B. A. Wooley, A 1.8-V Digital-Audio Sigma-Delta Modulator in 0.8-µm CMOS, IEEE J. Solid-State Circuits, vol. 32, pp. 783-796, June 1997. 19. S. Rabii and B. A. Wooley, The Design of Low-Voltage, Low-Power Sigma-Delta Modulators, Kluwer Academic Publishers, 187 pp., 1999. 20. T. B. Cho and P. R. Gray, A 10-b, 20 Msample/s Pipelined CMOS ADC, IEEE J. Solid-State Circuits, vol. 30, pp. 166-172, Mar. 1995. 21. K. Vleugels, S. Rabii, and B. A. Wooley, A 2.5-V Sigma-Delta Modulator for Broadband Communications Applications, IEEE J. Solid-State Circuits, vol. 36, pp. 1887-1899, Dec. 2001. 22. A. Tabatabaei and B. A. Wooley, A Two-Path Bandpass Sigma-Delta Modulator with Extended Noise Shaping, IEEE J. Solid-State Circuits, vol. 35, pp. 1799-1809, Dec. 2000. 23. A. K. Ong and B. A. Wooley A Two-Path Bandpass ΣΔ Modulator for Digital IF Extraction at 20 MHz, IEEE J. Solid-State Circuits, vol. 32, pp. 1920-1934, Dec. 1997 Bruce A. Wooley - 75 - Stanford University, 2005

References IV DECIMATION & INTERPOLATION FILTERS 24. B. P. Brandt and B. A. Wooley, A Low-Power, Area-Efficient Digital Filter for Decimation and Interpolation, IEEE J. Solid-State Circuits, vol. 29, pp. 679-687, June 1994. 25. R. E. Crochiere and L. R. Rabiner, Interpolation and Decimation of Digital Signals A Tutorial Review, Proc. IEEE, vol. 69, pp. 300-331, Mar. 1981. OVERSAMPLING D-to-A CONVERSION 26. D. K. Su and B. A. Wooley, A CMOS Oversampling D/A Converter with a Current- Mode Semi-Digital Reconstruction Filter, IEEE J. Solid-State Circuits, vol. 28, pp. 1224-1233, Dec. 1993. 27. K. Falakshahi, C.-K. K. Yang and B. A. Wooley, A 14-bit 10-Msamples/s D/A Converter Using Σ-Δ Modulation, IEEE J. Solid-State Circuits, vol. 34, pp. 607-615, May 1999. 28. D. B. Barkin, A. C. Y. Lin, D. K. Su, and B. A. Wooley, A CMOS Oversampling Bandpass Cascaded D/A Converter with Digital FIR and Current-Mode Semi- Digital Filtering, IEEE J. Solid-State Circuits, vol. 39, pp. 585-593, Apr. 2004. Bruce A. Wooley - 76 - Stanford University, 2005