P54FCT240/74fct240 INVERTING OCTAL BUFFER/LINE DRIVER WITH 3-STATE OUTPUTS FEATURES Function, Pinout and Drive Compatible with the FCT and F Logic FCT-A speed at 5.1ns max (MIL) Output levels compatible with TTL and CMOS Edge-rate control circuitry for significantly improved noise characteristics ESD protection exceeds 2000V Power-off disable feature Matched rise and fall times Fully compatible with TTL input and output logic levels 48 ma sink current, 12 ma source current (MIL) DESCRIPTION The P54/74FCT240 is an inverting octal buffer and line driver designed to be employed as memory address drivers, clock drivers and bus-oriented transmitters/receivers. The device provides speed and drive capabilities equivalent to the fastest bipolar logic counterparts while reducing power dissipation by using advanced CMOS technoloy. The input and output voltage levels allow direct interface with TTL, NMOS and CMOS devices without external components. Functional Block Diagram Pin ConfigurationS DIP (D2) LCC (L2) Updated March 2016
Maximum Ratings (1,2) Sym Parameter Value Unit T STG Storage Temperature -65 to +150 C T A Ambient Temperature Under Bias -65 to +135 C Potentional to Ground -0.5 to +7.0 V P T Power Dissipation 0.5 W I OUTPUT Current Applied to Output 120 ma Input Voltage -0.5 to +7.0 V V OUT Voltage Applied to Output -0.5 to +7.0 V RECOMMENDED OPERATING CONDITIONS Grade Ambient Temp GND Military -55 C to +125 C 0V 5.0V ± 10% Industrial -40 C to +85 C 0V 5.0V ± 5% CAPACITANCES ( = 5.0V, T A = 25 C, f = 1.0MHz) Sym Parameter Conditions Typ Unit C IN Input Capacitance = 0V 6 pf C OUT Output Capacitance V OUT = 0V 8 pf DC ELECTRICAL CHARACTERISTICS (Over Recommended Operating Temperature & Supply Voltage) Sym Parameter Test Conditions Min Max Unit V OH V OL High Level Output Voltage Low Level Output Voltage (Min) V IH = 2.0 V, V IL = 0.8 V (Min) V IH = 2.0 V, V IL = 0.8 V I OH = -300 µa 4.3 I OH = -12 ma 2.4 I OL = 300 µa 0.2 I OL = 32 ma 0.5 V IK Input Clamp Voltage (Min), I IN = -18mA -1.2 V I IH High Level Input Current, 5.0 µa I IL Low Level Input Current, -5.0 µa I OZH High Impedence Output Current, 10 I OZL, -10 I OS Short Circuit Output Current -60 ma V V µa I CCQ Quiescent Power Supply Current (CMOS inputs) 0.2 V or - 0.2 V f i = 0 MHz 1.5 ma I CC Quiescent Power Supply Current (TTL inputs) = 3.4 V 2.0 ma I CCD Dynamic Power Supply Current Outputs open One bit toggling 50% duty cycle - 0.2 V or 0.2 V = OE B 0.25 ma/ MHz Notes: 1. Operation beyond the limits set forth in the above table may impair the useful life of the device. Unless otherwise noted, these limits are over the operating free-air temperature range. 2. Unused inputs must always be connected to an appropriate logic voltage level, preferably either or ground. 3. Per TTL driven input ( =3.4V); all other inputs at or GND. Page 2
DC ELECTRICAL CHARACTERISTICS (Over Recommended Operating Temperature & Supply Voltage) P54FCT240 / P74FCT240 - OCTAL BUFFER/LINE DRIVER WITH 3-STATE OUTPUTS Sym Parameter Test Conditions Min Max Unit I CCT Total Power Supply Current Outputs open, = OE B 50% duty cycle f i = 10 MHz One bit toggling f i = 2.5 MHz Eight bits toggling - 0.2 V or 0.2 V = 3.4 V or - 0.2 V or 0.2 V = 3.4 V or 4.0 ma 4.8 ma 6 ma 14 ma C IN Input Capacitance T C = +25 C,, F = 1 MHz 10 pf C OUT Output Capacitance T C = +25 C,, F = 1 MHz 12 pf AC CHARACTERISTICS (Over Recommended Operating Temperature & Supply Voltage) Sym Parameter Condition 54/74FCT240 54/74FCT240A Ind Mil Ind Mil Min Max Min Max Min Max Min Max Unit t PLH t PHL Propagation Delay D X to O X 1.5 8.0 1.5 9.0 1.5 4.8 1.5 5.1 ns t PZH C L = 50pF Output Enable Time 1.5 8.0 1.5 10.5 1.5 6.2 1.5 6.5 ns t PZL R L = 500Ω t PHZ t PLZ Output Disable Time 1.5 11.0 1.5 12.5 1.5 5.6 1.5 5.9 ns Test Open Drain Disable Low Enable Low All Other Tests Switch Closed Open Page 3
ENABLE/DISABLE TIMES PROPAGATION DELAY PIN DESCRIPTION FUNCTION TABLE Pin Names Description Inputs Outputs, OE B Dxx Oxx Output Enable Inputs (Active LOW) Inputs Outputs OE B D O XX L L L H L L H L H H X Z H = High Voltage Level X = Don't Care L = Low Voltage Level Z = High Impedance ORDERING INFORMATION Page 4
Pkg # D2 # Pins 20 (300 mil) Symbol Min Max A - 0.200 b 0.014 0.026 b2 0.045 0.065 c 0.008 0.018 D - 1.060 E 0.220 0.310 ea e 0.300 BSC 0.100 BSC L 0.125 0.200 Q 0.015 0.070 S1 0.005 - S2 0.005 - α 0 15 SIDEBRAZED DUAL INLINE PACKAGE Pkg # L2 # Pins 20 Symbol Min Max A 0.060 0.075 A1 0.050 0.065 B1 0.022 0.028 D/E 0.342 0.358 D1/E1 0.200 BSC D2/E2 0.100 BSC D3/E3-0.358 e 0.050 BSC h 0.040 REF j 0.020 REF L 0.045 0.055 L1 0.045 0.055 L2 0.075 0.095 ND 5 NE 5 SQUARE LEADLESS CHIP CARRIER Page 5
REVISIONS DOCUMENT NUMBER DOCUMENT TITLE LOGIC103 P54FCT240 - OCTAL BUFFER/LINE DRIVER WITH 3-STATE OUTPUTS REV ISSUE DATE ORIGINATOR DESCRIPTION OF CHANGE OR Dec 2015 JDB New Data Sheet 01 Feb 2016 JDB Updated DC Electrical Characteristics 02 Mar 2016 JDB DC Electrical Characteristics 03 Mar 2016 JDB DC Electrical Characteristics Page 6