PD 97378A HEXFET Power MOSFET Applications l High Efficiency Synchronous Rectification in SMPS l Uninterruptible Power Supply l High Speed Power Switching l Hard Switched and High Frequency Circuits Benefits l Improved Gate, Avalanche and Dynamic dv/dt Ruggedness l Fully Characterized Capacitance and Avalanche SOA l Enhanced body diode dv/dt and di/dt Capability l LeadFree G D S V DSS R DS(on) typ. max. I D (Silicon Limited) I D (Package Limited) D 40V 0.90mΩ.25mΩ 400Ac 240A G S S D 2 Pak 7 Pin S SS G D S Gate Drain Source Absolute Maximum Ratings Symbol Parameter Max. Units I D @ T C = 25 C Continuous Drain Current, V GS @ V (Silicon Limited) 400c I D @ T C = C Continuous Drain Current, V GS @ V (Silicon Limited) 280c I D @ T C = 25 C Continuous Drain Current, V GS @ V (Wire Bond Limited) 240 A I DM Pulsed Drain Current d 6 P D @T C = 25 C Maximum Power Dissipation 380 W Linear Derating Factor 2.5 W/ C V GS GatetoSource Voltage ± 20 V dv/dt Peak Diode Recovery f 2.0 V/ns T J Operating Junction and 55 to 75 T STG Storage Temperature Range Soldering Temperature, for seconds (.6mm from case) 300 C Avalanche Characteristics E AS (Thermally limited) Single Pulse Avalanche Energy e 290 mj I AR Avalanche Currentd See Fig. 4, 5, 22a, 22b A E AR Repetitive Avalanche Energy d mj Thermal Resistance Symbol Parameter Typ. Max. Units R θjc JunctiontoCase kl 0.40 C/W R θja JunctiontoAmbient (PCB Mount) j 40 www.irf.com 04/22/20
Static @ (unless otherwise specified) Symbol Parameter Min. Typ. Max. Units V (BR)DSS DraintoSource Breakdown Voltage 40 V V (BR)DSS / T J Breakdown Voltage Temp. Coefficient 0.038 V/ C R DS(on) Static DraintoSource OnResistance 0.90.25 mω V GS(th) Gate Threshold Voltage 2.0 4.0 V I DSS DraintoSource Leakage Current 20 µa 250 I GSS GatetoSource Forward Leakage na GatetoSource Reverse Leakage R G Internal Gate Resistance 2.0 Ω Dynamic @ (unless otherwise specified) Symbol Parameter Min. Typ. Max. Units gfs Forward Transconductance 300 S Q g Total Gate Charge 60 240 nc Q gs GatetoSource Charge 42 Q gd GatetoDrain ("Miller") Charge 65 Q sync Total Gate Charge Sync. (Q g Q gd ) 95 t d(on) TurnOn Delay Time 23 ns t r Rise Time 240 t d(off) TurnOff Delay Time 9 t f Fall Time 60 C iss Input Capacitance 930 pf C oss Output Capacitance 2020 C rss Reverse Transfer Capacitance 990 C oss eff. (ER) Effective Output Capacitance (Energy Related) i 2590 C oss eff. (TR) Effective Output Capacitance (Time Related)h 2650 Diode Characteristics Symbol Parameter Min. Typ. Max. Units I S Continuous Source Current 400c A Conditions V GS = 0V, I D = 250µA Reference to 25 C, I D = 5mAd V GS = V, I D = 95A g V DS = V GS, I D = 250µA V DS = 40V, V GS = 0V V DS = 40V, V GS = 0V, T J = 25 C V GS = 20V V GS = 20V Conditions V DS = V, I D = 95A I D = 80A V DS =20V V GS = V g I D = 80A, V DS =0V, V GS = V V DD = 26V I D = 240A R G = 2.7Ω V GS = V g V GS = 0V V DS = 25V ƒ =.0 MHz, See Fig. 5 V GS = 0V, V DS = 0V to 32V i, See Fig. V GS = 0V, V DS = 0V to 32V h Conditions MOSFET symbol (Body Diode) showing the I SM Pulsed Source Current 6 A integral reverse G (Body Diode)d pn junction diode. V SD Diode Forward Voltage.3 V, I S = 95A, V GS = 0V g t rr Reverse Recovery Time 49 ns V R = 34V, 5 T J = 25 C I F = 240A Q rr Reverse Recovery Charge 37 nc di/dt = A/µs g 4 T J = 25 C I RRM Reverse Recovery Current 3.2 A t on Forward TurnOn Time Intrinsic turnon time is negligible (turnon is dominated by LSLD) D S Notes: Calculated continuous current based on maximum allowable junction temperature. Bond wire current limit is 240A. Note that current limitations arising from heating of the device leads may occur with some lead mounting arrangements. (Refer to AN40) Repetitive rating; pulse width limited by max. junction temperature. ƒ Limited by T Jmax, starting, L = 0.0mH R G = 25Ω, I AS = 240A, V GS =V. Part not recommended for use above this value. I SD 240A, di/dt 740A/µs, V DD V (BR)DSS, T J 75 C. Pulse width 400µs; duty cycle 2%. C oss eff. (TR) is a fixed capacitance that gives the same charging time as C oss while V DS is rising from 0 to 80% V DSS. C oss eff. (ER) is a fixed capacitance that gives the same energy as C oss while V DS is rising from 0 to 80% V DSS. ˆ When mounted on " square PCB (FR4 or G Material). For recom mended footprint and soldering techniques refer to application note #AN994. R θ is measured at T J approximately 90 C. Š R θjc value shown is at time zero. 2 www.irf.com
C, Capacitance (pf) V GS, GatetoSource Voltage (V) I D, DraintoSource Current (A) R DS(on), DraintoSource On Resistance (Normalized) I D, DraintoSource Current (A) I D, DraintoSource Current (A) 0 VGS TOP 5V V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V 0 VGS TOP 5V V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V 4.5V 60µs PULSE WIDTH Tj = 25 C 0. 0. 0 V DS, DraintoSource Voltage (V) 4.5V 60µs PULSE WIDTH Tj = 75 C 0. 0 V DS, DraintoSource Voltage (V) Fig. Typical Output Characteristics Fig 2. Typical Output Characteristics 0 2.0 I D = 95A V GS = V T J = 75 C.5.0 V DS = 25V 60µs PULSE WIDTH 0. 3 4 5 6 7 8 V GS, GatetoSource Voltage (V) Fig 3. Typical Transfer Characteristics 0.5 60 40 20 0 20 40 60 80 20406080 T J, Junction Temperature ( C) Fig 4. Normalized OnResistance vs. Temperature 000 00 V GS = 0V, f = MHZ C iss = C gs C gd, C ds SHORTED C rss = C gd C oss = C ds C gd C iss C oss 4.0 2.0.0 8.0 I D = 80A V DS = 32V V DS = 20V C rss 6.0 0 4.0 2.0 0.0 0 50 50 200 250 V DS, DraintoSource Voltage (V) Q G, Total Gate Charge (nc) Fig 5. Typical Capacitance vs. DraintoSource Voltage Fig 6. Typical Gate Charge vs. GatetoSource Voltage www.irf.com 3
Energy (µj) E AS, Single Pulse Avalanche Energy (mj) V (BR)DSS, I D, Drain Current (A) DraintoSource Breakdown Voltage (V) I SD, Reverse Drain Current (A) I D, DraintoSource Current (A) 0 T J = 75 C 00 0 OPERATION IN THIS AREA LIMITED BY R DS (on) µsec msec V GS = 0V 0. 0.0 0.5.0.5 2.0 Tc = 25 C Tj = 75 C Single Pulse 0 DC msec 420 360 V SD, SourcetoDrain Voltage (V) Fig 7. Typical SourceDrain Diode Forward Voltage Limited By Package 50 48 Fig 8. Maximum Safe Operating Area Id = 5mA V DS, DraintoSource Voltage (V) 300 240 46 80 44 20 60 42 3.5 3.0 2.5 2.0.5.0 0.5 0 25 50 75 25 50 75 T C, Case Temperature ( C) Fig 9. Maximum Drain Current vs. Case Temperature 40 60 40 20 0 20 40 60 80 20406080 T J, Temperature ( C ) 200 0 800 600 400 200 Fig. DraintoSource Breakdown Voltage I D TOP 44A 80A BOTTOM 240A 0.0 0 5 0 5 5 20 25 30 35 40 45 25 50 75 25 50 75 V Starting T J, Junction Temperature ( C) DS, DraintoSource Voltage (V) Fig. Typical C OSS Stored Energy Fig 2. Maximum Avalanche Energy vs. DrainCurrent 4 www.irf.com
E AR, Avalanche Energy (mj) Avalanche Current (A) Thermal Response ( Z thjc ) C/W 0. 0.0 D = 0.50 0.20 0. 0.05 0.02 0.0 SINGLE PULSE ( THERMAL RESPONSE ) R R R 2 R 2 R 3 R 3 τ J τ J τ τ τ 2 τ 2 τ 3 τ 3 Ci= τi/ri Ci i Ri R 4 Ri ( C/W) τi (sec) R 4 0.00757 0.000006 Notes:. Duty Factor D = t/t2 2. Peak Tj = P dm x Zthjc Tc 0.00 E006 E005 0.000 0.00 0.0 0. t, Rectangular Pulse Duration (sec) 0 Fig 3. Maximum Effective Transient Thermal Impedance, JunctiontoCase τ 4 τ 4 τ C τ 0.06508 0.000064 0.833 0.005 0.4378 0.009800 Duty Cycle = Single Pulse 0.0 Allowed avalanche Current vs avalanche pulsewidth, tav, assuming Tj = 50 C and Tstart =25 C (Single Pulse) 0.05 0. 320 280 240 200 60 20 80 40 Allowed avalanche Current vs avalanche pulsewidth, tav, assuming Τ j = 25 C and Tstart = 50 C..0E06.0E05.0E04.0E03.0E02.0E0 tav (sec) TOP Single Pulse BOTTOM.0% Duty Cycle I D = 240A 0 25 50 75 25 50 75 Starting T J, Junction Temperature ( C) Fig 5. Maximum Avalanche Energy vs. Temperature Fig 4. Typical Avalanche Current vs.pulsewidth Notes on Repetitive Avalanche Curves, Figures 4, 5: (For further info, see AN5 at www.irf.com). Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of T jmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long ast jmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 6a, 6b. 4. P D (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (.3 factor accounts for voltage increase during avalanche). 6. I av = Allowable avalanche current. 7. T = Allowable rise in junction temperature, not to exceed T jmax (assumed as 25 C in Figure 4, 5). t av = Average time in avalanche. D = Duty cycle in avalanche = t av f Z thjc (D, t av ) = Transient thermal resistance, see Figures 3) P D (ave) = /2 (.3 BV I av ) = DT/ Z thjc I av = 2DT/ [.3 BV Z th ] E AS (AR) = P D (ave) t av www.irf.com 5
Q RR (nc) I RRM (A) Q RR (nc) V GS(th), Gate threshold Voltage (V) I RRM (A) 4.5 4.0 9 I F = 96A V R = 34V 3.5 3.0 2.5 2.0 I D = 250µA I D =.0mA I D =.0A 8 7 6 5 4 T J = 25 C.5 3.0 75 50 25 0 25 50 75 25 50 75 200 T J, Temperature ( C ) Fig 6. Threshold Voltage vs. Temperature 2 200 300 400 500 di F /dt (A/µs) Fig. 7 Typical Recovery Current vs. di f /dt 2 9 8 I F = 44A V R = 34V T J = 25 C 40 20 I F = 96A V R = 34V T J = 25 C 7 80 6 5 60 4 3 40 2 200 300 400 500 di F /dt (A/µs) Fig. 8 Typical Recovery Current vs. di f /dt 20 200 300 400 500 di F /dt (A/µs) Fig. 9 Typical Stored Charge vs. di f /dt 80 60 40 20 I F = 44A V R = 34V T J = 25 C 80 60 40 20 200 300 400 500 di F /dt (A/µs) Fig. 20 Typical Stored Charge vs. di f /dt 6 www.irf.com
D.U.T ƒ Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer Reverse Recovery Current Driver Gate Drive Period P.W. D.U.T. I SD Waveform Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt D = P.W. Period V GS =V V DD * R G dv/dt controlled by RG Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. Device Under Test V DD ReApplied Voltage Body Diode Inductor Curent Current Forward Drop Ripple 5% I SD * V GS = 5V for Logic Level Devices Fig 2. Peak Diode Recovery dv/dt Test Circuit for NChannel HEXFET Power MOSFETs 5V tp V (BR)DSS V DS L DRIVER R G 20V V GS tp D.U.T IAS 0.0Ω V DD A I AS Fig 22a. Unclamped Inductive Test Circuit Fig 22b. Unclamped Inductive Waveforms V DS R D V DS V GS D.U.T. 90% R G V DD VV GS Pulse Width µs Duty Factor 0. % % V GS t d(on) t r t d(off) t f Fig 23a. Switching Time Test Circuit Fig 23b. Switching Time Waveforms Current Regulator Same Type as D.U.T. Vds Id 50KΩ Vgs 2V.2µF.3µF V GS D.U.T. V DS Vgs(th) 3mA I G I D Current Sampling Resistors Qgs Qgs2 Qgd Qgodr Fig 24a. Gate Charge Test Circuit Fig 24b. Gate Charge Waveform www.irf.com 7
D 2 Pak 7 Pin Package Outline Dimensions are shown in millimeters (inches) Note: For the most current drawing please refer to IR website at http://www.irf.com/package/ 8 www.irf.com
D 2 Pak 7 Pin Part Marking Information Ã4 D 2 Pak 7 Pin Tape and Reel Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/ Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (3) 25275 TAC Fax: (3) 2527903 Visit us at www.irf.com for sales contact information. 04/20 www.irf.com 9