Chapter 10 Differential Amplifiers

Chapter 10 Differential Amplifiers 10.1 General Considerations 10.2 Bipolar Differential Pair 10.3 MOS Differential Pair 10.4 Cascode Differential Amplifiers 10.5 Common-Mode Rejection 10.6 Differential Pair with Actie Load 1

Audio Amplifier Example An audio amplifier is constructed as aboe that takes a rectified AC oltage as its supply and amplifies an audio signal from a microphone. CH 10 Differential Amplifiers 2

Humming Noise in Audio Amplifier Example Howeer, V CC contains a ripple from rectification that leaks to the output and is perceied as a humming noise by the user. CH 10 Differential Amplifiers 3

Supply Ripple Rejection X Y X A r Y in A r in Since both node X and Y contain the same ripple, their difference will be free of ripple. CH 10 Differential Amplifiers 4

Ripple-Free Differential Output Since the signal is taken as a difference between two nodes, an amplifier that senses differential signals is needed. CH 10 Differential Amplifiers 5

Common Inputs to Differential Amplifier X Y X Ain Ain 0 Y r r Signals cannot be applied in phase to the inputs of a differential amplifier, since the outputs will also be in phase, producing zero differential output. CH 10 Differential Amplifiers 6

Differential Inputs to Differential Amplifier X Y X Y in A A in r 2A r in When the inputs are applied differentially, the outputs are 180 out of phase; enhancing each other when sensed differentially. CH 10 Differential Amplifiers 7

Differential Signals A pair of differential signals can be generated, among other ways, by a transformer. Differential signals hae the property that they share the same aerage alue (DC) to ground and AC alues are equal in magnitude but opposite in phase. CH 10 Differential Amplifiers 8

Single-ended s. Differential Signals CH 10 Differential Amplifiers 9

Example 10.3 Determine the common-mode leel at the output of the circuit shown in Fig. 10.3(b). In the absence of signals, VX VY VCC RC IC where RC RC1 RC 2 and I Q1 2 C denotes the bias current of and Q V V R I Thus, CM CC C C Interestingly, the ripple affects V CM but not the differential output. CH 10 Differential Amplifiers 10

Differential Pair With the addition of a tail current, the circuits aboe operate as an elegant, yet robust differential pair. CH 10 Differential Amplifiers 11

Common-Mode Response V I V BE1 C1 X V I V C 2 Y BE 2 V I 2 EE CC R C I 2 EE To aoid saturation, the collector oltages must not fall below the base oltages: I EE V R V 2 CC C CM CH 10 Differential Amplifiers 12

Example 10.4 A bipolar differential pair employs a load resistance of 1 kω and a tail current of 1 ma. How close to V CC can V CM be chosen? I VCC VCM RC 2 05V CM EE That is, V must remain below V by at least 0.5 V. CC CH 10 Differential Amplifiers 13

Common-Mode Rejection Due to the fixed tail current source, the input commonmode alue can ary without changing the output commonmode alue. CH 10 Differential Amplifiers 14

Differential Response I I I V V C1 C2 X Y I 0 V V EE CC CC R C I EE CH 10 Differential Amplifiers 15

Differential Response II I I V V C2 C1 Y X I 0 V V EE CC CC R C I EE CH 10 Differential Amplifiers 16

Differential Pair Characteristics None-zero differential input produces ariations in output currents and oltages, whereas common-mode input produces no ariations. CH 10 Differential Amplifiers 17

Example 10.5 A bipolar differential pair employs a tail current of 0.5 ma and a collector resistance of 1 kω. What is the maximum allowable base oltage if the differential input is large enough to completely steer the tail current? Assume V CC =2.5V. Because I EE is completely steered, V - R I 2 V at one collector. CC C EE To aoid saturation, V 2 V. B CH 10 Differential Amplifiers 18

Small-Signal Analysis I I C1 C 2 I 2 I 2 EE EE I I Since the input to Q 1 and Q 2 rises and falls by the same amount, and their emitters are tied together, the rise in I C1 has the same magnitude as the fall in I C2. CH 10 Differential Amplifiers 19

Virtual Ground IC1 gm( V VP ) IC 2 gm( V VP ) I C 2 IC1 0 g ( V V ) g ( V V ) m P m P V I I P C1 C 2 0 g m g V m V For small changes at inputs, the g m s are the same, and the respectie increase and decrease of I C1 and I C2 are the same, node P must stay constant to accommodate these changes. Therefore, node P can be iewed as AC ground. CH 10 Differential Amplifiers 20

Small-Signal Differential Gain VX gmvrc VY gmvrc V V 2g VR X Y m C A 2g mvr 2V C g m R C Since the output changes by -2g m VR C and input by 2V, the small signal gain is g m R C, similar to that of the CE stage. Howeer, to obtain same gain as the CE stage, power dissipation is doubled. CH 10 Differential Amplifiers 21

Example 10.6 Design a bipolar differential pair for a gain of 10 and a power budget of 1mW with a supply oltage of 2V. V CC 2 V 1 mw I EE 0.5 ma 2 V IC I EE / 2 0.25 ma 1 gm V V 26 mv 104 T A RC 1040 g m T CH 10 Differential Amplifiers 22

Example 10.7 Compare the power dissipation of a bipolar differential pair with that of a CE stage if both circuits are designed for equal oltage gains, collector resistances, and supply oltages. Differential pair CE stage AV diff gm 12RC AV CE gmrc g R g R m12 C m C I 2V I EE EE T I V 2I PD, diff VC I EE 2V CIC P, C T C V I D CE C C CH 10 Differential Amplifiers 23

Large Signal Analysis V V V V in1 in2 BE1 BE 2 C1 C2 EE C1 C2 T S1 IS 2 in1 in2 C2 C2 EE VT CH 10 Differential Amplifiers 24 and C2 C1 V T ln in1 in2 in1 in2 in1 in2 ln V V I exp I I I I I I I I I I V 1 exp EE V IEE exp V 1 exp V V V T V VT V V T I

Example 10.8 Determine the differential input oltage that steers 98% of the tail current to one transistor. I 1 002I EE V V I exp in EE V C 1 in 2 Vin 1 Vin2 391VT T We often say a differential input of 4V T is sufficient to turn one side of the bipolar pair nearly off. CH 10 Differential Amplifiers 25

Input/Output Characteristics V V R I out1 CC C C1 out 2 CC C C 2 V exp V 1 exp I V 1 exp in1 in2 in1 in2 in1 in2 CH 10 Differential Amplifiers 26 V CC CC R C V V R I V R V V R I C out1 out 2 C EE R I C I EE EE V 1 exp V 1 exp EE V VT V V T V V T V VT V V in1 in2 in1 in2 T V V tanh 2V in1 in2 T

Example 10.9 Sketch the output waeforms of the bipolar differential pair in Fig. 10.14(a) in response to the sinusoidal inputs shown in Figs. 10.14(b) and (c). Assume Q 1 and Q 2 remain in the forward actie region. Figure10.14 (a) CH 10 Differential Amplifiers 27

Example 10.9 (cont d) The left column operates in linear region (small-signal), whereas the right column operates in nonlinear region (large-signal). CH 10 Differential Amplifiers 28

Small-Signal Model r in1 1 P in2 2 g g 0 1 2 m1 1 m2 2 1 r 2 r 1 r 2 gm 1 gm2 With and 1 2 0 2in 1 2 1 Since in1 in2,. P in1 1 CH 10 Differential Amplifiers 29

Half Circuits out1 in1 out 2 in2 g m R C Since V P is grounded, we can treat the differential pair as two CE half circuits, with its gain equal to one half circuit s single-ended gain. CH 10 Differential Amplifiers 30

Example 10.10 Compute the differential gain of the circuit shown in Fig. 10.16(a), where ideal current sources are used as loads to maximize the gain. Figure10.16 (a) out1 in1 out 2 in 2 g m r O CH 10 Differential Amplifiers 31

Example 10.11 Figure 10.17(a) illustrates an implementation of the topology shown in Fig. 10.16(a). Calculate the differential oltage gain. Figure10.17 (a) out1 out 2 in1 in 2 CH 10 Differential Amplifiers 32 g r r m ON OP

Extension of Virtual Ground V X 0 It can be shown that if R 1 = R 2, and points A and B go up and down by the same amount respectiely, V X does not moe. This property holds for any other node that appears on the axis of symmetry. CH 10 Differential Amplifiers 33

Half Circuit Example I A g CH 10 Differential Amplifiers 34 m1 ro 1 ro 3 R 1

Half Circuit Example II A g CH 10 Differential Amplifiers 35 m1 ro 1 ro 3 R 1

Half Circuit Example III A CH 10 Differential Amplifiers 36 R E R C 1 g m

Half Circuit Example IV A E 2 CH 10 Differential Amplifiers 37 R R C 1 g m

I/O Impedances i X X 1 2 X 1 r 2 r X i 1 2 2r i 1 X X Rin 2r i X 1 i X i X In a similar manner, R out 2R C CH 10 Differential Amplifiers X 38

MOS Differential Pair s Common-Mode Response I I D1 D2 I 2 SS V V V R X Y DD D I 2 SS Similar to its bipolar counterpart, MOS differential pair produces zero differential output as V CM changes. CH 10 Differential Amplifiers 39

Equilibrium Oerdrie Voltage I D ISS 2 1 W C V V 2 L n ox GS TH V V GS TH equil n I C 2 SS ox W L The equilibrium oerdrie oltage is defined as the oerdrie oltage seen by M 1 and M 2 when both of them carry a current of I SS /2. CH 10 Differential Amplifiers 40

Minimum Common-mode Output Voltage V DD R D I 2 SS V CM V TH In order to maintain M 1 and M 2 in saturation, the commonmode output oltage cannot fall below the alue aboe. This alue usually limits oltage gain. CH 10 Differential Amplifiers 41

Example 10.15 A MOS differential pair is drien with an input CM leel of 1.6V. If I SS =0.5mA, V TH =0.5 V, and V DD =1.8 V, what is the maximum allowable load resistance? ISS V R V V 2 V V V RD 2 I DD D CM TH 2.8 k DD CM TH SS CH 10 Differential Amplifiers 42

Differential Response CH 10 Differential Amplifiers 43

Small-Signal Response V P 0 I g V, D1 D2 m I g V m V V 2g R V A X Y m D g R m D Similar to its bipolar counterpart, the MOS differential pair exhibits the same irtual ground node and small signal gain. CH 10 Differential Amplifiers 44

Power and Gain Tradeoff In order to obtain the same gain as a CS stage, a MOS differential pair must dissipate twice the amount of current. This power and gain tradeoff is also echoed in its bipolar counterpart. CH 10 Differential Amplifiers 45

Example 10.16 Design an NMOS differential pair for a oltage gain of 5 and a power budget of 2 mw subject to the condition that the stage following the differential pair requires an output CM leel of at least 1.6V. Assume μ n C ox =100 μa/v 2, λ=0, and V DD = 1.8 V. 2 mw ISS 1 11 ma 1.8 V ISS VCM, out VDD RD 1.6 V 2 R 360 D Textbook Error! For R 360, A 5 W I 2 C R 360 L 2 1738 CH 10 Differential Amplifiers 46 g D m n ox D W L SS

Example 10.17 What is the maximum allowable input CM leel in the preious example if V TH =0.4 V? To guarantee that M and M operate in saturation, I V V R V 2 V V. 1 2 SS CM, in DD D TH Thus, V CM, in CM, out 2 V TH CH 10 Differential Amplifiers 47

Example 10.18 The common-source stage and the differential pair shown in Fig. 10.28 incorporate equal load resistors. If the two circuits are designed for the same oltage gain and the same supply oltage, discuss the choice of (a) transistor dimensions for a gien power budget, (b) power dissipation for gien transistor dimensions. Figure10.28 3 (a) for same power budget, I I 2I 2I D1 SS D2 D3 W 1 W 1 W L 2 L 2 L 1 2 1 2 3 W gm 2nCox ID L (b) for same transistor dimensions, diff CS CH 10 Differential Amplifiers 48 I P SS 2I D1 2P 3

MOS Differential Pair s Large-Signal Response Goal is to obtain I D1 - I D2 V V V V. in1 GS1 in2 GS 2 I I I D1 D2 SS I C W L V V 2 D (1 2) n ox ( )( GS TH ). 2I D VGS VTH W ncox L V V V V in1 in2 GS1 GS 2 2 ( I D1 I D2 ) W ncox L CH 10 Differential Amplifiers 49

MOS Differential Pair s Large-Signal Response (cont d) 2 2 ( Vin 1 Vin2) ( I D1 I D2 2 I D1ID2 ) W ncox L 2 ( ISS 2 I D1I D2 ) W ncox L W 4 ID1I D2 2 ISS ncox ( Vin 1 Vin 2) L W 16I I 2 I C ( V V ) D1 D2 SS n ox in1 in2 L 2 2 2 W 16 I ( I I ) 2 I C ( V V ) D1 SS D1 SS n ox L in1 in2 2 2 CH 10 Differential Amplifiers 50

MOS Differential Pair s Large-Signal Response (cont d) 2 2 W 2 D1 SS D1 SS n ox in1 in2 L 16I 16I I 2 I C ( V V ) 0 2 ISS 1 2 2 1 4 W D SS n ox ( in1 in2 ) 2 SS 2 4 L I I C V V I I V V W 4 W ( ) 4 L SS 2 in1 in2 ncox ISS ncox L Vin 1 Vin2 2 I V I V C W 4 I C W ( V V ) D2 ox 4 L SS 2 in2 in1 n SS n ox L in2 in1 ( the symmetry of the circuit) 2 I D1 I D2 1 nc 2 ox W L 4I SS V V V V 2 in1 in 2 in1 in2 C n ox W L CH 10 Differential Amplifiers 51

Maximum Differential Input Voltage Edge of Conduction ~0 I SS + + V TH - - V GS2 V V GS1 GS 2 V V TH TH 2I SS C n ox W L 2I V V 2 V V W nc ox L SS in1 in 2 max GS TH equil There exists a finite differential input oltage that completely steers the tail current from one transistor to the other. This alue is known as the maximum differential input oltage. CH 10 Differential Amplifiers 52

Contrast Between MOS and Bipolar Differential Pairs MOS Bipolar In a MOS differential pair, there exists a finite differential input oltage to completely switch the current from one transistor to the other, whereas, in a bipolar pair that oltage is infinite. CH 10 Differential Amplifiers 53

The effects of Doubling the Tail Current Since I SS is doubled and W/L is unchanged, the equilibrium oerdrie oltage for each transistor must increase by 2 to accommodate this change, thus V in,max increases by 2 as well. Moreoer, since I SS is doubled, the differential output swing will double. CH 10 Differential Amplifiers 54

The effects of Doubling W/L Since W/L is doubled and the tail current remains unchanged, the equilibrium oerdrie oltage will be lowered by 2 to accommodate this change, thus V in,max will be lowered by as well. Moreoer, the differential output swing will remain unchanged since neither I SS nor R D has changed CH 10 Differential Amplifiers 55

Example 10.20 Design an NMOS differential pair for a power budget of 3 mw and V in,max =500 mv. Assume μ n C ox =100 μa/v 2 and V DD =1.8 V. I SS From 3 mw 1.67 ma 1.8 V in1 in2 max W 2I L C V R D V V SS 2 n ox in,max 133.6 2I C is determined by the required oltage gain. n SS ox W L CH 10 Differential Amplifiers 56

Small-Signal Analysis of MOS Differential Pair 1 W 4I I I C V V V V 2 L W ncox L SS D1 D2 n ox in1 in2 in1 in2 1 W C V V 2 L n ox in1 in2 W C I V V L n ox SS in1 in2 When the input differential signal is small compared to [4I SS / n C ox (W/L)] 1/2, the output differential current is linearly proportional to it, and small-signal model can be applied. CH 10 Differential Amplifiers 57 4I C n SS ox W L 2

Virtual Ground and Half Circuit V A P 0 g R m D Applying the same analysis as the bipolar case, we will arrie at the same conclusion that node P will not moe for small input signals and the concept of half circuit can be used to calculate the gain. CH 10 Differential Amplifiers 58

MOS Differential Pair Half Circuit Example I A 0 g m 1 1 ro 3 r g m3 CH 10 Differential Amplifiers 59 O1

MOS Differential Pair Half Circuit Example II 0 A CH 10 Differential Amplifiers 60 g g m1 m3

MOS Differential Pair Half Circuit Example III A 0 R CH 10 Differential Amplifiers 61 SS R 2 DD 2 1 g m

Bipolar Cascode Differential Pair A g g r r r r r m1 m3 O1 3 O 3 O1 3 CH 10 Differential Amplifiers 62

Output Impedance of CE Stage with Degeneration i g r X X m O ix gmix RE r ro ix RE r R 1 g ( R r ) r R r out m E O E r ( g r 1)( R r ) O m O E r 1 g ( R r ) O m E CH 10 Differential Amplifiers 63

Output Impedance of CS Stage with Degeneration i g i g i R i g i R X m 1 X m X S X m X S r i g i R i R O X m X S X S X R r 1 g R R out O m S S 1 g r R r g r R m O S O r m O S O CH 10 Differential Amplifiers 64

CH 10 Differential Amplifiers 65 Bipolar Telescopic Cascode ) ( 5 7 5 5 3 1 3 3 1 r r r g r r r g g A O O m O O m m

Example: Bipolar Telescopic Parasitic Resistance R R R r 1 g r r r r 2 2 1 1 op O5 m5 O 7 5 O 7 5 A g m1 g m3ro 3( ro 1 r 3) R op CH 10 Differential Amplifiers 66

MOS Cascode Differential Pair A g m1 O3 m3 O1 CH 10 Differential Amplifiers 67 r g r

MOS Telescopic Cascode A g g r r CH 10 Differential Amplifiers 68 ( g r r m5 O5 7 m1 m3 O3 O1 O )

Example: MOS Telescopic Parasitic Resistance CH 10 Differential Amplifiers 69 R 1 g r R r r R A g ( R r g r ) op m5 O 5 1 O 7 O 5 1 m1 op O 3 m3 O1

Effect of Finite Tail Impedance V V out, CM in, CM R EE RC / 2 1/ 2g m If the tail current source is not ideal, then when a input CM oltage is applied, the currents in Q 1 and Q 2 and hence output CM oltage will change. CH 10 Differential Amplifiers 70

Input CM Noise with Ideal Tail Current CH 10 Differential Amplifiers 71

Input CM Noise with Non-ideal Tail Current CH 10 Differential Amplifiers 72

Comparison As it can be seen, the differential output oltages for both cases are the same. So for small input CM noise, the differential pair is not affected. CH 10 Differential Amplifiers 73

1 W 2 I D1 ncox VGS1 VTH 2 L 1 W 2 I D2 ncox VGS 2 VTH 2 L I I & I I, V V CM to DM Conersion, A CM-DM D1 D2 D1 D2 GS1 GS 2 Textbook Error! V V 2I R CM GS D SS 1 I I D 2 RSS, VGS gm g VCM I D 1 2RSS g V V V out out1 out 2 VCM 1/ g 2R V R R V 1/ g 2R 2R If finite tail impedance and asymmetry are both present, then the differential output signal will contain a portion of input common-mode signal. CH 10 Differential Amplifiers 74 m I R I R R I D D D D D D R m D SS out D D CM m SS SS R D D m

Example: A CM-DM A CM DM 1 g m1 2 [1 g m3 R ( R 1 C r )] r R 3 O3 1 r 3 CH 10 Differential Amplifiers 75

CMRR CMRR A A DM CM DM CMRR defines the ratio of wanted amplified differential input signal to unwanted conerted input common-mode noise that appears at the output. CH 10 Differential Amplifiers 76

Example 10.28 Calculate the CMRR of the circuit in Fig. 10.46. Figure10.46 A DM m1 C CMRR A CM DM A CM DM g R g R 1 m1 C 2 [1 gm3( R1 r 3)] ro 3 R1 r 3 RC gm 1 CH 10 Differential Amplifiers 77

Differential to Single-ended Conersion Many circuits require a differential to single-ended conersion, howeer, the aboe topology is not ery good. CH 10 Differential Amplifiers 78

Supply Noise Corruption The most critical drawback of this topology is supply noise corruption, since no common-mode cancellation mechanism exists. Also, we lose half of the signal. CH 10 Differential Amplifiers 79

Better Alternatie This circuit topology performs differential to single-ended conersion with no loss of gain. CH 10 Differential Amplifiers 80

Actie Load With current mirror used as the load, the signal current produced by the Q 1 can be replicated onto Q 4. This type of load is different from the conentional static load and is known as an actie load. CH 10 Differential Amplifiers 81

Differential Pair with Actie Load The input differential pair decreases the current drawn from R L by I and the actie load pushes an extra I into R L by current mirror action; these effects enhance each other. CH 10 Differential Amplifiers 82

Actie Load s. Static Load The load on the left responds to the input signal and enhances the single-ended output, whereas the load on the right does not. CH 10 Differential Amplifiers 83

MOS Differential Pair with Actie Load Similar to its bipolar counterpart, MOS differential pair can also use actie load to enhance its single-ended output. CH 10 Differential Amplifiers 84

Asymmetric Differential Pair Because of the astly different resistance magnitude at the drains of M 1 and M 2, the oltage swings at these two nodes are different and therefore node P cannot be iewed as a irtual ground when V in2 =-V in1. CH 10 Differential Amplifiers 85

Quantitatie Analysis - Approach 1 M 4 3 r OP 1 g mp i i & i g r 1 X Y A X mp OP CH 10 Differential Amplifiers 86 A gmpa A i r i X Y ON N r N ON r OP M M1 M 2 i g g i g r i out out 1 Y mp A mp X mp OP X rop rop i X out r 1 g g r 1 OP mp mp OP out

Quantitatie Analysis - Approach 1 cont d 1 2 i g r i g r A X mn ON Y mn ON out 2i r g r 0 A X ON mn ON in1 in2 out & i i Substituting for and i, out 1 2 in1 in2 X Y A X 1 g r 2r 1 mp OP ON 1 r 1 g g r r 1 g g r g r OP mp mp OP OP mp mp OP 1 out OP mp mp OP gmnr ON in1 in2 2 ON 2 OP mn ON OP r 1 g g r r r g r r 0 out out mn ON in1 in2 CH 10 Differential Amplifiers 87

Quantitatie Analysis - Approach 2 i X X i X 1 2 Textbook Error! + - Textbook Error! g r ( ) The mn on in1 in2 R The 2r on & i g r i g r 1 2 X m1 1 O1 X m2 2 O2 X CH 10 Differential Amplifiers 88

Quantitatie Analysis - Approach 2 cont d 1 r 1 ro 3 RThe g g O3 gm3 A out The m4 A m3 out out The 0 r 1 O4 ro 3 RThe g m3 1 ro 3 g 3 1 m out gm4 out The 0 1 1 r O4 O3 RThe r r O3 R The gm3 g m3 2 1 0 ( r R and g g ) R r g out out The O3 The m3 m4 The O4 m3 1 1 g r out ron rop ron out gmn ron rop in1 in2 CH 10 Differential Amplifiers 89 + - mn ON in1 in2

Example 10.29 Proe that the oltage swing at node A is much less than that at the output. A I out I gm4 ro 4 A 1 out A gm4a ro 3 ro 4 gm3 out m4 A O4 gm3 out A ro 4gm3 A r 2r g out g O4 m3 A 1 CH 10 Differential Amplifiers 90